CN112198428A

CN112198428A - Method and system for testing response time of radio frequency switch chip

Info

Publication number: CN112198428A
Application number: CN202011389499.1A
Authority: CN
Inventors: 刘旭伟; 莫松安; 谷颜秋
Original assignee: Foshan Linkage Technology Co ltd
Current assignee: Foshan Linkage Technology Co ltd
Priority date: 2020-12-02
Filing date: 2020-12-02
Publication date: 2021-01-08
Anticipated expiration: 2040-12-02
Also published as: CN112198428B

Abstract

The invention discloses a method and a system for testing the response time of a radio frequency switch chip, wherein the method comprises the steps that an ATE radio frequency signal source outputs a transmitting signal to a radio frequency switch to be tested at a preset frequency and power; the digital signal processor outputs a DUT control signal to the radio frequency switch to be tested so as to control the state of the radio frequency switch to be tested; the ATE radio frequency receiver receives a transmitting signal output by a radio frequency switch to be tested, processes the received signal and sends the processed receiving signal to the digital signal processor; the digital signal processor processes the processed received signal and outputs a test result; the system comprises a digital signal processor, an ATE radio frequency signal source, an ATE radio frequency receiver and a radio frequency switch to be tested. The invention is processed in digital domain on the basis of the signal receiver, is not influenced by the time response of the detector and the analysis bandwidth of the oscilloscope, can process the signal bandwidth, improves the test rate of ATE equipment and reduces the complexity of hardware.

Description

Method and system for testing response time of radio frequency switch chip

Technical Field

The invention relates to the technical field of switch testing, in particular to a method and a system for testing the response time of a radio frequency switch chip.

Background

The time response of the radio frequency switch is an important index of the radio frequency switch chip, and can completely represent the opening and closing speed and the signal stabilization time of the radio frequency switch chip. In the rf switching time response test, there are two main categories, i.e., the switching response time, which is divided into the on time (tON) and the off time (tOFF), and the power response time, which is divided into the power rise time (trese) and the power fall time (tFALL). These tests are performed on the power values (envelopes) of the control signal and the input/output rf signal, and represent the on/off time and the signal settling time, respectively.

The current methods for testing the time response of the radio frequency switch chip mainly comprise two methods, one method is to adopt a detector form to detect the power of a radio frequency signal into a voltage signal and then detect and analyze the voltage signal. The other is to use an oscilloscope mode, and the real-time envelope of the signal can be directly displayed on a screen by using the low-bandwidth detection characteristic of the oscilloscope, and at this time, the bandwidth of the oscilloscope is required to be larger than the receiving frequency in order to completely receive the signal.

The problem of the time response test mode of the detector is the time response problem of the detector. The function of the detector is to convert the power signal of the radio frequency signal into a voltage signal, and during the conversion, there is a conversion delay which can be reflected in the rising edge or the falling edge of the voltage signal, and when the rising edge or the falling edge of the DUT (device under test) is much slower than the detector, the delay of the detector can be reflected as an error signal to the test result of the DUT, but when the response time of the DUT is not much different from the response time of the detector, the delay of the detector is superimposed on the response of the DUT, thereby causing the wrong test result of the DUT.

When the oscilloscope is used for testing, only frequency signals in the bandwidth of the oscilloscope can be used for testing under the influence of the bandwidth of the oscilloscope, or only the oscilloscope with higher bandwidth can be used for testing in order to realize the high-frequency response time test, so that the system testing cost and complexity are greatly increased.

Disclosure of Invention

The invention provides a method and a system for testing the response time of a radio frequency switch chip, which are used for solving one or more technical problems in the prior art and at least providing a beneficial selection or creation condition.

In a first aspect, an embodiment of the present invention provides a method for testing response time of a radio frequency switch chip, where the method includes:

the ATE radio frequency signal source outputs a transmitting signal to the radio frequency switch to be tested at a preset frequency and power;

the digital signal processor outputs a DUT control signal to the radio frequency switch to be tested so as to control the state of the radio frequency switch to be tested;

the ATE radio frequency receiver receives a transmitting signal output by a radio frequency switch to be tested, processes the received signal and sends the processed receiving signal to the digital signal processor;

the digital signal processor processes the processed received signal and outputs a test result;

the digital signal processor comprises a ping-pong FIFO, a digital multiplier, a digital low-pass filter, a signal synthesis module and a signal detection calculation module, wherein the digital signal processor processes the processed received signal, and the outputting of the test result comprises:

the processed received signals are written into a ping-pong FIFO, and the ping-pong FIFO outputs the written signals to a digital multiplier as two paths of same signals at a preset speed;

the digital multiplier multiplies the two paths of same signals to obtain a squaring signal, and sends the squaring signal to the digital low-pass filter;

the digital low-pass filter filters the squaring signal, the direct current signal of the squaring signal is reserved, the high-frequency signal is filtered to obtain a filtering signal, and the filtering signal is output to the signal synthesis module;

the signal synthesis module synthesizes the filtering signals at different moments to obtain a synthesized signal, and outputs the synthesized signal to the signal detection and calculation module;

and when the amplitude of the synthesized signal is detected to be reduced to be unchanged, the closing time and the power falling time of the radio frequency switch to be detected are determined according to the recorded time point of the DUT control signal acting on the radio frequency switch to be detected to close the radio frequency switch to be detected.

Further, the writing of the processed received signal into the ping-pong FIFO, the ping-pong FIFO outputting the written signal as two identical signals to the digital multiplier at a predetermined rate, comprises:

the ping-pong FIFO writes the processed received signals in a time domain crossing mode, namely when the first FIFO writes data, the second FIFO outputs the data stored in the second FIFO to the digital multiplier as two paths of same data at a preset rate, when the second FIFO writes data, the first FIFO outputs the data stored in the first FIFO to the digital multiplier as two paths of same data at a preset rate, the data written in the first FIFO and the second FIFO have an overlapping part in the time domain, the storage sizes of the first FIFO and the second FIFO are equal, and the data output is carried out only after the first FIFO or the second FIFO is full of data.

Further, the digital multiplier multiplies two paths of same signals to obtain a self-multiplication signal, which specifically comprises:

the input signal of the digital multiplier is

；

The squaring signal is:

；

namely:

；

wherein the content of the first and second substances,

which is the amplitude of the signal, t represents time,

the angular frequency is represented by the angular frequency,

representing the phase angle.

Further, the digital low-pass filter filters the squaring signal, the direct current signal of the squaring signal is reserved, and the high-frequency signal is filtered to obtain a filtering signal which specifically comprises:

digital low-pass filter pair squaring signal

Filtering is carried out;

the DC signal of the squaring signal is retained, and the high-frequency signal is filtered to obtain a filtering signal of

。

Further, when it is detected that the amplitude of the synthesized signal is increased to be unchanged, determining the turn-on time and the power rise time of the radio frequency switch to be tested according to the recorded time point of the DUT control signal acting on the radio frequency switch to be tested to turn on the radio frequency switch to be tested specifically as follows:

when it is detected that the amplitude of the synthesized signal increases to be constant, a time point T1 at which the amplitude of the synthesized signal increases to be constant is acquired;

acquiring a recorded time point T2 when the DUT control signal acts on the radio frequency switch to be tested to enable the radio frequency switch to be tested to be conducted;

acquiring a rising start time point T3;

the on time tON of the radio frequency switch is: tON = (T1-T0) -T2;

the power rise time, tRISE, is: tRISE = (T1-T0) - (T3-T0) = T1-T3;

wherein t0 is the total time delay of the signal passing through the ping-pong FIFO, the digital multiplier and the digital low-pass filter in sequence.

Further, when it is detected that the amplitude of the synthesized signal is reduced to be unchanged, determining the closing time and the power down time of the radio frequency switch to be tested according to the recorded time point when the DUT control signal acts on the radio frequency switch to be tested to close the radio frequency switch to be tested specifically as follows:

when it is detected that the amplitude of the synthesized signal decreases to be constant, a time point T4 at which the amplitude of the synthesized signal decreases to be constant is acquired;

acquiring a recorded time point T5 when a DUT control signal acts on a radio frequency switch to be tested to close the radio frequency switch;

acquiring an amplitude reduction starting time point T6 of the synthesized signal;

the off time tOFF of the radio frequency switch is: tOFF = (T4-T0) -T5;

the power fall time tFALL is: tFALL = (T4-T0) - (T6-T0) = T4-T6;

Further, the method further comprises: and the digital signal processor respectively controls the working states of the ATE radio frequency signal source and the ATE radio frequency receiver.

In a second aspect, an embodiment of the present invention further provides a system for testing response time of a radio frequency switch chip, where the system includes a digital signal processor, an ATE radio frequency signal source, an ATE radio frequency receiver, and a radio frequency switch to be tested; the ATE radio frequency signal source is connected with the digital signal processor, the output end of the ATE radio frequency signal source is connected with the input end of the radio frequency switch to be tested, the multi-path output of the radio frequency switch to be tested is connected with the ATE receiver, the control end of the radio frequency switch to be tested is connected with the digital signal processor, and the output end of the ATE receiver is connected with the digital signal processor;

the ATE radio frequency signal source is used for outputting a transmitting signal to the radio frequency switch to be tested at a preset frequency and power;

the digital signal processor is used for outputting a DUT control signal to the radio frequency switch to be tested so as to control the conducting state of the radio frequency switch to be tested;

the ATE radio frequency receiver is used for receiving the transmitting signal output by the radio frequency switch to be tested, processing the received signal and sending the processed receiving signal to the digital signal processor;

the digital signal processor is also used for processing the processed received signal and outputting a test result;

the digital signal processor comprises a ping-pong FIFO, a digital multiplier, a digital low-pass filter, a signal synthesis module and a signal detection calculation module, and is used for processing the processed received signal, and outputting a test result, wherein the digital signal processor comprises:

a ping-pong FIFO for writing the processed received signal and outputting the written signal as two paths of same signals to a digital multiplier at a predetermined rate;

the digital multiplier is used for multiplying the two paths of same signals to obtain a squaring signal and sending the squaring signal to the digital low-pass filter;

the digital low-pass filter is used for filtering the squaring signal, reserving the direct-current signal of the squaring signal, filtering the high-frequency signal to obtain a filtering signal, and outputting the filtering signal to the signal synthesis module;

the signal synthesis module is used for synthesizing the filtering signals at different moments and outputting the synthesized signals to the signal detection and calculation module;

and the signal detection calculation module is used for detecting the synthesized signal, determining the turn-on time and the power rise time of the radio frequency switch to be tested according to the recorded time point when the DUT control signal acts on the radio frequency switch to be tested to enable the radio frequency switch to be conducted when the amplitude of the synthesized signal is detected to be increased to be unchanged, and determining the turn-off time and the power fall time of the radio frequency switch to be tested according to the recorded time point when the DUT control signal acts on the radio frequency switch to be tested to enable the radio frequency switch to be turned off when the amplitude of the synthesized signal is detected to be reduced to be unchanged.

The method and the system for testing the response time of the radio frequency switch chip, provided by the embodiment of the invention, have the following beneficial effects at least: the invention can be realized in the digital domain by completely utilizing the existing receiver without additionally adding hardware, can process the signal bandwidth, is convenient for system integration and miniaturization, can improve the test speed of ATE equipment, and reduces the complexity of ATE system construction and the system cost, thereby improving the test precision, improving the integration degree of the system and reducing the hardware complexity.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the example serve to explain the principles of the invention and not to limit the invention.

Fig. 1 is a flowchart of a method for testing response time of an rf switch chip according to an embodiment of the present invention;

FIG. 2 is a flow chart of a digital signal processor for processing signals to obtain test results according to an embodiment of the present invention;

FIG. 3 is a waveform diagram generated in a method for testing response time of an RF switch chip according to an embodiment of the present invention;

FIG. 4 is a flow chart of a method for testing response time of an RF switch chip according to another embodiment of the present invention;

fig. 5 is a schematic structural diagram of a system for testing response time of an rf switch chip according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It should be noted that although functional block divisions are provided in the system drawings and logical orders are shown in the flowcharts, in some cases, the steps shown and described may be performed in different orders than the block divisions in the systems or in the flowcharts. The terms first, second and the like in the description and in the claims, and the drawings described above, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The embodiments of the present invention will be further explained with reference to the drawings.

As shown in fig. 1, fig. 1 is a flowchart of a method for testing response time of a radio frequency switch chip according to an embodiment of the present invention, where the method includes the following steps:

s101, outputting a transmitting signal to a radio frequency switch to be tested by an ATE radio frequency signal source at a preset frequency and power;

s102, the digital signal processor outputs a DUT control signal to the radio frequency switch to be tested so as to control the state of the radio frequency switch to be tested;

s103, receiving a transmitting signal output by the radio frequency switch to be tested by the ATE radio frequency receiver, processing the received signal, and sending the processed receiving signal to the digital signal processor;

and S104, processing the processed received signal by the digital signal processor, and outputting a test result.

Specifically, controlling the state of the radio frequency switch to be tested comprises controlling the radio frequency switch to be tested to be switched on and controlling the radio frequency switch to be tested to be switched off, and testing the response time of the radio frequency switch to be tested is realized by controlling the state of the radio frequency switch to be tested.

Further, the digital signal processor includes a ping-pong FIFO, a digital multiplier, a digital low-pass filter, a signal synthesis module, and a signal detection calculation module, as shown in fig. 2, the digital signal processor processes the processed received signal, and outputting a test result includes the following steps:

s201, writing the processed received signals output by the ATE radio frequency receiver into a ping-pong FIFO, and outputting the written signals to a digital multiplier as two paths of same signals at a preset rate by the ping-pong FIFO;

s202, multiplying two paths of same signals by a digital multiplier to obtain a squaring signal, and sending the squaring signal to a digital low-pass filter;

s203, filtering the squaring signal by a digital low-pass filter, reserving the direct-current signal of the squaring signal, filtering the high-frequency signal to obtain a filtering signal, and outputting the filtering signal to a signal synthesis module;

s204, the signal synthesis module synthesizes the filtering signals at different moments and outputs the synthesized signals to the signal detection and calculation module;

s205, the signal detection and calculation module detects the synthesized signal, determines the turn-on time and the power rise time of the radio frequency switch to be tested according to the recorded time point when the amplitude of the synthesized signal is increased to be unchanged and the radio frequency switch to be tested is acted by the DUT control signal to be conducted, and determines the turn-off time and the power fall time of the radio frequency switch to be tested according to the recorded time point when the amplitude of the synthesized signal is reduced to be unchanged and the radio frequency switch to be tested is acted by the DUT control signal to be closed.

Specifically, the ping-pong FIFO is different from a conventional ping-pong FIFO in that two FIFOs of the ping-pong FIFO are not time-domain aligned but time-domain interleaved in order to compensate for the problem that a large number of bits in front of an output data string of a subsequent digital low-pass filter are invalid. The ping-pong FIFO can feed all rates of the sampled signal to the digital multiplier at the same high rate.

Step S201 specifically includes: the ping-pong FIFO writes the processed received signals in a time domain crossing mode, namely when the first FIFO writes data, the second FIFO outputs the data stored in the second FIFO to the digital multiplier as two paths of same data at a preset rate, when the second FIFO writes data, the first FIFO outputs the data stored in the first FIFO to the digital multiplier as two paths of same data at a preset rate, the data written in the first FIFO and the second FIFO have an overlapping part in the time domain, the storage sizes of the first FIFO and the second FIFO are equal, and the data output is carried out only after the first FIFO or the second FIFO is full of data.

For example, ping-pong FIFO needs to store a predetermined amount of data, 100 first FIFO and second FIFO can store, then 1-100 data are written into the first FIFO, after the first FIFO is full, the data are output to the multiplier at a predetermined high speed, the data multiplier and the digital low pass filter process the 1-100 data, when the first FIFO outputs data, 91-190 data are written into the second FIFO, after the second FIFO is full, the data are output to the multiplier at a predetermined high speed, and simultaneously 181-280 data are written into the first FIFO, and the writing and reading are repeated and alternated until all data are read.

Further, in step S202, the step of multiplying the two identical signals by the digital multiplier to obtain a squared signal includes:

the input data of the digital multiplier is

；

The squaring signal is:

；

namely:

；

wherein the content of the first and second substances,

which is the amplitude of the signal, t represents time,

the angular frequency is represented by the angular frequency,

representing the phase angle.

When the first FIFO or the second FIFO is full, the signals are sent to a digital multiplier to multiply two same signals, and when the signals are not stable in the opening process of the radio frequency switch

Is time-varying, as shown in fig. 3 for the first half of the real-time sampled signal 1, and the real-time sampled signal 2, when the rf switch state is fixed,

the second half of the signal 2 is sampled in real time as shown in the figure for a fixed signal.

The first part of the expression is a direct current signal, the second part is a radio frequency high frequency signal, and as shown in fig. 3, the squaring signal 1 and the squaring signal 2 are the result of squaring the real-time sampling signal 1 and the real-time sampling signal 2, respectively.

Digital multiplier output signal

Is fed into a digital low-pass filter, pair

Filtering is carried out to

The DC signal is retained, the high-frequency signal is filtered out, and the output filtering signal is recorded as

Then, then

As shown in fig. 3, the filtered signal 1 and the filtered signal 2 are the filtered output results of the squaring signal 1 and the squaring signal 2, respectively. Because the initial part data of the digital filter is incomplete and the digital filter has different response characteristics, the initial part of the output of the filtering signal is inaccurate, as shown in the first half part of the filtering signal 1 and the filtering signal 2, in order to make up for the inaccurate characteristics of the initial data, a time domain cross sampling mode is adopted for processing at the ping-pong FIFO.

Filtering signals of different sampling time

Sending the signals to a signal synthesis module for short sampling times

Time domain synthesis of the synthesized signal

As shown by the composite signal in fig. 3. Since the ping-pong FIFOs are interleaved in the time domain during sampling, there is also a signal interleaving during signal synthesis, as shown by the position of the junction of two signals in the synthesized signal in fig. 3, which deals with the data error at the beginning of the second data processing.

Will synthesize the signal

And sending the signals to a signal detection and calculation module, wherein the signal detection and calculation module simultaneously records the time point of the DUT control signal acting on the radio frequency switch to be detected, when the DUT control signal starts triggering the radio frequency switch to be detected to be opened, the digital signal processor simultaneously starts to receive the signals, and after the radio frequency switch to be detected is switched on from off, when the signal detection and calculation module detects that the amplitude of the input signal is increased to be unchanged, the on time (tON) and the power rise time (tRISE) of the radio frequency switch can be obtained from the synthesized signal. Similarly, after the radio frequency switch to be tested is switched from on to off, when the signal detection and calculation module detects that the amplitude of the input signal is reduced to be unchanged, the off time (tOFF) and the power down time (tFALL) of the radio frequency switch can be obtained from the synthesized signal. It should be noted that the step of testing the on time and the power rise time of the rf switch to be tested and the step of testing the off time and the power fall time of the rf switch to be tested are two independent testing steps, and the testing of the on time and the power rise time may be performed first, or the testing of the off time and the power fall time may be performed first.

The abscissa in fig. 3 represents the number of sampled points, for example 1000 represents the 1000 th sample point, and the ordinate represents the value of the sample, which is also a representation of the power. In fig. 3, the sampling rates of the real-time sampling signal 1 and the real-time sampling signal 2 are determined by the ATE radio frequency receiver, the sampling rate of the ATE radio frequency receiver can be set by the digital processor, and the time interval between sampling points can be calculated according to the sampling rate, for example, when the sampling rate is 1GHz, the time interval between two adjacent sampling points is 1 ns.

acquiring a rising start time point T3;

the on time tON of the radio frequency switch is: tON = (T1-T0) -T2;

the power rise time, tRISE, is: tRISE = (T1-T0) - (T3-T0) = T1-T3;

the ping-pong FIFO can send the sampling signals of all rates to the digital multiplier at the same high rate, the ping-pong FIFO has a fixed time delay, and in addition, the digital multiplier and the digital low-pass filter also have a fixed time delay, wherein t0 is the total time delay of the signals sequentially passing through the ping-pong FIFO, the digital multiplier and the digital low-pass filter, the rising start time point can be the start time of the rising, or the time point corresponding to the stable amplitude value multiplied by a first preset percentage, and the first preset percentage can be set according to actual needs, for example, the time point corresponding to the stable amplitude value multiplied by 10%.

the off time tOFF of the radio frequency switch is: tOFF = (T4-T0) -T5;

the power fall time tFALL is: tFALL = (T4-T0) - (T6-T0) = T4-T6;

t0 is the total time delay of the signal passing through the ping-pong FIFO, the digital multiplier, and the digital low-pass filter in sequence, the time point of the beginning of the descent may be the starting time of the beginning of the descent, or may be the time point corresponding to the stable amplitude value multiplied by the second preset percentage, and the second preset percentage may be set according to the actual requirement, for example, the time point corresponding to the stable amplitude value multiplied by 90%.

Further, step S201 is preceded by:

the digital signal processor outputs a TX control signal to control the working state of an ATE radio frequency signal source;

the digital signal processor outputs an RX control signal to control the operating state of the ATE radio frequency receiver.

And the automatic test is realized by controlling the ATE radio frequency signal source and the ATE radio frequency receiver through the digital signal processor.

Fig. 4 is a flowchart of a method for testing response time of a radio frequency switch chip according to another embodiment of the present invention, where the method includes the following steps:

s401, the digital signal processor sends a control signal to start an ATE radio frequency signal source and an ATE radio frequency receiver;

s402, setting working parameters of an ATE radio frequency signal source and an ATE radio frequency receiver through a digital signal processor;

s403, outputting a transmitting signal to the radio frequency switch to be tested by the ATE radio frequency signal source at the set frequency and power;

s404, the digital signal processor outputs a DUT control signal to the radio frequency switch to be tested to control the radio frequency switch to be tested to be in a conducting state, and the signal detection and calculation module records a first time point when the DUT control signal acts on the radio frequency switch to be tested to enable the radio frequency switch to be conducted;

s405, the ATE radio frequency receiver receives a transmitting signal output by the radio frequency switch to be tested, sends a processed receiving signal to the ping-pong FIFO, and processes the processed receiving signal through the ping-pong FIFIFI, the digital multiplier, the digital low-pass filter and the signal synthesis module in sequence to obtain a synthesized signal;

s406, when the amplitude of the synthesized signal is detected to be increased to be unchanged, the signal detection and calculation module calculates the starting time and the power rising time of the radio frequency switch to be controlled according to the first time point;

s407, the digital signal processor outputs a DUT control signal to the radio frequency switch to be detected so as to control the radio frequency switch to be detected to be in a closed state, and the signal detection and calculation module records a second time point when the DUT control signal acts on the radio frequency switch to be detected to close the radio frequency switch;

s408, the ATE radio frequency receiver receives a transmitting signal output by the radio frequency switch to be detected, and sends a processed receiving signal to the ping-pong FIFO, and the processed receiving signal is processed by the ping-pong FIFIFIFI, the digital multiplier, the digital low-pass filter and the signal synthesis module in sequence to obtain a synthesized signal;

s409, when the amplitude of the synthesized signal is detected to be reduced to be unchanged, according to a second time point, the signal detection and calculation module calculates the closing time and the power reduction time of the radio frequency switch to be switched;

and S410, the digital signal processor sends a control signal to turn off the ATE radio frequency signal source and the ATE radio frequency receiver.

Fig. 5 is a schematic structural diagram of a system for testing response time of an rf switch chip according to another embodiment of the present invention. The test system comprises a digital signal processor, an ATE radio frequency signal source, an ATE radio frequency receiver and a radio frequency switch to be tested; the ATE radio frequency signal source is connected with the digital signal processor, the output end of the ATE radio frequency signal source is connected with the input end of the radio frequency switch to be tested, the multi-path output of the radio frequency switch to be tested is connected with the ATE receiver, the control end of the radio frequency switch to be tested is connected with the digital signal processor, and the output end of the ATE receiver is connected with the digital signal processor;

a ping-pong FIFO for writing the processed received signal and outputting the data to the digital multiplier as two paths of same data at a predetermined rate;

the digital multiplier is used for multiplying two same signals to obtain a squaring signal and sending the squaring signal to the digital low-pass filter;

The invention discloses a method and a system for testing response time of a radio frequency switch chip, which can sample any frequency, is not influenced by time response of a detector and analysis bandwidth of an oscilloscope, and greatly improves time response resolution and time response error compared with the mode of the detector.

One of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the foregoing and various other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention.

Claims

1. A method for testing the response time of a radio frequency switch chip is characterized by comprising the following steps:

2. The method of claim 1, wherein the step of writing the processed received signal into a ping-pong FIFO, the ping-pong FIFO outputting the written signal as two identical signals to a digital multiplier at a predetermined rate comprises:

3. The method for testing the response time of the radio frequency switch chip according to claim 1, wherein the digital multiplier multiplies two paths of identical signals to obtain a self-multiplied signal, specifically:

the input signal of the digital multiplier is

；

The squaring signal is:

；

namely:

；

wherein the content of the first and second substances,

which is the amplitude of the signal, t represents time,

the angular frequency is represented by the angular frequency,

representing the phase angle.

4. The method for testing the response time of the radio frequency switch chip according to claim 3, wherein the digital low pass filter filters the squaring signal, the direct current signal of the squaring signal is retained, and the filtering signal obtained by filtering the high frequency signal is specifically:

digital low-pass filter pair squaring signal

Filtering is carried out;

。

5. The method for testing the response time of the radio frequency switch chip according to claim 1, wherein when it is detected that the amplitude of the synthesized signal is increased to be unchanged, determining the on-time and the power-up time of the radio frequency switch to be tested according to the recorded time point of the DUT control signal acting on the radio frequency switch to be tested to turn on the radio frequency switch to be tested specifically comprises:

acquiring a rising start time point T3;

the on time tON of the radio frequency switch is: tON = (T1-T0) -T2;

the power rise time, tRISE, is: tRISE = (T1-T0) - (T3-T0) = T1-T3;

6. The method for testing the response time of the radio frequency switch chip according to claim 1, wherein when it is detected that the amplitude of the synthesized signal is reduced to be unchanged, determining the turn-off time and the power down time of the radio frequency switch to be tested according to the recorded time point when the DUT control signal acts on the radio frequency switch to be tested to turn off the radio frequency switch specifically comprises:

the off time tOFF of the radio frequency switch is: tOFF = (T4-T0) -T5;

the power fall time tFALL is: tFALL = (T4-T0) - (T6-T0) = T4-T6;

7. The method for testing the response time of the radio frequency switch chip of claim 1, wherein the method further comprises: and the digital signal processor respectively controls the working states of the ATE radio frequency signal source and the ATE radio frequency receiver.

8. A test system for response time of a radio frequency switch chip is characterized by comprising a digital signal processor, an ATE radio frequency signal source, an ATE radio frequency receiver and a radio frequency switch to be tested; the ATE radio frequency signal source is connected with the digital signal processor, the output end of the ATE radio frequency signal source is connected with the input end of the radio frequency switch to be tested, the multi-path output of the radio frequency switch to be tested is connected with the ATE receiver, the control end of the radio frequency switch to be tested is connected with the digital signal processor, and the output end of the ATE receiver is connected with the digital signal processor;