CN110535551B - Method and system for synchronizing fault recording sampling data in power system - Google Patents

Method and system for synchronizing fault recording sampling data in power system Download PDF

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CN110535551B
CN110535551B CN201910917717.5A CN201910917717A CN110535551B CN 110535551 B CN110535551 B CN 110535551B CN 201910917717 A CN201910917717 A CN 201910917717A CN 110535551 B CN110535551 B CN 110535551B
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付国新
江晓亮
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Nanjing SAC Automation Co Ltd
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    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
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Abstract

The invention discloses a method and a system for synchronizing fault recording sampling data in a power system, which are characterized by comprising the following steps: analyzing and storing fault recording sampling SV message data of each merging unit of the transformer substation, wherein the hardware absolute time scale is marked on the data; selecting a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization moment; and finding out an interpolation position according to the absolute time scale of the synchronous time, calculating interpolation data of the synchronous time, and respectively finishing the synchronous interpolation of the recording sampling data. The method does not depend on the total station synchronous signal, solves the problem that the computation resource of the FPGA synchronous data is limited when a plurality of SVs are accessed, realizes the synchronization of the power system fault recording sampling data under a non-real-time system, improves the accuracy of the sampling data and the consistency of the amplitude, and has good application prospect.

Description

Method and system for synchronizing fault recording sampling data in power system
Technical Field
The invention relates to the technical field of power automation, in particular to a method and a system for synchronizing fault recording sampling data in a power system.
Background
In an intelligent substation of a power system, two fault recording sampling modes are provided, one mode is synchronous sampling based on a source end of external source (GPS synchronizer), and in the mode, all sampling is carried out under the pulse per second of a GPS; and the other method is that the tail ends of the two methods do not need external source synchronization to be directly sampled and sampled respectively under the beat of the crystal oscillators of the two methods. The recorder, which is a "black box" of the power system, needs to have access to both of these collected data. When the oscillograph is accessed to a great number of asynchronous sampling external source data in a point-to-point mode, the oscillograph needs to synchronize the sampling data from different devices, and the recording function of primary system voltage, electric power and the output quantity of the electric power when the system is greatly disturbed, such as short circuit fault, system oscillation, voltage breakdown and the like, is realized. Because of a lot of external sources, and in order to record the waveform can analyze that the amplitude attenuation of the harmonic wave of not less than 25 is not more than 5%, Largange second-order interpolation is adopted for interpolation synchronization, in order to satisfy the precision of the record data, the calculated amount is large, if adopt FPGA to carry out data processing, the capacity requirement to FPGA is very high, can increase the cost of the electric power system trouble record ripples device. Therefore, a method for solving the synchronization of fault recording data is needed.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides a method and a system for synchronizing fault recording sampling data in a power system, and solves the problems of overhigh hardware cost and insufficient synchronization precision caused by the fact that a fault recorder of the existing power system is synchronized by adopting an FPGA (field programmable gate array) when a large amount of asynchronously sampled external source data is accessed.
In order to achieve the above purpose, the invention adopts the following technical scheme: a method for synchronizing fault recording sampling data in a power system comprises the following steps:
analyzing and storing fault recording sampling SV message data of each merging unit of the transformer substation, wherein the hardware absolute time scale is marked on the data;
selecting a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization moment;
and finding out an interpolation position according to the absolute time scale of the synchronous time, calculating interpolation data of the synchronous time, and respectively finishing the synchronous interpolation of the recording sampling data.
Further, analyzing and storing the fault recording sampling SV message data of each merging unit of the transformer substation, which is marked with the hardware absolute time scale, specifically comprises the following steps:
and analyzing each frame of SV message, extracting sampling information, wherein the sampling information comprises an absolute time scale and a sampling value, distributing an SV double-ended queue for each substation merging unit, and storing the sampling information into the tail of the corresponding SV double-ended queue.
Further, selecting a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization time, specifically:
and scanning head nodes of all SV double-ended queues, selecting a merging unit with the absolute time scale dispersion smaller than 1 microsecond as a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization moment.
Further, finding out an interpolation position according to the absolute time scale of the synchronization time specifically comprises:
finding out the synchronous interpolation position according to the formula (1),
(tsyn-t'k)×(tsyn-t'k-1)≤0 (1)
obtaining absolute time scales and sampling values of three sampling points to be interpolated: (t'k,x'k)、(t'k-1,x'k-1)、(t'k-2,x'k-2) Wherein: t'kIs a k-th sampling time scale, x 'of a certain merging unit'kThe sampling value of the kth sampling moment of a certain merging unit; t'k-1Is a sampling time scale of k-1 th sampling time of a certain merging unit x'k-1Sampling values of k-1 sampling time of a certain merging unit; t'k-2Is a k-2 sampling time scale, x 'of a certain merging unit'k-2The sampling value of the k-2 sampling time of a certain merging unit.
Further, calculating interpolation data of the synchronization time specifically includes:
calculating the synchronization time t according to a second-order interpolation formula (2)synOf the sampled data xsyn
xsyn=x'k×Lk+x'k-1×Lk-1+x'k-2×Lk-2 (2)
Wherein:
Figure BDA0002216595280000021
a synchronization system for fault recording sampling data in a power system is characterized by comprising one or more message acquisition units and a recording data processing unit connected with the message acquisition units.
Further, the message acquisition unit is an FPGA message acquisition card and is used for acquiring SV messages of the merging unit of the transformer substation, marking hardware time marks on the SV messages and transmitting the SV messages to the wave recording data processing unit.
Furthermore, the wave recording data processing unit is a CPU, and the CPU is loaded with a non-real-time operating system.
Further, the CPU carries a Linux non-real-time operating system.
Further, 8 ethernet controllers and 1 PCIE controller are embedded in the message acquisition card.
The invention achieves the following beneficial effects: the non-real-time system sampling synchronization method based on the high-precision hardware time scale reduces the hardware cost of fault recording of the power system and improves the data synchronization precision.
The method does not depend on the total station synchronous signal, solves the problem that the computation resource of the FPGA synchronous data is limited when a plurality of SVs are accessed, realizes the synchronization of the power system fault recording sampling data under a non-real-time system, improves the accuracy of the sampling data and the consistency of the amplitude, and has good application prospect.
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FIG. 1 is a schematic diagram of an SV message collection system of the present invention;
FIG. 2 is a work flow diagram of the data synchronization of the present invention;
FIG. 3 is a diagram illustrating the data structure defined by the data synchronization of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
Example 1:
as shown in fig. 1, a synchronization system for sampling data of fault recording in an electrical power system includes one or more message acquisition units and a recording data processing unit connected to the message acquisition units.
The message acquisition unit is an FPGA message acquisition card used for acquiring SV messages of the merging unit of the transformer substation, the FPGA message acquisition card is built by adopting an EP3C55 FPGA with high cost performance, and 8 Ethernet controllers and 1 PCIE (high-speed serial computer extended bus) controller are embedded in each message acquisition card. The message acquisition card is responsible for acquiring SV messages of the merging unit of the transformer substation, marking hardware time marks on the SV messages and transmitting the SV messages to the wave recording data processing unit through the PCIE bus.
Each FPGA message acquisition card receives and records a clock synchronization signal of a high-precision clock generator of a wave data processing unit CPU, maintains an absolute time scale with the resolution ratio not lower than 10 nanoseconds, and the FPGA stamps the absolute time scale when receiving the first bit of the message and then transmits the absolute time scale to the CPU in a DMA mode through a PCIE controller.
The recording data processing unit is a CPU, an Intel Celeron Process N2806 dual-core low-power consumption embedded CPU processor is adopted, and the CPU carries a Linux non-real-time operating system. Receiving data (SV messages acquired by a message acquisition card and high-precision time marks marked on each SV message) and operating in a Linux kernel state;
example 2:
a synchronization method of fault recording sampling data in a power system comprises the following steps:
step 1: and (3) message data acquisition, namely acquiring SV messages of a plurality of merging units of the transformer substation by using an FPGA message acquisition card and respectively marking high-precision hardware absolute time scales. When the FPGA message acquisition card receives the first bit of the SV message, a hardware absolute time scale t with high precision (the time scale resolution is better than 10 nanoseconds) is markedkTransmitting SV messages to a CPU in an end-to-end mode through a PCIE bus;
step 2: a dual-core low-power-consumption embedded processor is adopted to form a data processing CPU of the wave recorder, a Linux non-real-time operating system is carried, and fault wave recording data SV messages of all merging units are analyzed and stored;
the SV messages of each merging unit are analyzed and stored, specifically:
CPU analyzes each frame SV message, extracts sampling information, the sampling information includes absolute time scale tkAnd a sampling value xkAnd distributing an SV double-ended queue for each substation merging unit, wherein each node of the queue corresponds to sampling information at a certain sampling moment, and storing the sampling information into the tail of the corresponding SV double-ended queue.
As shown in FIG. 3, the double-ended FIFO queue is adopted, the acquired data enters from the tail of the queue, the data is synchronously acquired from the head of the queue, and each node contains an absolute time scale tkSV rated delay TdAnd a sampling value xk
And step 3: selecting a reference merging unit, scanning head nodes of all SV double-ended queues at regular time by a CPU (Central processing Unit), scanning depth 1000 points, and selecting an absolute time scale dispersion smaller than 1 microsecond (namely the absolute value of subtraction of time difference between two adjacent points and standard time difference is smaller than 1 microsecond, for example, the standard time difference between the two points is 250 microseconds, if the time difference between the two points is 251 microseconds or 249 microseconds, the standard time scale dispersion is not satisfactory, and if the time difference between the two points is 251 microseconds or 249 microseconds, the standard time scale dispersion is not larger than 1 microsecond250.5 microseconds, the requirement that the absolute time scale dispersion is less than 1 microsecond) is met, and the absolute time scale of the reference merging unit is taken as the absolute time scale t of the synchronization momentsyn
And 4, step 4: respectively scanning other SV double-end queue nodes according to the absolute time scale t of the synchronization momentsynFinding out the interpolation position and calculating the synchronization time tsynInterpolated data x ofsynAnd respectively completing the synchronous interpolation of the recording sampling data.
Finding out the synchronous interpolation position according to the formula (1) to obtain the absolute time scales and sampling values of three sampling points to be interpolated: (t'k,x'k)、(t'k-1,x'k-1)、(t'k-2,x'k-2) Wherein: t'kIs the kth sampling time scale, x 'of other merging unit'kSampling values of k-th sampling time of other merging units; t'k-1Is the k-1 sampling time scale, x 'of other merging unit'k-1Sampling values of k-1 sampling moments of other merging units; t'k-2Is the k-2 sampling time scale, x 'of other merging unit'k-2The sampling value of the k-2 sampling moment of some other merging unit. In order to improve the scanning efficiency, the position of the interpolation point is memorized every time, and the position of the next interpolation point can be directly searched from the last memorized position.
(tsyn-t'k)×(tsyn-t'k-1)≤0 (1)
As can be seen from formula (1), the synchronous interpolation position is located at t'k、t'k-1At time or between two times;
calculating the synchronization time t according to a second-order interpolation formula (2)synOf the sampled data xsyn
xsyn=x'k×Lk+x'k-1×Lk-1+x'k-2×Lk-2 (2)
Wherein:
Figure BDA0002216595280000041
the non-real-time system sampling synchronization method based on the high-precision hardware time scale reduces the hardware cost of fault recording of the power system and improves the data synchronization precision.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims (7)

1. A method for synchronizing fault recording sampling data in a power system is characterized by comprising the following steps:
analyzing and storing fault recording sampling SV message data of each merging unit of the transformer substation, wherein the hardware absolute time scale is marked on the data;
selecting a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization moment;
finding out an interpolation position according to the absolute time scale of the synchronous moment, calculating interpolation data of the synchronous moment, and respectively finishing synchronous interpolation of the wave recording sampling data;
analyzing and storing fault recording sampling SV message data of each merging unit of the transformer substation, which is marked with a hardware absolute time scale, specifically comprising the following steps:
analyzing each frame of SV message, extracting sampling information, wherein the sampling information comprises absolute time scales and sampling values, distributing an SV double-ended queue for each substation merging unit, and storing the sampling information into the tail of the corresponding SV double-ended queue;
selecting a reference merging unit, taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization time, and specifically:
scanning head nodes of all SV double-ended queues, selecting a merging unit with the absolute time scale dispersion smaller than 1 microsecond as a reference merging unit, and taking the absolute time scale of the reference merging unit as the absolute time scale of the synchronization moment;
finding out an interpolation position according to the absolute time scale of the synchronous moment, which specifically comprises the following steps:
finding out the synchronous interpolation position according to the formula (1),
(tsyn-t′k)×(tsyn-t′k-1)≤0 (1)
obtaining absolute time scales and sampling values of three sampling points to be interpolated: (t'k,x′k)、(t′k-1,x′k-1)、(t′k-2,x′k-2) Wherein: t'kIs a k-th sampling time scale, x 'of a certain merging unit'kThe sampling value of the kth sampling moment of a certain merging unit; t'k-1Is a sampling time scale of k-1 th sampling time of a certain merging unit x'k-1Sampling values of k-1 sampling time of a certain merging unit; t'k-2Is a k-2 sampling time scale, x 'of a certain merging unit'k-2Sampling values of k-2 sampling moments of a certain merging unit;
tsynthe absolute time scale of the reference merging unit is used as the absolute time scale of the synchronization moment.
2. The method for synchronizing the fault recording sampling data in the power system according to claim 1, wherein the interpolation data at the synchronization time is calculated, specifically:
calculating the synchronization time t according to a second-order interpolation formula (2)synOf the sampled data xsyn
xsyn=x′k×Lk+x′k-1×Lk-1+x′k-2×Lk-2 (2)
Wherein:
Figure FDA0002752608420000021
3. a synchronization system for fault recording sampling data in an electric power system is characterized by comprising one or more message acquisition units and a recording data processing unit connected with the message acquisition units;
the recorded wave data processing unit executes the method for synchronizing fault recorded wave sampling data in the power system according to any one of claims 1-2.
4. The system for synchronizing fault recording sampling data in an electric power system according to claim 3, wherein the message collection unit is an FPGA message collection card and is configured to collect SV messages of the merging unit of the substation, mark hardware time marks on the SV messages, and transmit the SV messages to the recording data processing unit.
5. The system for synchronizing fault recording sampling data in an electric power system according to claim 3, wherein the recording data processing unit is a CPU carrying a non-real-time operating system.
6. The system for synchronizing fault recording sampling data in an electric power system according to claim 5, wherein the CPU is loaded with a Linux non-real-time operating system.
7. The system according to claim 4, wherein the message collection card has 8 Ethernet controllers and 1 PCIE controller embedded therein.
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