CN202049485U - High-speed data acquiring and digital signal processing board based on FPGA - Google Patents

Abstract

The utility model discloses a high-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array), characterized in that: an analog signal input and A/D conversion module, a digital signal processing module and a communication module are arranged in an integrated way, wherein the analog signal input and A/D conversion module comprises a signal conditioning circuit and an A/D conversion module; the digital signal processing module comprises an FPGA module, a memory DDR2 (Double Data Rate 2) and a data memory FLASH, original sampling data is processed by the digital signal processing module, wherein the processing steps comprise discrimination for fault starting, shifting out for fault data and processing for wavelet transformation, and an embedded network is realized by using the FPGA module; and the communication module is connected with the FPGA module, network physics layer chips are employed to match with the embedded network of the FPGA, so as to realize exchange of acquiring and calculating results with other boards or background computers. The high-speed data acquiring and digital signal processing board based on the FPGA of the utility model can realize high-speed synchronous acquiring and quick processing of high frequency transient traveling waves.

Description

High-speed data acquisition and digital signal panel based on FPGA

Technical field

The utility model relates to a kind of high-speed data acquisition and digital signal processing device based on FPGA, and especially a kind of being used in electric system carried out high speed, data in synchronization collection and the real-time fast device of handling to the high frequency transient signal.

Background technology

Transmission line travelling wave protection with hypervelocity performance is an important topic of relay protection of power system research.But, still do not have perfect traveling-wave protection device in the world at present and emerge.Main cause has 2 points, and the one, lack suitable mathematical measure analysis of high frequency transient state travelling wave signal; The 2nd, technical requirement is too high, such as, require sample frequency to reach more than the 500kHz, and to finish in the processing time 1-2 millisecond time, the problems referred to above are insurmountable with traditional technological means.

The utility model content

The purpose of this utility model is for overcoming the weak point of prior art; a kind of high-speed data acquisition and digital signal panel based on FPGA proposed; by the signal of being gathered is carried out wavelet transformation; thereby realize the high-speed synchronous collection and the fast processing of the capable ripple of high frequency transient, for the transmission line travelling wave protective device of realizing perfect performance provides safeguard.

The utility model technical solution problem adopts following technical scheme:

The utility model is integrated simulating signal input and A/D modular converter, digital signal processing module and the communication module of being provided with based on the high-speed data acquisition of FPGA and the characteristics of digital signal panel;

Described simulating signal input and A/D modular converter comprise: be used for receiving 12 channel signal modulate circuits of four circuit voltages or current analog signal, the A/D modular converter that links to each other with described signal conditioning circuit; Described A/D modular converter carries sampling hold circuit, uses external reference voltage and external clock, ternary output;

Described digital signal processing module comprises: the FPGA module that links to each other with described A/D modular converter, the storer DDR2 and the data-carrier store FLASH that link to each other with described FPGA module, the DSP program that provides for described FPGA module is stored among described DDR2 or the FLASH; Described digital signal processing module is finished following digital signal processing:

A, handle original sampling data, comprising: the shifting out and the processing of wavelet transformation of the differentiation of fault initiating, fault data;

B, utilizing the FPGA module to realize built-in network, is that carrier is realized information interaction with the built-in network; Described FPGA is inner to start the pattern that module adopts soft start, after the voltage that collects or current data are carried out the criterion of part starting algorithm, starts with the form guiding of interrupting, and record starts address constantly simultaneously; Behind the fault initiating through the time-delay, fault data shifts out module DMA and starts working, upwards seek the fault data of self-defined length from interrupting address constantly, fault data length is set is not more than 1s, comprise before the fault and fault after total data, and be moved out to fault data storage space among the storer DDR2 of system assignment.

C, with described storer DDR2 storage failure data, and store among the FLASH described fault data into effective backup as data;

Described communication module links to each other with described FPGA module, adopts the networked physics layer chip to match with the built-in network of FPGA, realizes and other plate or background computer exchange collection and result of calculation.

The utility model can at a high speed, synchronously be gathered various voltage and current signals, and these signals are carried out handling in real time fast.Particularly can carry out high speed, data in synchronization collection and processing in real time fast to the high frequency transient signal, compared with the prior art, the utility model beneficial effect is embodied in:

1, in the utility model based on the configuration of FPGA, DDR2 and FLASH, made full use of the ability of the parallel computation of FPGA, can realize express-analysis, calculating and the jumbo storage of fault data, the data security height;

2, the utility model adopts the built-in network design based on FPGA, has superpower network communications capability, fault data of transmission outward and result of calculation that can be real-time;

3, the utility model utilizes wavelet transformation technique, and real-time analysis handling failure data accurately analyze position of failure point, and computing velocity is fast, the precision height;

4, apparent size of the present utility model is little, is easy to cascade and expansion, can gather the nearly electric parameters of 24 circuits simultaneously;

5, the utility model adopts the pattern of soft start, can dispose multiple startup method simultaneously, all can start for the various faults type, uses flexible, convenient;

6, the utility model can be used for a plurality of fields in the electric system, protective relaying device for example, electric power system fault oscillograph, electric power system fault logout instrument etc., the occasion that needs the synchronous high-speed data acquisition and handle in real time fast.

Description of drawings

Fig. 1 gathers and the digital signal panel hardware structure diagram for the utility model high speed;

Fig. 2 is a communication mode synoptic diagram in the utility model;

Fig. 3 is a three-phase fault current waveform figure in the present embodiment;

Fig. 4 is the synoptic diagram of A phase fault electric current behind the wavelet transformation in the present embodiment;

Fig. 5 is the utility model deposit data form synoptic diagram;

Fig. 6 is the utility model fault handling and network service control flow chart.。

Embodiment

Referring to Fig. 1, this example is by simulating signal input and A/D modular converter I, based on the digital signal processing module II of FPGA, and three part compositions of communication module III.

Simulating signal input and A/D modular converter I: comprise signal conditioning circuit, A/D modular converter and A/D control loop, wherein: the A/D in the signal conditioning circuit partly sample three road voltages, three road electric currents, sampling rate is 800K, also can be made as 1.6 megahertzes, in order to be complementary with preposition amplifier, PT, CT secondary side require maximum to be output as ± 10V; A/D conversion chip among the digital to analog converter chip A/D is selected AD8553: sampling rate 800K, carries sampling hold circuit, uses external reference voltage, external clock, low-power consumption, low noise, ternary output.

Digital signal processing module II based on FPGA: comprise correspondent peripheral circuit and A/D sampling module and the data processing module all realized in FPGA inside; Wherein: the A/D sampling module is used to control the A/D conversion, and transformation result is sent into storer DDR2 and FLASH, forms the pairing fault data first address of fault initiating; FPGA is driven by the crystal oscillator of the high stability of external 80 megahertzes, and the AD that produces 800 KHz at the inner frequency division of FPGA triggers signal constantly, and this trigger pip is undertaken by the pps pulse per second signal of GPS synchronously.The data that collect are by impact damper, and directly circulation is stored among the storer DDR2; Data processing module is used to handle original sampling data, comprising: the shifting out of the differentiation of fault initiating, fault data, and the processing of wavelet transformation program;

The inner pattern that starts module employing soft start of FPGA after the electric current and voltage data that collect are carried out the criterion of part starting algorithm, starts the address constantly of record startup simultaneously with the form guiding of interrupting.Behind the fault initiating, time-delay through certain hour, fault data shifts out the module dma module and starts working, upwards seek the fault data of self-defined length from interrupting address constantly, comprise before the fault and the data after the fault, fault data length generally is set at and is not more than 1 second, fault data is moved out to fault data storage space among the storer DDR2 of system assignment, this space size is 64M, can hold fault data simultaneously more than 1000, simultaneously, this fault data also will store among the FLASH, as effective backup of data.

Digital signal processor module FPGA is chosen as the CycloneIV chip, is mainly used in data processing and analysis, has powerful parallel processing capability, has speed fast, the characteristics that precision is high.

Communication module III: adopt the IP101PHY chip, be used for gathering and result of calculation with other plate or background computer exchange.

Because the MAC function is contained in FPGA inside, the IP101PHY chip that has then added Taiwan nine positive companies in peripheral circuit is to realize network communicating function.The IP101PHY chip is supported the 10-100M adaptive network transmission of IEEE802.3/802.3u, support identification MDI/MDIX function automatically, adopt the 48-pinLQFP packaged type, chip only has the low power dissipation design energy savings very of 3.3v voltage, and supports to enter automatically the energy-saving standby state.With the connected mode of central processing unit or background computer as shown in Figure 2, be initiatively to send out data by FPGA to give background processor, adopt the mode of network service, can make full use of the reliable and stable advantage of Network Transmission, and support the function of breakpoint transmission and re-transmission etc.

If three-phase current waveform to be sampled as shown in Figure 3, the curve 1 among Fig. 3, curve 2, curve 3 are represented A phase, B phase and C three-phase current mutually respectively; Be applied to travelling wave ranging with digital-to-analog conversion of present embodiment high speed and digital signal panel, carry out failure data acquisition and digital signal processing, its function, the course of work and principle are:

1, gathers and writes down the analog data of 24 passages simultaneously;

2, the voltage and current that comes from ultra-high-tension power transmission line is transformed into the electric current of 100 volts voltage and 5 amperes or 1 ampere respectively through the voltage and current mutual inductor;

3, the electric current of 100 volts voltage and 5 amperes or 1 ampere is transformed into simulating signal for the positive and negative 10V that gathers use through Hall element again;

4, the simulating signal of 20 four tunnel positive and negative 10V inserts the input end of high speed acquisition board;

5, under the control of FPGA, finish the synchronized sampling and the timesharing analog to digital conversion of one time 20 four tunnel simulating signal every 1 microsecond, conversion accuracy is 16;

6, in FPGA, the transformation result of step 3 is pushed into impact damper in order, enters the DDR2 data-carrier store again;

7, in DDR2, data are recycled to be deposited, promptly from certain unit, store data continuously, institute have living space deposit full after, new data will cover legacy data, deposit form as shown in Figure 5;

8, under the normal condition, data are stored continuously, but FPGA will not do any processing to it;

9, after fault takes place, the start-up circuit among the FPGA will work, and send look-at-me, FPGA will note this constantly with storage address correspondingly;

10, after fault took place, FPGA shifted out module DMA by fault data fault data is shifted out the circulation memory block, is carried in data space and the FLASH storer.

If at t fault has taken place constantly, T=10ms breaks down in Fig. 3, electric current will be undergone mutation:

Constantly through time-delay a period of time (for example 2ms), fault data shifts out module DMA will upwards seek the data of two cycles from the address of last record from this, and every road amounts to 32 K words (16) (having write down 40 milliseconds fault data window altogether);

11, carry out wavelet transformation or other digital signal processing for the voltage and current data after the above-mentioned fault, ask for the fault signature value behind the wavelet transformation, calculate fault distance.With the A in the three-phase fault electric current is example mutually, and the maximum of points among Fig. 4 is the fault signature value behind the A phase wavelet transformation.

12, fault data and result of calculation are delivered in central processing unit or the backstage through the network service mouth gone, thereby finish the task of whole data collection and calculation of fault.

Communication software part mainly by two independently thread form, fault handling thread and network service thread, its flow process as shown in Figure 6.The main task of fault handling thread is the register that config failure is handled, registration Interrupt Process function, responding DMA request and handling interrupt service routine, informing network communication thread transmission data.The network service thread is responsible for setting up network service and is connected, and sets up corresponding server end or client according to channel type, waits to send out the district by patrolling and examining data, and the stipulations that the traveling wave fault data are worked out according to inside are carried out framing, by network data is sent out.

Claims (1)

1. based on high-speed data acquisition and the digital signal panel of FPGA, it is characterized in that integrated simulating signal input and A/D modular converter, digital signal processing module and the communication module of being provided with;

Described simulating signal input and A/D modular converter comprise: be used for receiving 12 channel signal modulate circuits of four circuit voltages or current analog signal, the A/D modular converter that links to each other with described signal conditioning circuit; Described A/D modular converter carries sampling hold circuit, uses external reference voltage and external clock, ternary output;

Described digital signal processing module comprises: the FPGA module that links to each other with described A/D modular converter, the storer DDR2 and the data-carrier store FLASH that link to each other with described FPGA module, the DSP program that provides for described FPGA module is stored among described DDR2 or the FLASH; Described digital signal processing module is finished following digital signal processing:

A, handle original sampling data, comprising: the shifting out and the processing of wavelet transformation of the differentiation of fault initiating, fault data;

B, utilizing the FPGA module to realize built-in network, is that carrier is realized information interaction with the built-in network; Described FPGA is inner to start the pattern that module adopts soft start, after the voltage that collects or current data are carried out the criterion of part starting algorithm, starts with the form guiding of interrupting, and record starts address constantly simultaneously; Behind the fault initiating through the time-delay, fault data shifts out module DMA and starts working, upwards seek the fault data of self-defined length from interrupting address constantly, fault data length is set is not more than 1s, comprise before the fault and fault after total data, and be moved out to fault data storage space among the storer DDR2 of system assignment.

C, with described storer DDR2 storage failure data, and store among the FLASH described fault data into effective backup as data;

Described communication module links to each other with described FPGA module, adopts the networked physics layer chip to match with the built-in network of FPGA, realizes and other plate or background computer exchange collection and result of calculation.

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