CN101587499B - Multi-channel signal acquiring system based on NAND - Google Patents

Multi-channel signal acquiring system based on NAND Download PDF

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Publication number
CN101587499B
CN101587499B CN2009100878496A CN200910087849A CN101587499B CN 101587499 B CN101587499 B CN 101587499B CN 2009100878496 A CN2009100878496 A CN 2009100878496A CN 200910087849 A CN200910087849 A CN 200910087849A CN 101587499 B CN101587499 B CN 101587499B
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module
clock
data
unloading
signal
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CN101587499A (en
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谢民
高梅国
张雄奎
方秋均
李先楚
雷磊
刘国满
侯文才
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Beijing Institute of Technology BIT
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Beijing Institute of Technology BIT
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Abstract

The invention relates to a multi-channel signal acquiring system belonging to the technical filed of digital signal processing. The system comprises: one clock module, two double-channel high speed data acquisition module, eight NAND storage modules, one unloading module, one secondary baseboard module, one main control module and one client end module, the analog signals can be acquired and stored in real time by four-way 900 MHZ sampling rate, the system has 3 TB storage capacity. The invention adopts the NAND storage body as the storage medium, has advantages of small facility volume and low power consumption, the synchronization consistency of four-way acquisition channel can be implemented by the synchronization processing of a clock enable signal, a sampling trigger signal and a sampling clock and the accurate design of a signal delay.

Description

Multi-channel signal acquiring system based on NAND
Technical field
The present invention relates to a kind of multi-channel signal acquiring system, belong to digital signal processing technique field.
Background technology
Data storage device is widely used in every profession and trades such as radar, industrial automation, health care, communication, owing to relate to the employed environment difference of equipment, its implementation also is not quite similar.How satisfying under the prerequisite of performance requirement, accomplishing economically, convenient, practical as far as possible, still is the major reason that data storage research is constantly weeded out the old and bring forth the new.In the research of modern data storage system, particularly in the middle of the Embedded Application, how under the limited situation of volume power consumption, to realize the high speed acquisition and the mass memory of data, and realize the playback reproduction of data, become present research focus.For example in the radar receiving system, usually the high-speed real-time that collects to be saved in the storer in time so that do subsequent treatment.Modern radar receiving system, all at 12 or 14, sampling rate also may reach 100Msps or higher in the A/D conversion of its data acquisition, and therefore how need research badly stores these high speed and super precision degrees of data.A kind of feasible method is earlier high-speed data to be stored in the mass storage, reads in computing machine then at a slow speed and handles.In order to guarantee the high reliability of data, some special-purpose high-speed data acquistion systems have adopted disk array, are mainly used in mass data storage in the radar system as the LH-DACQ High-Speed RADAR digital data recording system of permanent Si Jie company development.This system adopts scsi disk as basic storage medium, and adopts the storage Control Engine of RAID0.Its lasting writing speed is 320MB/s, and the peak value storage speed surpasses 385MB/s.But this class is all very big by storage system volume and the power consumption that disk constitutes, and can't satisfy the demand of Embedded Application.
Summary of the invention
The storage system that the objective of the invention is to constitute at the disk in the middle of the existing Embedded Application exists deposits the shortcoming that volume is big, power consumption is big and memory bandwidth is little, design adopts high capacity storage chip NAND to make up the multi-channel high-speed signal acquiring system, and realizes multichannel synchronous acquisition.
The objective of the invention is to be achieved through the following technical solutions.
A kind of multi-channel signal acquiring system based on NAND of the present invention comprises: 1 clock module, 2 double-channel high speed data acquisition module, 8 NAND memory modules, 1 unloading module, 1 secondary floor module, 1 main control module and 1 client modules, each functional block diagram of system as shown in Figure 1, wherein:
Clock module receives outer input reference clock and produces the required sampling clock of double-channel high speed data acquisition module, and produces the required gate signal of double-channel high speed data acquisition module according to being provided with of main control module; In order to control the synchronism of multichannel collecting, clock module also provides synchronous reset signal for two double-channel high speed data acquisition module;
Double-channel high speed data acquisition module is provided by the sampling clock and the gate signal that provide according to clock module, the broadband analog signal that receives is gathered, and according to the parameter of main control module setting the data that sample are packed, then send to the NAND memory module;
The NAND memory module receives the data from double-channel high speed data acquisition module output, according to the parameter of main control module setting the data that receive is carried out real-time storage;
The unloading module is responsible for the data of a plurality of NAND memory modules are read, and finishes the splicing and the arrangement of data, and exports to client modules by gigabit ethernet interface;
The secondary floor module is responsible for providing the physical connection between double-channel high speed data acquisition module, NAND memory module, unloading module, the clock module;
Main control module is responsible for management and the control to all functions module, setting, the collection that comprises acquisition parameter starts and stops, observation, data erase and the data conversion storage etc. of image data, among Fig. 1, main control module is communicated by letter without the secondary floor module with clock module, double-channel high speed data acquisition module, high-speed high capacity memory module and unloading module, and is to use pci bus to communicate;
Client modules and main control module match, and are responsible for receiving the data that the unloading module is sent by gigabit Ethernet, carry out data storage by the file size of appointment, and preserve relevant Information Monitoring.
The course of work of a kind of multi-channel signal acquiring system based on NAND of the present invention is as follows:
As shown in Figure 2, carry out the multi-channel synchronous flow process after system powers at first automatically, enter waiting status then, the user can import correlation parameter at this moment and carry out orders such as gathering storage, data conversion storage; During fill order, the parameter generating command word that main control module at first can be imported according to the user automatically, and will reach each correlation module under the command word, system enters the corresponding command state; During EO, system can automatic rebound wait command state, thereby gets ready for next operation.
Gather storing process and comprise following job step:
Main control module will be gathered duration parameters and assign to clock board, and data bit width is assigned to double-channel high speed data acquisition module, and address parameter is assigned the memory module to NAND;
Main control module places acquisition state with the NAND memory module, and the control clock module enters gathers and produce the collection gate signal of specifying the collection duration;
Double-channel high speed data acquisition module is converted to digital signal according to the collection gate signal of clock module output with analog intermediate frequency signal, according to the data bit width parameter of main control module setting data is packed, and sends to the NAND memory module;
The NAND memory module receives the packet that double-channel high speed data acquisition module sends over, and the address parameter that is provided with according to main control module generates the order bag, sends to the NAND controller on the NAND memory module, and by it data is write the NAND memory bank;
Gather when finishing, main control module is preserved the coherent signal of this collection in the mode of data recording.
The data conversion storage process comprises following job step:
Client modules is set, makes it to be in the reception waiting status;
Main control module will specify the unloading of unloading record initial/position, end address information assigns the memory module to NAND, and data bit width information is assigned to the unloading module, and the NAND memory module is placed the data conversion storage state, then start the unloading module and begin unloading;
The unloading module is sent request data signal to the NAND memory module;
After the NAND memory module receives this signal, read the data of assigned address, packing sends to the unloading module;
The packet that the data bit width information butt joint that the unloading module provides according to motherboard is received splices and puts in order, then exports client modules to by gigabit Ethernet;
Client modules is preserved by passage the data that receive according to the file size that is provided with;
When the address of NAND memory module unloading reached the end address, the NAND memory module finished unloading automatically.
In order to realize multichannel synchronous acquisition, the present invention has adopted the synchronous reset technology, thereby guaranteed initial multi-channel A C chip output data first consistent behind demultplexer that power in system, then by the synchronization process of gate signal and sampling clock and walk the wire delay design accurately and realized in the plate/plate between the synchronous acquisition of multi-channel A C.
Beneficial effect:
Compare with existing acquisition system, it has following characteristics:
This equipment is 4 acquisition channels altogether, each passage 900MHz sampling rate, maximum storage bandwidth 4.5GB/s; Memory capacity is 3TB altogether; The 6U17 scouring machine case of standard, power consumption only are 350W; The synchronization accuracy of four passages is less than a sampled point.
Description of drawings
Fig. 1 is a functional module composition frame chart of the present invention;
Fig. 2 is a system works flow process of the present invention;
Fig. 3 is a secondary base plate connection layout of the present invention;
Fig. 4 is a multi-channel synchronous schematic flow sheet of the present invention;
Fig. 5 is that synchronizing signal of the present invention produces synoptic diagram, wherein:
A1: sampling gate signal, clock enable signal through 100MHz exports synchronously offer ADC plate 1; A2: sampling gate signal, clock enable signal through 100MHz exports synchronously offer ADC plate 2; B1: the sampling clock that offers ADC plate 1; B2: the sampling clock that offers ADC plate 2.
Embodiment
Below in conjunction with the drawings and the specific embodiments the present invention is done and to describe in further detail:
A kind of multi-channel signal acquiring system based on NAND comprises: 2 blocks of Dual-Channel High-Speed Data Acquisition plates, 8 NAND memory board, a clock board, a unloading plate, a secondary base plate, motherboard, standard 6U17 groove CPCI cabinet and client computers that capacity is 384GB.
The Dual-Channel High-Speed Data Acquisition plate is provided by the sampling clock and the gate signal that provide according to clock board, the broadband analog signal that receives is gathered, and according to the parameter of motherboard setting sampled data is packed, and then sends to the high-speed high capacity memory board; The integrated TS83102G0 of two Atmel companies on every block of Dual-Channel High-Speed Data Acquisition plate realizes analog to digital conversion speed 900MSPS; Every block of Dual-Channel High-Speed Data Acquisition plate and 4 NAND memory boards are by 4 source synchronization link interconnection (by the secondary base plate), the bandwidth 800MB/s of every link; For one road ADC, its acquisition bandwidth is 1125MB/s, and the data that ADC gathers among the present invention send to two memory boards by the mode of table tennis.
The NAND memory board receives the data from the output of Dual-Channel High-Speed Data Acquisition plate in gathering storing process, according to the parameter of motherboard setting the data that receive are carried out real-time storage; In the data conversion storage course of work, receive the request of unloading plate after, send the data to the unloading plate according to the parameter of motherboard setting.
Clock board produces the required sampling clock of Dual-Channel High-Speed Data Acquisition plate by outer input reference clock, and produces the required gate signal of Dual-Channel High-Speed Data Acquisition plate according to being provided with of motherboard; In order to control the synchronism of multichannel collecting, this integrated circuit board provides synchronous reset signal for two blocks of Dual-Channel High-Speed Data Acquisition plates.
The unloading plate is responsible for the data of polylith NAND memory board are read, and finishes the splicing and the arrangement of data, and exports to client computer by gigabit Ethernet.
The secondary base plate is responsible for providing the physical connection between Dual-Channel High-Speed Data Acquisition plate, NAND memory board, unloading plate, the clock board, and concrete data path as shown in Figure 3.In order to guarantee 4 road ADC output datas first consistent on two blocks of Dual-Channel High-Speed Data Acquisition plates, on the secondary base plate, designed two synchronous reset signals, by clock board to two block Dual-Channel High-Speed Data Acquisition plate, and strict control is isometric.
Motherboard is responsible for management and the control to every other integrated circuit board, finishes the process control to whole acquisition system, comprises that setting, the collection of acquisition parameter starts and stop, observation, data erase and the data conversion storage etc. of image data.
Client computer and motherboard match, and are responsible for receiving the data that the unloading plate sends by gigabit Ethernet, carry out data storage by the file size of appointment, and preserve relevant Information Monitoring.
Standard 6U17 groove CPCI cabinet provides hardware platform for whole signal acquiring system.
The present invention is multichannel synchronous in order to realize between plate, employed method is as shown in Figure 4: after powering on, two blocks of Dual-Channel High-Speed Data Acquisition plates are finished separately and are closed clock, the ADC chip that resets, the DEMUX that resets, counting wait for that some all after dates discharge the DEMUX reset signals, discharge these several steps operations of ADC chip reset, wait for that then clock enable signal that clock board provides opens the sampling clock of 4 paths simultaneously.Owing to guaranteed the consistance of walking wire delay of clock enable signal to two plates on hardware design, and device on two blocks of Dual-Channel High-Speed Data Acquisition plates, FPGA program are identical, thereby guarantee the sampled point phase place unanimity of passage between plate.
Fix for the phase relation of guarantee to sample gate signal, clock enable signal and sampling clock, adopted design as shown in Figure 5 among the present invention, the gate signal of promptly sampling, clock enable signal by with the low-frequency clock of sampling clock homology synchronously after output.

Claims (4)

1. multi-channel high-speed high capacity signal acquiring system based on NAND, it is characterized in that: comprise 1 clock module, 2 double-channel high speed data acquisition module, 8 NAND memory modules, 1 unloading module, 1 secondary floor module, 1 main control module and 1 client modules, wherein:
Clock module receives outer input reference clock and produces the required sampling clock of double-channel high speed data acquisition module, and produces the required gate signal of double-channel high speed data acquisition module according to being provided with of main control module; In order to control the synchronism of multichannel collecting, clock module also provides synchronous reset signal for two double-channel high speed data acquisition module;
Double-channel high speed data acquisition module is provided by the sampling clock and the gate signal that provide according to clock module, the broadband analog signal that receives is gathered, and according to the parameter of main control module setting the data that sample are packed, then send to the NAND memory module;
The NAND memory module receives the data from double-channel high speed data acquisition module output, according to the parameter of main control module setting the data that receive is carried out real-time storage;
The unloading module is responsible for the data of a plurality of NAND memory modules are read, and finishes the splicing and the arrangement of data, and exports to client modules by gigabit ethernet interface;
The secondary floor module is responsible for providing the physical connection between double-channel high speed data acquisition module, NAND memory module, unloading module, the clock module;
Main control module is responsible for management and the control to the above-mentioned functions module, comprises that setting, the collection of acquisition parameter starts and stop, observation, data erase and the data conversion storage of image data; Main control module is communicated by letter without the secondary floor module with clock module, double-channel high speed data acquisition module, high-speed high capacity memory module and unloading module, and is to use pci bus to communicate;
Client modules and main control module match, and are responsible for receiving the data that the unloading module is sent by gigabit Ethernet, carry out data storage by the file size of appointment, and preserve relevant Information Monitoring.
2. a kind of multi-channel high-speed high capacity signal acquiring system according to claim 1 based on NAND, it is characterized in that: carry out the multi-channel synchronous flow process after system powers at first automatically, enter waiting status then, the user can import correlation parameter at this moment and carry out and gather storage, data conversion storage order; During fill order, the parameter generating command word that main control module at first can be imported according to the user automatically, and will reach each correlation module under the command word, system enters the corresponding command state; During EO, system can automatic rebound wait command state, thereby gets ready for next operation;
When carrying out the data acquisition memory command:
Main control module will be gathered duration parameters and assign to clock module, and data bit width is assigned to double-channel high speed data acquisition module, and address parameter is assigned the memory module to NAND;
Main control module places acquisition state with the NAND memory module, and the control clock module enters gathers and produce the collection gate signal of specifying the collection duration;
Double-channel high speed data acquisition module is converted to digital signal according to the collection gate signal of clock module output with analog intermediate frequency signal, according to the data bit width parameter of main control module setting data is packed, and sends to the NAND memory module;
The NAND memory module receives the packet that double-channel high speed data acquisition module sends over, and the address parameter that is provided with according to main control module generates the order bag, sends to the NAND controller on the NAND memory module, and by it data is write the NAND memory bank;
Gather when finishing, main control module is preserved the coherent signal of this collection in the mode of data recording;
When carrying out the data conversion storage order:
Client modules is set, makes it to be in the reception waiting status;
Main control module will specify the unloading of unloading record initial/position, end address information assigns the memory module to NAND, and data bit width information is assigned to the unloading module, and the NAND memory module is placed the data conversion storage state, then start the unloading module and begin unloading;
The unloading module is sent request data signal to the NAND memory module;
After the NAND memory module receives this request data signal, read the data of assigned address, packing sends to the unloading module;
The packet that the data bit width information butt joint that the unloading module provides according to motherboard is received splices and puts in order, then exports client modules to by gigabit Ethernet;
Client modules is preserved by passage the data that receive according to the file size that is provided with;
When the address of NAND memory module unloading reached the end address, the NAND memory module finished unloading automatically.
3. a kind of multi-channel high-speed high capacity signal acquiring system according to claim 1 based on NAND, it is characterized in that: multichannel synchronous in order to realize between plate, after powering on, two blocks of Dual-Channel High-Speed Data Acquisition plates are finished separately and are closed clock, the ADC chip resets, DEMUX resets, counting waits for that some all after dates discharge the DEMUX reset signal, discharge the operation of ADC chip reset, wait for that then clock enable signal that clock module provides opens the sampling clock of 4 paths simultaneously, owing on hardware design, guaranteed the consistance of walking wire delay of clock enable signal to two plates, and device on two blocks of Dual-Channel High-Speed Data Acquisition plates, the FPGA program is identical, thereby guarantees the sampled point phase place unanimity of passage between plate.
4. a kind of multi-channel high-speed high capacity signal acquiring system according to claim 1 based on NAND, it is characterized in that: for the phase relation of guarantee to sample gate signal, clock enable signal and sampling clock is fixed, sampling gate signal, clock enable signal provide by clock module, by exporting synchronously with the low-frequency clock of sampling clock homology.
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