CN102253295B - High-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array) - Google Patents
High-speed data acquiring and digital signal processing board based on FPGA (Field Programmable Gate Array) Download PDFInfo
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Abstract
The invention discloses a high-speed data acquiring and digital signal processing board based on an FPGA (Field Programmable Gate Array), which is characterized by being integrally provided with an analog signal input and A/D (Analog-to-Digital) conversion module, a digital signal processing module and a communication module, wherein the analog signal input and A/D conversion module comprises a signal conditioning circuit and an A/D conversion module; the digital signal processing module comprises an FPGA module, a storage DDR2 and a data storage FLASH; the digital signal processing module is used for processing original sampling data through the steps of fault starting judgment, fault data shift out and wavelet transform processing; an embedded network is realized by the FPGA module; the communication module is connected with the FPGA module; and a networked physics layer chip is cooperated with an FPGA embedded network to realize the purposes of exchanging, collecting and calculating results with other plates or a background computer. According to the high-speed data acquiring and digital signal processing board, high-frequency transient state traveling wave can be synchronously collected and quickly processed.
Description
Technical field
The present invention relates to a kind of high-speed data acquisition and digital signal processing device based on FPGA, especially a kind of in electric system for the high frequency transient signal being carried out at a high speed, synchronous data acquisition and the device of processing in real time fast.
Background technology
Transmission line travelling wave protection with hypervelocity performance is an important topic of relay protection of power system research.But, there is no in the world perfect traveling-wave protection device at present and emerge.Main cause has 2 points, and the one, lack suitable mathematical measure analysis of high frequency transient state travelling wave signal; The 2nd, technical requirement is too high, such as, require more than sample frequency reaches 500kHz, and the processing time to complete 1-2 millisecond time, the problems referred to above are insurmountable by traditional technological means.
Summary of the invention
The objective of the invention is for overcoming the weak point of prior art; a kind of high-speed data acquisition and digital signal panel based on FPGA proposed; carry out wavelet transformation by the signal to gathered; thereby realize high-speed synchronous collection and the fast processing of the capable ripple of high frequency transient, for the transmission line travelling wave protective device of realizing perfect performance provides safeguard.
Technical solution problem of the present invention adopts following technical scheme:
The present invention is based on the high-speed data acquisition of FPGA and the characteristics of digital signal panel is integrated simulating signal input and A/D modular converter, digital signal processing module and the communication module of arranging;
Described simulating signal input and A/D modular converter comprise: for receiving 12 passage signal conditioning circuits of four circuit voltages or current analog signal, the A/D modular converter be connected with described signal conditioning circuit; Described A/D modular converter carries sampling hold circuit, uses external reference voltage and external clock, ternary output;
Described digital signal processing module comprises: the FPGA module be connected with described A/D modular converter, the storer DDR2 and the data-carrier store FLASH that with described FPGA module, are connected, the DSP program provided for described FPGA module is stored in described DDR2 or FLASH; Described digital signal processing module completes following digital signal processing:
A, process original sampling data, comprising: the shifting out and the processing of wavelet transformation of the differentiation of fault initiating, fault data;
B, utilize the FPGA module to realize built-in network, the built-in network of take is realized information interaction as carrier; The inner pattern that starts module employing soft start of described FPGA, after carrying out the criterion of part starting algorithm by the voltage to collecting or current data, start the address of simultaneously recording Startup time with the form guiding of interrupting; After fault initiating through time delay, fault data shifts out module DMA and starts working, upwards find the fault data of self-defined length constantly from interrupting address, fault data length is set and is not more than 1s, comprise before fault and fault after total data, and be moved out to the fault data storage space in the storer DDR2 of system assignment.
C, with described storer DDR2 storage failure data, and store in FLASH described fault data into effective backup as data;
Described communication module is connected with described FPGA module, and the Adoption Network physical chip matches with the built-in network of FPGA, realizes and other plate or background computer exchange collection and result of calculation.
The present invention can at a high speed, synchronously gather various voltage and current signals, and these signals are carried out processing in real time fast.Particularly can carry out at a high speed the high frequency transient signal, synchronous data acquisition and processing in real time fast, compared with the prior art, beneficial effect of the present invention is embodied in:
1, the configuration based on FPGA, DDR2 and FLASH in the present invention, take full advantage of the ability of the parallel computation of FPGA, can realize express-analysis, calculating and the jumbo storage of fault data, and data security is high;
2, the present invention adopts the built-in network design based on FPGA, has superpower network communications capability, the fault data of transmission outward and result of calculation that can be real-time;
3, the present invention utilizes wavelet transformation technique, real-time analysis handling failure data, and an accurate analysis position of being out of order, computing velocity is fast, and precision is high;
4, apparent size of the present invention is little, is easy to cascade and expansion, can gather the nearly electric parameters of 24 circuits simultaneously;
5, the present invention adopts the pattern of soft start, can configure multiple starting method simultaneously, for the various faults type, all can start, and uses flexible, convenient;
6, the present invention can be used for a plurality of fields in electric system, protective relaying device for example, Power System Fault Record device, electric power system fault logout instrument etc., the occasion that needs the synchronous high-speed data acquisition and process in real time fast.
The accompanying drawing explanation
Fig. 1 is that high speed of the present invention gathers and the digital signal panel hardware structure diagram;
Fig. 2 is communication mode schematic diagram in the present invention;
Fig. 3 is three-phase fault current waveform figure in the present embodiment;
Fig. 4 is the schematic diagram of A phase fault electric current after wavelet transformation in the present embodiment;
Fig. 5 is deposit data form schematic diagram of the present invention;
Fig. 6 is fault handling of the present invention and network service control flow chart.。
Embodiment
Referring to Fig. 1, this example is inputted by simulating signal and A/D modular converter I, the digital signal processing module II based on FPGA, and tri-parts of communication module III form.
Simulating signal input and A/D modular converter I: comprise signal conditioning circuit, A/D modular converter and A/D control loop, wherein: the A/D in signal conditioning circuit partly sample three road voltages, three road electric currents, sampling rate is 800K, also can be made as 1.6 megahertzes, in order to be complementary with preposition amplifier, PT, CT secondary side require be output as ± 10V of maximum; A/D conversion chip in digital to analog converter chip A/D is selected AD8553: sampling rate 800K, carries sampling hold circuit, uses external reference voltage, external clock, low-power consumption, low noise, ternary output.
Digital signal processing module II based on FPGA: comprise corresponding peripheral circuit and A/D sampling module and the data processing module all realized in FPGA inside; Wherein: the A/D sampling module, for controlling the A/D conversion, is sent into storer DDR2 and FLASH to transformation result, forms the corresponding fault data first address of fault initiating; FPGA is driven by the crystal oscillator of the high stability of external 80 megahertzes, and the AD that produces 800 KHz at the inner frequency division of FPGA triggers signal constantly, and this trigger pip is undertaken synchronously by the pps pulse per second signal of GPS.The data that collect are by impact damper, and direct circulation is stored in storer DDR2; Data processing module is for the treatment of original sampling data, comprising: the shifting out of the differentiation of fault initiating, fault data, and the processing of wavelet transformation program;
The inner pattern that starts module employing soft start of FPGA, after carrying out the criterion of part starting algorithm by the electric current and voltage data to collecting, start the address of simultaneously recording Startup time with the form guiding of interrupting.After fault initiating, time delay through certain hour, fault data shifts out the module dma module and starts working, upwards find the fault data of self-defined length constantly from interrupting address, comprise before fault and fault after data, fault data length generally is set as being not more than 1 second, fault data is moved out to fault data storage space in the storer DDR2 of system assignment, this space size is 64M, can hold fault data more than 1000 simultaneously, simultaneously, this fault data also will store in FLASH, as effective backup of data.
Digital signal processor module FPGA is chosen as the CycloneIV chip, is mainly used in data and processes and analyze, and has powerful parallel processing capability, has speed fast, the characteristics that precision is high.
Communication module III: adopt IP101 PHY chip, for gathering and result of calculation with other plate or background computer exchange.
Because the MAC function is contained in FPGA inside, in peripheral circuit, added the IP101 PHY chip of Taiwan Jiu Yang company to realize network communicating function.IP101 PHY chip is supported the 10-100M adaptive network transmission of IEEE802.3/802.3u, support identification MDI/MDIX function automatically, adopt the 48-pinLQFP packaged type, chip only has the low power dissipation design saving energy very of 3.3v voltage, and supports automatically to enter the energy-saving standby state.With the connected mode of central processing unit or background computer as shown in Figure 2, be initiatively to send out data to background processor by FPGA, the mode of Adoption Network communication, can take full advantage of the reliable and stable advantage of Internet Transmission, and support the function of breakpoint transmission and re-transmission etc.
If three-phase current waveform to be sampled as shown in Figure 3, the curve 1 in Fig. 3, curve 2, curve 3 mean respectively the three-phase current of A phase, B phase and C phase; Be applied to travelling wave ranging with the digital-to-analog conversion of the present embodiment high speed and digital signal panel, carry out failure data acquisition and digital signal processing, its function, the course of work and principle are:
1, gather simultaneously and record the analog data of 24 passages;
2, the voltage and current that comes from ultra-high-tension power transmission line is transformed into respectively the electric current of the voltage of 100 volts and 5 amperes or 1 ampere through the voltage and current mutual inductor;
3, the electric current of the voltage of 100 volts and 5 amperes or 1 ampere is transformed into the simulating signal for the positive and negative 10V of collection through Hall element again;
4, the input end of the simulating signal of the Er Shi tetra-positive and negative 10V in tunnel access high speed acquisition board;
5, under the control of FPGA, complete synchronized sampling and the timesharing analog to digital conversion of Er Shi tetra-tunnel simulating signals every 1 microsecond, conversion accuracy is 16;
6, in FPGA, the transformation result of step 3 is pushed into impact damper in order, then enters the DDR2 data-carrier store;
7,, in DDR2, data are recycled to be deposited, from certain unit, store data continuously, institute have living space deposit full after, new data will cover legacy data, Store form as shown in Figure 5;
8, under normal circumstances, data are stored continuously, but FPGA will not do any processing to it;
9, after fault occurs, the start-up circuit in FPGA will work, and send look-at-me, FPGA will record this constantly with storage address correspondingly;
10, after fault occurs, FPGA shifts out module DMA by fault data fault data is shifted out to the circulation memory block, is carried in data space and FLASH storer.
If at t, fault has occurred constantly, in Fig. 3, T=10ms breaks down, electric current will be undergone mutation:
From this constantly for example, through time delay a period of time (2ms), fault data shifts out module DMA will be from the address of last record, the data ，Mei road of upwards finding two cycles amounts to 32 K words (16) (altogether having recorded the fault data window of 40 milliseconds);
11, carry out wavelet transformation or other digital signal processing for the voltage and current data after above-mentioned fault, ask for the fault eigenvalue after wavelet transformation, calculate fault distance.The A of take in the three-phase fault electric current is example mutually, and the maximum of points in Fig. 4 is the fault eigenvalue after A phase wavelet transformation.
12, fault data and result of calculation are delivered in central processing unit or backstage and gone through the network service mouth, thereby complete the task of whole data acquisition and calculation of fault.
Communication software part mainly by two independently thread form, fault handling thread and network service thread, its flow process as shown in Figure 6.The main task of fault handling thread is the register that config failure is processed, and registration interrupts processing function, responding DMA request and handling interrupt service routine, informing network communication thread transmission data.The network service thread is responsible for setting up network service and is connected, and according to channel type, sets up corresponding server end or client, and by patrolling and examining data Dai Fa district, the stipulations that the traveling wave fault data are worked out according to inside are carried out framing, by network, data are sent out.
Claims (1)
1. the high-speed data acquisition based on FPGA and digital signal panel, is characterized in that integrated simulating signal input and A/D modular converter, digital signal processing module and the communication module of arranging;
Described simulating signal input and A/D modular converter comprise: for receiving 12 passage signal conditioning circuits of four circuit voltages or current analog signal, the A/D modular converter be connected with described signal conditioning circuit; Described A/D modular converter carries sampling hold circuit, uses external reference voltage and external clock, ternary output;
Described digital signal processing module comprises: the FPGA module be connected with described A/D modular converter, the storer DDR2 and the data-carrier store FLASH that with described FPGA module, are connected, the DSP program provided for described FPGA module is stored in described DDR2 or FLASH; Described digital signal processing module completes following digital signal processing:
A, process original sampling data, comprising: the shifting out and the processing of wavelet transformation of the differentiation of fault initiating, fault data;
B, utilize the FPGA module to realize built-in network, the built-in network of take is realized information interaction as carrier; The inner pattern that starts module employing soft start of described FPGA, after carrying out the criterion of part starting algorithm by the voltage to collecting or current data, start the address of simultaneously recording Startup time with the form guiding of interrupting; After fault initiating through time delay, fault data shifts out module DMA and starts working, upwards find the fault data of self-defined length constantly from interrupting address, fault data length is set and is not more than 1s, comprise before fault and fault after total data, and be moved out to the fault data storage space in the storer DDR2 of system assignment;
C, with described storer DDR2 storage failure data, and store in FLASH described fault data into effective backup as data;
Described communication module is connected with described FPGA module, and the Adoption Network physical chip matches with the built-in network of FPGA, realizes and other plate or background computer exchange collection and result of calculation;
Digital signal processing module comprises corresponding peripheral circuit and A/D sampling module and the data processing module all realized in FPGA inside; Wherein: the A/D sampling module, for controlling the A/D conversion, is sent into storer DDR2 and FLASH to transformation result, forms the corresponding fault data first address of fault initiating; Data processing module is for the treatment of original sampling data, comprising: the shifting out of the differentiation of fault initiating, fault data, and the processing of wavelet transformation;
The inner pattern that starts module employing soft start of FPGA, after carrying out the criterion of part starting algorithm by the electric current and voltage data to collecting, start the address of simultaneously recording Startup time with the form guiding of interrupting; After fault initiating, time delay through certain hour, fault data shifts out the module dma module and starts working, upwards find the fault data of self-defined length constantly from interrupting address, comprise before fault and fault after data, fault data length generally is set as being not more than 1 second, fault data is moved out to fault data storage space in the storer DDR2 of system assignment, this space size is 64M, can hold fault data more than 1000 simultaneously, simultaneously, this fault data also will store in FLASH, as effective backup of data; Under normal circumstances, data are stored continuously, but FPGA will not do any processing to it; After fault occurs, the inside start-up circuit in FPGA will be worked, and send look-at-me, and FPGA will record and interrupt constantly with these moment data, having the address in DDR2.
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| CN102401871B (en) * | 2011-11-29 | 2014-04-30 | 安徽继远电网技术有限责任公司 | Failure message integrated device based on FPGA and ARM hardware platform |
| CN102624391A (en) * | 2012-04-08 | 2012-08-01 | 安徽继远电网技术有限责任公司 | High-precision IRIG-B code timing and decoding board |
| CN102968512B (en) * | 2012-07-05 | 2015-04-29 | 无锡普智联科高新技术有限公司 | Multichannel SSI (small scale integration) data collecting module based on MicroBlaze soft core |
| CN103412966B (en) * | 2013-07-18 | 2017-02-08 | 记忆科技(深圳)有限公司 | High-speed data collection and storage device |
| CN104155545A (en) * | 2014-07-28 | 2014-11-19 | 广西电网公司电力科学研究院 | Multichannel analog quantity acquisition module based on GPS signals |
| CN104570855A (en) * | 2014-12-18 | 2015-04-29 | 文曲 | FPGA-based data acquisition system and method |
| CN106843023B (en) * | 2015-12-03 | 2019-08-06 | 国网智能电网研究院 | A kind of electric power data acquisition system based on FPGA |
| CN108872809A (en) * | 2018-06-20 | 2018-11-23 | 南京中大智能科技有限公司 | A kind of instrument for measuring partial discharge's high speed Wave record method |
| CN111930099A (en) * | 2020-07-30 | 2020-11-13 | 珠海市鸿瑞信息技术股份有限公司 | One-way FPGA acquisition fault maintenance analysis system of industrial control network |
| CN113114254B (en) * | 2021-05-18 | 2022-08-26 | 天津凯发电气股份有限公司 | High-speed multi-channel synchronous analog quantity acquisition control method |
| CN113341904A (en) * | 2021-06-30 | 2021-09-03 | 杭州布厂汇网络科技有限公司 | High-speed data acquisition equipment and method based on industrial internet platform |
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| CN101350036B (en) * | 2008-08-26 | 2010-09-15 | 天津理工大学 | High speed real-time data acquisition system |
| CN101587499B (en) * | 2009-06-24 | 2010-12-08 | 北京理工大学 | Multi-channel signal acquiring system based on NAND |
| CN201465110U (en) * | 2009-06-29 | 2010-05-12 | 北京理工大学 | 32-channel synchronous signal acquisition board |
| CN101777759B (en) * | 2010-03-23 | 2013-01-02 | 西安交通大学 | Complete set of protection devices for ultrahigh-speed DC line on basis of single-ended transient signals and protection method thereof |
| CN202049485U (en) * | 2011-06-03 | 2011-11-23 | 安徽继远电网技术有限责任公司 | High-speed data acquiring and digital signal processing board based on FPGA |
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