CN103513650A - High-voltage direct-current electricity transmission converter valve control equipment and wave recording monitoring system thereof - Google Patents
High-voltage direct-current electricity transmission converter valve control equipment and wave recording monitoring system thereof Download PDFInfo
- Publication number
- CN103513650A CN103513650A CN201310438443.4A CN201310438443A CN103513650A CN 103513650 A CN103513650 A CN 103513650A CN 201310438443 A CN201310438443 A CN 201310438443A CN 103513650 A CN103513650 A CN 103513650A
- Authority
- CN
- China
- Prior art keywords
- data
- fpga
- record ripple
- converter valve
- telecommunication management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
- G05B23/0221—Preprocessing measurements, e.g. data collection rate adjustment; Standardization of measurements; Time series or signal analysis, e.g. frequency analysis or wavelets; Trustworthiness of measurements; Indexes therefor; Measurements using easily measured parameters to estimate parameters difficult to measure; Virtual sensor creation; De-noising; Sensor fusion; Unconventional preprocessing inherently present in specific fault detection methods like PCA-based methods
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Programmable Controllers (AREA)
- Testing And Monitoring For Control Systems (AREA)
Abstract
The invention discloses high-voltage direct-current electricity transmission converter valve control equipment and a wave recording monitoring system thereof. A CPU and an FPGA which are connected with each other are included. The FPGA is connected with an expanding memory and a communication management processor which is provided with a communication interface used for being connected with an upper computer. The communication management processor is further connected with a temporary storage memory. When the valve control equipment is in fault or needs to store data, the FPGA starts fault wave recording, and original wave recording data are stored in the expanding memory. When the upper computer needs to read the data, the data are read from the expanding memory through the FPGA and are cached in a double-port RAM of the FPGA, the communication management processor reads the data from the double-port RAM through a bus, and the data are sent to the upper computer through the communication interface. According to the control equipment and a wave recording control method, the FPGA and the communication management processor are used for achieving wave recording data recording and communication with the upper computer respectively, each part performs its own duty, processing speed is improved, and the stability of equipment operation is guaranteed.
Description
Technical field
The invention belongs to the high-voltage dc transmission electrical domain of electric system, be specifically related to a kind of high voltage direct current transmission converter valve opertaing device and record ripple control method.
Background technology
Wave recording device is called electric system " black box ", is that power equipment is monitored requisite automatic safety device, and system status and operational factor before and after its can be when equipment failure automatic record trouble, for fault diagnosis and investigation provide important evidence.Specific to high-voltage dc transmission electrical domain, valve control equipment is as the bottom opertaing device of converter valve, mainly by CPU and FPGA, connected to form, it is controlled function and is mainly the required start pulse signal that the control signal sending over according to control system produces triggering converter valve, and the signal message of processing is digital quantity signal.In valve control equipment, increase record wave energy, the information recording should be able to accurately reflect that control sequential, valve control equipment running status and the valve control equipment of control system are to triggering sequential of converter valve etc., to help seeking system failure cause in uniting and adjustment at the scene and system experimentation stage, while being especially difficult to locate failure cause position between utmost point control system and valve control equipment, can provide reliable strong evidence to locate failure cause.
In addition, in the DC transmission engineering putting into operation at present, except valve control equipment, miscellaneous equipment directly or indirectly all can pass through failure wave-recording function playback controls process, valve control equipment increase record wave energy seems and is extremely necessary, at valve control equipment, increase after failure wave-recording function, for fault analysis after the accident at whole station, location causes of incident, find solution and will play effect more easily, and in high voltage direct current converter valve field, also do not occur having at present the converter valve opertaing device of failure wave-recording function.
Summary of the invention
The object of this invention is to provide a kind of high voltage direct current transmission converter valve opertaing device, to solve existing valve control equipment, do not possess the problem of failure wave-recording function, a kind of record ripple control method of using this opertaing device is provided simultaneously.
In order to realize above object, the technical scheme that high voltage direct current transmission converter valve opertaing device of the present invention adopts is: comprise interconnective CPU and the FPGA with record wave energy, FPGA is connected with an extended memory and device is processed in a telecommunication management, described telecommunication management is processed device and is provided with for be connected, upload the communication interface of recorder data with host computer, and this telecommunication management is processed device and is also provided with the memory interface for expanding; When valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory; When host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in the two-port RAM of FPGA, telecommunication management is processed device by bus reading out data from two-port RAM, by communication interface, sends to host computer.
Described telecommunication management is processed device and is provided with for the address toggle switch of address is set.
It is ARM that device is processed in described telecommunication management, DSP or single-chip microcomputer; Described communication interface is Ethernet interface or USB interface.
Described extended memory is SDRAM, and temporary storage is flash storer.
This converter valve opertaing device adopts Control card, and the panel of described Control card is provided with record ripple and drops into switch, manually boot record ripple button and manually empty flash memory button.
The technical scheme that the record ripple control method of converter valve opertaing device of the present invention adopts is: the method comprises the steps:
(1) when valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory;
(2) when host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in two-port RAM, telecommunication management is processed device by bus reading out data from two-port RAM;
(3) telecommunication management is processed device the data that read from FPGA is sent to host computer by communication interface.
Triggering record ripple in step (1) starts and has manually and automatic two kinds of modes: when manually booting record ripple, by host computer, issue enabled instruction, process device be handed down to FPGA and start through telecommunication management; When adopting while automatically starting record ripple, according to the operating mode of valve control equipment, independently set, the autonomous condition of setting be valve control equipment control model change or system state abnormal.
When record ripple does not start, data are in the not log-on data memory block circulation covering storage of record ripple; When record ripple starts, clock and enabling address while first needing startup write extended memory, and then the recorder data after starting is stored, the data after record ripple starts are in record ripple log-on data storage area stores, until this record ripple log-on data memory block is write full; When once recording ripple, complete Shi， address and jump to next time record ripple and do not start place, Shi data storage area and again start circulation and cover storage.
Host computer will be processed the failure wave-recording file of the Generating Data File standard format of device reception from telecommunication management.
This valve control equipment also has the recorder data of extended memory and removes and query function.High voltage direct current transmission converter valve opertaing device of the present invention and record ripple control method are based on existing converter valve opertaing device and guarantee to increase record wave energy on basis that the former all functions of valve control equipment are not affected, realization to valve control device interior status signal, control system to the start pulse signal of valve control equipment, the record that valve control equipment is sent to the start pulse signal of converter valve, realize data acquisition, start record ripple, the generation of recorder data source document, and it is temporary at valve control device interior expansion Quick Extended memory devices, to be used for recording ripple raw data file; In valve control equipment, increase telecommunication management and process device and pin-saving chip, carry out the storage of recorder data and communicating by letter of recorder data, original recorder data is sent to host computer, the record ripple raw data file that host computer receiving valve control equipment sends over.At valve control equipment, increase after failure wave-recording function, for fault analysis after the accident at whole station, location causes of incident, finds solution and will play effect more easily.Opertaing device of the present invention and record ripple control method adopt FPGA and telecommunication management process record that device realizes respectively recorder data with the communicating by letter of host computer, Each performs its own functions, improved processing speed, guaranteed the stability of equipment operation.
Accompanying drawing explanation
Fig. 1 is the system principle diagram of invention valve control equipment;
Fig. 2 is block diagram for software modules of the present invention;
Fig. 3 is the workflow diagram of FPGA;
Fig. 4 is record ripple raw data definition schematic diagram;
Fig. 5 is that device and FPGA exchanges data process flow diagram are processed in telecommunication management;
Fig. 6 is that device and host computer data communication process flow diagram are processed in telecommunication management;
Fig. 7 is original recorder data processing flow chart;
Fig. 8 is that SDRAM. reads address process flow diagram;
Fig. 9 is that two-port RAM reads in and reads address figure.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment, the present invention is described further.
Record wave energy is to realizing, the record of interface signal, valve control working state signal between valve control and valve, valve control and control system to be monitored and record.The involved converter valve opertaing device of the present embodiment conventionally can be called converter valve control system in this area, also can be called valve control equipment or valve control system.
Be illustrated in figure 1 the theory diagram of high voltage direct current transmission converter valve opertaing device of the present invention, as seen from the figure, this system comprises interconnective CPU and the FPGA with record wave energy, FPGA is connected with an extended memory and one and is provided with for uploading the telecommunication management of the communication interface of recorder data and processes device, and telecommunication management is processed device and is also connected with the temporary storage for temporary recorder data.
Be illustrated in figure 2 the block diagram for software modules of the present embodiment, FPGA comprise record ripple fault initiating module, extended memory write address and write data generating module, extended memory is read address generating module, extended memory module for reading and writing, two-port RAM data access module and FPGA and telecommunication management processing device interface module, when valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory; When host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in the two-port RAM of FPGA, telecommunication management is processed device by bus reading out data from two-port RAM, by communication interface, sends to host computer.
This converter valve opertaing device of the present embodiment adopts Control card, mode by expansion SDRAM on valve control equipment Control card increases memory capacity buffer memory SDRAM, by FPGA, be used for realizing the startup of failure wave-recording, tissue and the generation of failure wave-recording raw data file, and recorder data is buffered in buffer memory SDRAM.
The temporary storage of the present embodiment adopts flash storer, the record ripple raw data file that telecommunication management processing device processor is used for that FPGA is generated dumps to the flash storer of expansion, realize the temporary of data file, and by telecommunication management, process device and control extension standards Ethernet interface, realize the upload function of data file.
Telecommunication management is processed device and is adopted ARM, DSP or single-chip microcomputer; On valve control equipment Control card, increase communication interface, communication interface adopts Ethernet interface or USB interface.
On the panel of Control card, being provided with record ripple drops into switch, manually boots record ripple button and manually empty flash memory button, to facilitate debugging to start, record ripple and the upper temporary recorder data file that does not need analysis of cleaning flash, can verify the impact of record wave energy on the former control function of valve control equipment simultaneously.
In telecommunication management, process on device and increase address toggle switch, telecommunication management is set and processes Qi address, for realizing a plurality of valve control cabinets, be connected with host computer.
The record ripple control method workflow of converter valve opertaing device of the present invention as shown in Figure 3, comprises the steps:
(1) when valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory;
The entry condition of record ripple arranges according to the needs of control and systematic analysis, and starting judgement is that fault is made to preliminary judgement to determine whether to start record ripple, and the startup requirement of record ripple accurately, quick.According to the needs of DC transmission engineering systematic analysis, trigger in the present embodiment record ripple and start and have manually and automatic two kinds of modes: when manually booting record ripple, by host computer, issue enabled instruction, through telecommunication management, process device and be handed down to FPGA and start; When adopting automatic startup record ripple; according to the operating mode of valve control equipment, independently set; setting record ripple condition is: valve control equipment control model change or system state abnormal; when valve control equipment enters preliminary examination pattern, release, locking and occur the abnormal or system failure of interface signal, tripping operation, start record ripple, and sampling time in every kind of situation also can be because of the difference of entry condition difference to some extent.
The generative process of record ripple raw data file is as follows: according to the standard-required of failure wave-recording, complete documentation failure process recorder data need to comprise fault one section of system state data after system state data and fault for the previous period.For starting system state data for the previous period, record trouble need to open up a systematic sampling data buffer, with the image data before the time of buffer memory trouble spot, as occurred, start record ripple, the data of Ze Jiang buffer zone are preserved as recorder data file, otherwise this buffer data of real-time update, take and guarantee the sampled data of institute's buffered data as a period of time before current time.Here with buffering, record ripple front 10 milliseconds of time-sampling data start-up time, the sample frequency of 1MHZ, 32 passage meters, the buffer pool size needing is 40K byte, 320Kbit.
As shown in Figure 4, record ripple raw data file predetermined format is: not have the binary format of separator to preserve, order is followed successively by the time, sampling number of failure wave-recording that starts, signal value, the signal value of each sampling channel of sampled point, the to the last signal value of each sampling channel of sampled point for the second time of each sampling channel of sampled point for the first time.
(2) when host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in the two-port RAM that FPGAIP core opens up, mode reading out data from two-port RAM that device interrupts by bus utilization is processed in telecommunication management;
The telecommunication management of the present embodiment is processed device and FPGA and is carried out exchanges data while reading recorder data file, by FPGA as main control equipment, by FPGA, in spare time, initiatively propose to send data, whether telecommunication management processing device is monitored constantly has data to need to receive, if in the middle of a data file of transmission, there is new entry condition, FGPA controller can interrupt sending under the condition of a data file of continuation buffering of having the ability, keep behind scene, remove to respond new startup record ripple, after new record ripple finishes, restoring scene, data before continuing transmit, its data exchange mode as shown in Figure 5.
(3) data that telecommunication management processing device is uploaded FPGA send to host computer by communication interface: the exchanges data that device and host computer are processed in telecommunication management is mainly by the communication interface of expansion, for host computer format conversion, generate the failure wave-recording formatted file of standard and preserve.The data-transmission mode of telecommunication management processing device and host computer as shown in Figure 6.
The function of host computer is as follows: (1) is realized with telecommunication management and processed device by the communication of communication interface; (2) from telecommunication management, process device and receive record ripple raw data file; (3) according to processing the failure wave-recording file of the Generating Data File standard format that device receives from telecommunication management and being saved in the file system of host computer.
The extended memory of the present embodiment is selected SDRAM, and telecommunication management is processed device and selected arm processor, is illustrated in figure 7 recorder data processing flow chart, and as seen from the figure, after powering on, first FPGA and extended memory SDRAM complete initial work.After initial work completes, FPGA starts SDRAM to write the 32 road port data of record ripple while not starting.
Be illustrated in figure 2 the block diagram for software modules of the present embodiment, as follows to the principle of work of each module:
1, SDRAM write address and data generating module: when record ripple does not start, data are in the not log-on data memory block circulation covering storage of record ripple; When record ripple starts, clock and enabling address while first needing startup write extended memory, and then the recorder data after starting is stored, the data after record ripple starts are in record ripple log-on data storage area stores, until this record ripple log-on data memory block is write full; When once recording ripple, complete Shi， address and jump to next time record ripple and do not start place, Shi data storage area and again start circulation and cover storage.
SDRAM write address and data generating module are main according to sending into the record ripple starting state signal in module, and record ripple number of times signal determines that the concrete memory address ，Jiang Ci address of recorder data sends the module for reading and writing to SDRAM.
2, SDRAM reads address generating module: ARM issues after read data order, can issue the start address of read data and end address to FPGA.Read address generating module and send to one by one module for reading and writing according to the address realm ，Jiang address sending, carry out the read operation of data.Corresponding one by one with address in order to realize the read operation of data, while meeting the following conditions at the same time, read address generating module and start output and read address.
(1) SDRAM record ripple enabling signal is invalid; (2) two-port RAM is not write full.
Meet after above-mentioned condition, need read effectively (1) by the read-write control signal of controlling SDRAM to write invalidate (0), the address of reading that FPGA issues ARM is sent into SDRAM successively, and its idiographic flow as shown in Figure 8.
3, SDRAM module for reading and writing: the parameter that need send into module when SDRAM module for reading and writing is operated is:
| Parameter | Function |
| clk_i, | System clock |
| dram_clk_i, | SDRAM clock, 100MHZ or 133MHZ |
[0054]?
| rst_i, | Reset signal |
| dll_locked, | SDRAM sheet selects control signal |
| addr_i, | Address reads and writes data |
| dat_i | While writing state, data writing |
| we_i | Read-write state high level is for writing, and low level is for reading |
| stb_i, | SDRAM state, high level is idle |
| cyc_i | Reserved control signal, normal read-write is high level |
SDRAM module for reading and writing output parameter is:
When the read-write state control signal we_i of SDRAM module for reading and writing is high level, module, according to sending into address register addr_i ， address, writes SDRAM by the data in data register dat_i; When we_i is low level, module is according to sending into address register addr_i ， address, by the data reading of corresponding address to output register dat_o.
4, two-port RAM data access module: the size of the two-port RAM of opening up in the present embodiment is 256*16b is mainly for buffer memory recorder data.ARM issues start address and the end address of institute's read data, and FPGA reads the data in corresponding SDRAM in two-port RAM after receiving order, after two-port RAM is write completely, sends interruptive command notice RAM and reads recorder data.If RAM after writing completely fails the data of the corresponding address scope issuing to run through,, after ARM runs through the data in two-port RAM, continue the data in SDRAM to read to two-port RAM, until the number of the desired address realm of ARM is run through.
Two-port RAM, when carrying out write operation, writes 32b at every turn; During read operation, read the concrete two-port RAM of 16b. at every turn and read in and read address as shown in Figure 9.
5, SDRAM removes, exits and record ripple enquiry module:
(1) when ARM sends clear instruction to FPGA, FPGA need complete following operation:
1 > storage record ripple time number register sets to 0;
2 > the storage record current buffer zone of ripple numbered register sets to 0;
After more than having operated, will remove result notice ARM.
(2) when ARM sends record ripple query statement to FPGA, FPGA need complete following operation:
1 > storage record ripple number of times content of registers is uploaded to ARM;
2 > the storage record current buffer zone of ripple numbered register content uploading is to ARM.
6, FPGA and ARM interface module: FPGA and ARM interface module are mainly that FPGA controller is by data bus, to ARM transmission or reception recorder data and steering order.The address bus that the present embodiment is used is 10, can meet the demand of interaction data and order completely.Specific address bus definition is as shown in the table:
The communication interface of the present embodiment provides the form of Ethernet interface and USB interface, can certainly adopt the interface shapes such as RS232, optical fiber, and these similar common technology means that are transformed to those skilled in the art, drop in protection domain of the present invention.
Claims (10)
1. a high voltage direct current transmission converter valve opertaing device, it is characterized in that: comprise interconnective CPU and the FPGA with record wave energy, FPGA is connected with an extended memory and device is processed in a telecommunication management, described telecommunication management is processed device and is provided with for be connected, upload the communication interface of recorder data with host computer, and this telecommunication management is processed device and is also provided with the memory interface for expanding; When valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory; When host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in the two-port RAM of FPGA, telecommunication management is processed device by bus reading out data from two-port RAM, by communication interface, sends to host computer.
2. high voltage direct current transmission converter valve opertaing device according to claim 1, is characterized in that: described telecommunication management is processed device and is provided with for the address toggle switch of address is set.
3. high voltage direct current transmission converter valve opertaing device according to claim 2, is characterized in that: it is ARM that device is processed in described telecommunication management, DSP or single-chip microcomputer; Described communication interface is Ethernet interface or USB interface.
4. according to the high voltage direct current transmission converter valve opertaing device described in claim 2 or 3, it is characterized in that: described extended memory is SDRAM, temporary storage is flash storer.
5. high voltage direct current transmission converter valve opertaing device according to claim 4, it is characterized in that: this converter valve opertaing device adopts Control card, the panel of described Control card is provided with record ripple and drops into switch, manually boot record ripple button and manually empty flash memory button.
6. a record ripple control method for converter valve opertaing device, is characterized in that, the method comprises the steps:
(1) when valve control equipment occurs extremely or needs save data, FPGA starts failure wave-recording, and original recorder data is deposited in extended memory;
(2) when host computer needs reading out data, by FPGA, data are read from extended memory, be buffered in two-port RAM, telecommunication management is processed device by bus reading out data from two-port RAM;
(3) telecommunication management is processed device the data that read from FPGA is sent to host computer by communication interface.
7. the record ripple control method of converter valve opertaing device according to claim 6, it is characterized in that: in step (1), triggering the startup of record ripple has manually and automatic two kinds of modes: when manually booting record ripple, by host computer, issue enabled instruction, through telecommunication management processing device, be handed down to FPGA and start; When adopting while automatically starting record ripple, according to the operating mode of valve control equipment, independently set, the autonomous condition of setting be valve control equipment control model change or system state abnormal.
8. the record ripple control method of converter valve opertaing device according to claim 6, is characterized in that: when record ripple does not start, data are in the not log-on data memory block circulation covering storage of record ripple; When record ripple starts, clock and enabling address while first needing startup write extended memory, and then the recorder data after starting is stored, the data after record ripple starts are in record ripple log-on data storage area stores, until this record ripple log-on data memory block is write full; When once recording ripple, complete Shi， address and jump to next time record ripple and do not start place, Shi data storage area and again start circulation and cover storage.
9. the record ripple control method of converter valve opertaing device according to claim 6, is characterized in that: host computer will be processed the failure wave-recording file of the Generating Data File standard format of device reception from telecommunication management.
10. according to the record ripple control method of the converter valve opertaing device described in claim 6～9, it is characterized in that: this valve control equipment also has the recorder data of extended memory and removes and query function.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438443.4A CN103513650B (en) | 2013-09-24 | 2013-09-24 | The record ripple control method of converter valve opertaing device |
| PCT/CN2014/087204 WO2015043456A1 (en) | 2013-09-24 | 2014-09-23 | High-voltage direct-current transmission converter valve control device and oscillation recording monitoring system thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310438443.4A CN103513650B (en) | 2013-09-24 | 2013-09-24 | The record ripple control method of converter valve opertaing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103513650A true CN103513650A (en) | 2014-01-15 |
| CN103513650B CN103513650B (en) | 2015-12-02 |
Family
ID=49896553
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310438443.4A Active CN103513650B (en) | 2013-09-24 | 2013-09-24 | The record ripple control method of converter valve opertaing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103513650B (en) |
| WO (1) | WO2015043456A1 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015043456A1 (en) * | 2013-09-24 | 2015-04-02 | 许继电气股份有限公司 | High-voltage direct-current transmission converter valve control device and oscillation recording monitoring system thereof |
| CN105652110A (en) * | 2015-12-21 | 2016-06-08 | 中国西电电气股份有限公司 | Converter valve secondary control interface fault signal intelligent recording device |
| CN107589320A (en) * | 2016-07-08 | 2018-01-16 | 台达电子企业管理（上海）有限公司 | The Wave record method and wave recording device of power model |
| CN108983110A (en) * | 2018-04-16 | 2018-12-11 | 许继集团有限公司 | A kind of power supply reliability detection system of converter valve monitoring device |
| CN109830931A (en) * | 2018-10-29 | 2019-05-31 | 全球能源互联网研究院有限公司 | A kind of embedded type fault wave recording device suitable for DC control and protection system |
| CN112180791A (en) * | 2020-09-29 | 2021-01-05 | 苏州英威腾电力电子有限公司 | Multiplexing monitoring expansion card and frequency converter |
| CN112346386A (en) * | 2020-11-11 | 2021-02-09 | 中国南方电网有限责任公司超高压输电公司广州局 | Method for realizing master control unit of direct current transmission converter valve monitoring system based on FSM and multitask |
| CN112688349A (en) * | 2020-12-16 | 2021-04-20 | 国网上海能源互联网研究院有限公司 | Universal control device and method for source network load storage interactive system |
| CN113900427A (en) * | 2021-10-19 | 2022-01-07 | 中国南方电网有限责任公司超高压输电公司贵阳局 | Method for rapidly positioning fault of converter valve control system |
| CN114123498A (en) * | 2021-11-16 | 2022-03-01 | 许继集团有限公司 | Wave recording control system for valve control equipment of direct-current transmission system |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461392A (en) * | 2014-12-08 | 2015-03-25 | 中北大学 | CH378-based high-speed serial data U disk recording device |
| CN109828177B (en) * | 2019-03-25 | 2024-02-20 | 广西电网有限责任公司钦州供电局 | Fault wave recording device of direct current system |
| CN111740578A (en) * | 2020-07-02 | 2020-10-02 | 中国南方电网有限责任公司超高压输电公司天生桥局 | Double-set redundancy switching method for valve control system |
| CN112379837B (en) * | 2020-11-13 | 2023-05-02 | 许继集团有限公司 | Method and device for generating wave recording file of feeder terminal |
| CN113341198B (en) * | 2021-06-01 | 2023-03-17 | 青岛东软载波科技股份有限公司 | Power line wave recording method and system based on metering chip register |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040098538A1 (en) * | 2002-11-18 | 2004-05-20 | Horn Robert L. | Caching in a virtualization system |
| CN1570794A (en) * | 2004-05-14 | 2005-01-26 | 北京博创兴工科技有限公司 | Numerical control system for machine tool |
| US20090161272A1 (en) * | 2007-12-21 | 2009-06-25 | General Electric Company | Arc detection system and method |
| CN102298106A (en) * | 2011-05-19 | 2011-12-28 | 河海大学 | FPGA (field programmable gate array)-based arc monitoring system in valve hall |
| CN102402201A (en) * | 2011-10-24 | 2012-04-04 | 华中科技大学 | Multi-axis motion control system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1291322C (en) * | 2004-06-24 | 2006-12-20 | 张小波 | A two-channel synchronous recording and storing method and equipment for fault recording data |
| US8098504B2 (en) * | 2006-01-18 | 2012-01-17 | Abb Technology Ltd. | Converter station for connecting an AC system to an end of an HVDC transmission line |
| BR112013014380B1 (en) * | 2010-12-09 | 2020-10-20 | State Grid Corporation Of China | cascading converter station and cascading multiterminal hvdc power transmission system |
| CN202121298U (en) * | 2011-07-19 | 2012-01-18 | 中国南方电网有限责任公司超高压输电公司检修试验中心 | Microcomputer protective system of converter transformer |
| CN103197184A (en) * | 2013-04-03 | 2013-07-10 | 河海大学 | Fault wave recording device with impact load considered |
| CN103513650B (en) * | 2013-09-24 | 2015-12-02 | 许继电气股份有限公司 | The record ripple control method of converter valve opertaing device |
-
2013
- 2013-09-24 CN CN201310438443.4A patent/CN103513650B/en active Active
-
2014
- 2014-09-23 WO PCT/CN2014/087204 patent/WO2015043456A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040098538A1 (en) * | 2002-11-18 | 2004-05-20 | Horn Robert L. | Caching in a virtualization system |
| CN1570794A (en) * | 2004-05-14 | 2005-01-26 | 北京博创兴工科技有限公司 | Numerical control system for machine tool |
| US20090161272A1 (en) * | 2007-12-21 | 2009-06-25 | General Electric Company | Arc detection system and method |
| CN102298106A (en) * | 2011-05-19 | 2011-12-28 | 河海大学 | FPGA (field programmable gate array)-based arc monitoring system in valve hall |
| CN102402201A (en) * | 2011-10-24 | 2012-04-04 | 华中科技大学 | Multi-axis motion control system |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015043456A1 (en) * | 2013-09-24 | 2015-04-02 | 许继电气股份有限公司 | High-voltage direct-current transmission converter valve control device and oscillation recording monitoring system thereof |
| CN105652110A (en) * | 2015-12-21 | 2016-06-08 | 中国西电电气股份有限公司 | Converter valve secondary control interface fault signal intelligent recording device |
| CN107589320A (en) * | 2016-07-08 | 2018-01-16 | 台达电子企业管理（上海）有限公司 | The Wave record method and wave recording device of power model |
| CN108983110A (en) * | 2018-04-16 | 2018-12-11 | 许继集团有限公司 | A kind of power supply reliability detection system of converter valve monitoring device |
| CN108983110B (en) * | 2018-04-16 | 2020-10-27 | 许继集团有限公司 | Power supply reliability detection system of converter valve monitoring equipment |
| CN109830931A (en) * | 2018-10-29 | 2019-05-31 | 全球能源互联网研究院有限公司 | A kind of embedded type fault wave recording device suitable for DC control and protection system |
| CN112180791A (en) * | 2020-09-29 | 2021-01-05 | 苏州英威腾电力电子有限公司 | Multiplexing monitoring expansion card and frequency converter |
| CN112346386A (en) * | 2020-11-11 | 2021-02-09 | 中国南方电网有限责任公司超高压输电公司广州局 | Method for realizing master control unit of direct current transmission converter valve monitoring system based on FSM and multitask |
| CN112688349A (en) * | 2020-12-16 | 2021-04-20 | 国网上海能源互联网研究院有限公司 | Universal control device and method for source network load storage interactive system |
| CN113900427A (en) * | 2021-10-19 | 2022-01-07 | 中国南方电网有限责任公司超高压输电公司贵阳局 | Method for rapidly positioning fault of converter valve control system |
| CN114123498A (en) * | 2021-11-16 | 2022-03-01 | 许继集团有限公司 | Wave recording control system for valve control equipment of direct-current transmission system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103513650B (en) | 2015-12-02 |
| WO2015043456A1 (en) | 2015-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103513650A (en) | High-voltage direct-current electricity transmission converter valve control equipment and wave recording monitoring system thereof | |
| US10229019B2 (en) | Power fail circuit for multi-storage-device arrays | |
| CN103345189B (en) | A kind of controller and a kind of power-off protection method | |
| CN106300638A (en) | A kind of low-voltage power down overrun control and control method | |
| CN108228394A (en) | A kind of double BIOS Flash control systems of server and method | |
| CN102736594B (en) | Modular design method of unified platform of intelligent power distribution terminal | |
| CN101261532B (en) | Electronic device energy supply control module and energy supply control method | |
| CN102289414A (en) | Memory data protection device and method | |
| CN103019870A (en) | Method and communication equipment for processing reset signal | |
| CN203858321U (en) | Distribution fault recorder based on DSP and CPLD | |
| CN104682544A (en) | Spare power automatic switching method and device | |
| CN104731736A (en) | Time synchronization device, method and system | |
| CN104298147A (en) | Power management device and method | |
| CN103309422A (en) | Power supply device | |
| CN207851170U (en) | Frequency converter black box subsystem | |
| CN111726563A (en) | Video storage device for train video monitoring system | |
| CN103150288B (en) | A kind of SOC of quick turn-on and its implementation | |
| CN100527184C (en) | Method for collecting transient data in power system | |
| CN101202458A (en) | Power supply circuit | |
| CN103744616A (en) | Data management method for battery management system | |
| CN202435022U (en) | Electrified railway traction network microcomputer feed line protection device | |
| CN107731260A (en) | A kind of SSD method of supplying power to, system and SSD | |
| CN210111618U (en) | Energy storage coordination control device | |
| CN112068686A (en) | Recording device and method for black box data of server power supply | |
| CN211264123U (en) | Digital processor module of station power utilization control device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |