CN107731260A - A kind of SSD method of supplying power to, system and SSD - Google Patents
A kind of SSD method of supplying power to, system and SSD Download PDFInfo
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- CN107731260A CN107731260A CN201711091493.4A CN201711091493A CN107731260A CN 107731260 A CN107731260 A CN 107731260A CN 201711091493 A CN201711091493 A CN 201711091493A CN 107731260 A CN107731260 A CN 107731260A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
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- G11C16/30—Power supply circuits
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Abstract
This application discloses a kind of SSD method of supplying power to, applied to the SSD for meeting NVMe standards, including：It is normal when monitoring main power source, powered by the main power source to target loop；When monitoring that the main power source is abnormal, main power source is disconnected, is powered by stand-by power supply to the target loop；Wherein, the stand-by power supply is obtained by auxiliary power combination voltage conversion circuit；Wherein, the magnitude of voltage of the main power source and the stand-by power supply is first voltage, and the magnitude of voltage of the auxiliary power is second voltage.The second voltage of auxiliary power is converted to first voltage as standby voltage by this programme, when main power source power supply occurs abnormal, target loop is powered by stand-by power supply, SSD is worked on, improves the reliability of system.The application further correspondingly discloses the electric power system of SSD a kind of and a kind of SSD.
Description
Technical Field
The invention relates to an NVMe SSD, in particular to a power supply method and system of an SSD and the SSD.
Background
With the continuous maturation of SSD (Solid State Disk) technology and the enhancement of performance, the original SATA interface and AHCI standard gradually become a big bottleneck limiting the performance of SSD. Therefore, as early as 2009, NVMe (Non-Volatile memory standard) was made by companies such as american light, dell, samsung, Marvell, NetAPP, EMC, IDT, etc., in order to establish a new storage specification standard for SSD, which is released from old SATA and AHCI. In 2011, the NVMe standard is officially released from the furnace, the standard is customized according to the characteristics of the SSD, and the new standard relieves various limitations imposed on the SSD by the old standard. In 2017, the latest nvme1.3 was released.
Compared with the AHCI standard, the NVMe standard has the advantages of high IOPS, low time delay, low power consumption, wide driving adaptability and the like. The NVMe standard uses a PCIe bus as a data transmission interface of the SSD, and the PCIe (Peripheral component interconnect Express) bus is a local parallel bus standard developed by PCISIG (PCI special interest group, mainly Intel), and is mainly applied to a motherboard of a computer and a server. At present, almost all mainboards have PCIe slots and have the function of connecting external devices, such as a video card, a memory, a network card, a sound card, a data acquisition card and the like. The most recent standard is pci 4.0.
Currently, the interface supporting NVMe SSD, such as the m.2 interface or the U.2 interface, typically provides three power supplies, which are +12V, +3.3V, and +3.3V _ AUX, respectively. The SSD is usually powered by +12V power, a few SSDs operating at low voltage can be powered by 3.3V, or by +12V and +3.3V respectively for different modules inside the SSD, and 3.3V _ AUX is usually used to power part of the power management logic and special registers, so as to reduce power consumption and shorten system recovery time.
The above scheme requires high reliability of the power supply, and once a problem occurs in the power supply for supplying power to the system or the modules in the system, the SSD may stop working or even be damaged.
Disclosure of Invention
In view of the above, the present invention provides a reliable and safe power supply method and system for an SSD, and the SSD. The specific scheme is as follows:
a power supply method of an SSD is applied to the SSD conforming to NVMe standard, and comprises the following steps:
when the main power supply is monitored to be normal, supplying power to a target loop through the main power supply;
when the main power supply is monitored to be abnormal, the main power supply is disconnected, and power is supplied to the target loop through a standby power supply; the standby power supply is obtained by combining an auxiliary power supply with a voltage conversion circuit;
the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage.
Preferably, the power supply method further includes:
and when the main power supply and the auxiliary power supply are monitored to be abnormal, stopping supplying power to the target loop.
Preferably, the first voltage is 12V, and the second voltage is 3.3V;
correspondingly, the voltage conversion circuit is a booster circuit.
Correspondingly, the invention discloses a power supply system of an SSD, which is applied to the SSD meeting the NVMe standard, and comprises a main power supply, a standby power supply obtained by combining a secondary power supply and a voltage conversion circuit, a logic circuit and a monitoring circuit, wherein the logic circuit is used for executing the following actions:
when the monitoring circuit monitors that the main power supply is normal, the main power supply supplies power to a target loop;
when the monitoring circuit monitors that the main power supply is abnormal, the main power supply is disconnected, and the standby power supply supplies power to the target loop;
the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage.
Preferably, the logic circuit is further configured to:
and when the monitoring circuit monitors that the main power supply and the standby power supply are abnormal, stopping supplying power to the target loop.
Preferably, the first voltage is 12V, and the second voltage is 3.3V;
correspondingly, the voltage conversion circuit is a booster circuit.
Preferably, the logic circuit specifically includes a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, and a third resistor; wherein,
the drain electrode of the first MOS tube is connected with the main power supply, the grid electrode of the first MOS tube is connected with the first output end of the monitoring circuit, and the source electrode of the first MOS tube is connected with the input end of the target loop;
the drain electrode of the second MOS tube is connected with the standby power supply, the grid electrode of the second MOS tube is connected with the second output end of the monitoring loop, and the source electrode of the second MOS tube is connected with the input end of the target loop;
the first end of the first resistor is connected with the main power supply, and the second end of the first resistor is connected with the first end of the second resistor;
the first end of the second resistor is also connected with the first output end of the monitoring circuit, and the second end of the second resistor is grounded;
and the first end of the third resistor is connected with the second output end of the monitoring circuit, and the second end of the third resistor is grounded.
Preferably, the logic circuit further includes: a first diode and a second diode, wherein:
the source electrode of the first MOS tube is connected with the anode of the first diode;
the source electrode of the second MOS tube is connected with the anode of the second diode;
and the cathode of the first diode and the cathode of the second diode are both connected with the target input end.
Preferably, the monitoring circuit is a circuit powered by an independent power supply.
Correspondingly, the invention also discloses an SSD which comprises the power supply system of the SSD.
The invention discloses a power supply method of an SSD, which is applied to the SSD meeting NVMe standard and comprises the following steps: when the main power supply is monitored to be normal, supplying power to a target loop through the main power supply; when the main power supply is monitored to be abnormal, the main power supply is disconnected, and power is supplied to the target loop through a standby power supply; the standby power supply is obtained by combining an auxiliary power supply with a voltage conversion circuit; the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage. According to the method, the second voltage of the secondary power supply is converted into the first voltage to serve as the standby voltage, and when the power supply of the main power supply is abnormal, the standby power supply supplies power to the target loop, so that the SSD can continue to work, and the reliability of the system is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flowchart illustrating steps of a method for powering an SSD according to an embodiment of the present invention;
FIG. 2 is a block diagram of a power supply system for an SSD in accordance with an embodiment of the present invention;
fig. 3 is a structural distribution diagram of a specific power supply system of an SSD according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a power supply method of an SSD, which is applied to the SSD conforming to NVMe standard, and is shown in figure 1, and comprises the following steps:
s1: when the main power supply is monitored to be normal, supplying power to a target loop through the main power supply;
s2: when the main power supply is monitored to be abnormal, the main power supply is disconnected, and power is supplied to the target loop through a standby power supply;
the standby power supply is obtained by combining an auxiliary power supply with a voltage conversion circuit;
the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage.
It will be appreciated that the voltage conversion circuit converts the second voltage of the secondary power supply to the first voltage of the backup power supply, the operating voltage of the target loop being the first voltage, so that the supply voltage can be switched between the primary and backup power supplies.
Further, the power supply method may further include:
s3: and when the main power supply and the auxiliary power supply are monitored to be abnormal, stopping supplying power to the target loop.
It is understood that stopping the power supply can prevent the SSD from being damaged due to the voltage abnormality.
Generally, the first voltage provided by the PCIe bus is 12V, and the second voltage is 3.3V; correspondingly, the voltage conversion circuit is a BOOST circuit, and the BOOST circuit may be a BOOST circuit.
The invention discloses a power supply method of an SSD, which is applied to the SSD meeting NVMe standard and comprises the following steps: when the main power supply is monitored to be normal, supplying power to a target loop through the main power supply; when the main power supply is monitored to be abnormal, the main power supply is disconnected, and power is supplied to the target loop through a standby power supply; the standby power supply is obtained by combining an auxiliary power supply with a voltage conversion circuit; the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage. According to the method, the second voltage of the secondary power supply is converted into the first voltage to serve as the standby voltage, and when the power supply of the main power supply is abnormal, the standby power supply supplies power to the target loop, so that the SSD can continue to work, and the reliability of the system is improved.
Correspondingly, the invention discloses a power supply system of an SSD, which is applied to an SSD conforming to NVMe standard, and as shown in fig. 2, the power supply system includes a main power supply 1, a backup power supply 2 obtained by combining a secondary power supply 21 and a voltage conversion circuit 22, a logic circuit 3, and a monitoring circuit 4, wherein the logic circuit 3 is configured to perform the following actions:
when the monitoring circuit 4 monitors that the main power supply 1 is normal, the main power supply 1 supplies power to the target loop 5;
when the monitoring circuit 4 monitors that the main power supply 1 is abnormal, the main power supply 1 is disconnected, and power is supplied to the target loop 5 through the standby power supply 2;
the voltage values of the main power supply 1 and the backup power supply 2 are both a first voltage, and the voltage value of the secondary power supply 21 is a second voltage.
Further, the logic circuit may be further configured to:
when the monitoring circuit monitors that the main power supply and the standby power supply are both abnormal, the power supply to the target loop 5 is stopped.
It can be understood that the system converts the second voltage of the secondary power supply into the first voltage as the standby voltage, when the power supply of the primary power supply is abnormal, the standby power supply supplies power to the target loop, so that the SSD can continue to work, and the reliability of the system is improved.
The embodiment of the invention discloses a specific SSD power supply system, and compared with the previous embodiment, the embodiment further describes and optimizes the technical scheme. Referring to FIG. 3:
generally, the main power supply and the secondary power supply are both provided by a PCIe bus, wherein the first voltage is 12V, and the second voltage is 3.3V;
accordingly, the voltage conversion circuit is a BOOST circuit, typically a BOOST circuit.
The logic circuit 3 specifically includes a first MOS transistor 31, a second MOS transistor 32, a first resistor 33, a second resistor 34, and a third resistor 35, wherein,
the drain electrode of the first MOS tube 31 is connected with the main power supply 1, the grid electrode of the first MOS tube 31 is connected with the first output end of the monitoring circuit 4, and the source electrode of the first MOS tube 31 is connected with the input end of the target loop;
the drain of the second MOS transistor 32 is connected to the standby power supply 2, the gate of the second MOS transistor 32 is connected to the second output end of the monitoring circuit 4, and the source of the second MOS transistor 32 is connected to the input end of the target circuit;
a first end of the first resistor 33 is connected with the main power supply 1, and a second end is connected with a first end of the second resistor 34;
the first end of the second resistor 34 is further connected to the first output end of the monitoring circuit 4, and the second end is grounded;
the third resistor 35 has a first terminal connected to the second output terminal of the monitoring circuit 4 and a second terminal connected to ground.
The logic circuit 3 formed by connecting the above components can complete the logic operation mentioned in the above embodiment. The MOS tubes in the logic circuit are all NMOS tubes. The specific principle is that the gate of the first MOS transistor 31 is controlled by the monitoring circuit 4, and the gate voltage is pulled up to +12V through the first resistor 33 and the second resistor 34, that is, the source and the drain of the first MOS transistor are defaulted to be on when the first output end of the monitoring circuit 4 has no output, and the main power supply 1 supplies power to the target loop 5; the gate of the second MOS transistor 32 is pulled down to the bottom through the third resistor 35, that is, when the second output terminal of the monitoring circuit 4 has no output, the source and the drain of the second MOS transistor are not turned on by default, and the standby power supply 2 does not supply power to the target loop 5.
Therefore, when the +12V main power supply 1 is normal, the gate of the first MOS transistor 31 is at a high level, the gate of the second MOS transistor 32 is at a low level, and the +12V main power supply 1 supplies power to the system; when the +12V main power supply 1 fails and the +12V standby power supply 2 is normal, the grid of the first MOS tube 31 is at a low level, the grid of the second MOS tube 32 is at a high level, and the standby power supply supplies power to the system; when the two power supplies are abnormal, the two MOS tube grids are both low levels, and the two power supplies are disconnected at the moment, so that damage to the SSD due to abnormal voltage is avoided.
Further, the logic circuit 3 may further include: a first diode 36 and a second diode 37, wherein:
the source of the first MOS transistor 31 is connected to the anode of the first diode 36;
the source of the second MOS transistor 32 is connected to the anode of the second diode 37;
the cathode of the first diode 36 and the cathode of the second diode 37 are both connected to the target input terminal.
It will be appreciated that the series diode is to prevent current back flow from damaging the power supply system.
Specifically, the target circuit 5 in the figure includes a plurality of DC-DC chips, and the 12V voltage of the main power supply 1 or the backup power supply 2 is converted into a voltage required by each module inside the SSD by the DC-DC chips, and then supplies power to the load in the target circuit.
Specifically, the monitoring circuit is a circuit powered by an independent power supply, generally, the power supply of the monitoring circuit is +3.3V _ AUX, and is provided by a PCIe bus, so that the monitoring circuit can normally operate when a main power supply and an auxiliary power supply fail.
Correspondingly, the invention also discloses an SSD, which comprises the power supply system of the SSD in any one of the embodiments.
For specific details of the SSD, reference may be made to the description of the power supply system of the SSD in the above embodiment.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The SSD power supply method and system provided by the present invention and the SSD are described in detail above, and a specific example is applied in the present disclosure to explain the principle and the embodiment of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (10)
1. A power supply method of an SSD is applied to the SSD conforming to NVMe standard, and comprises the following steps:
when the main power supply is monitored to be normal, supplying power to a target loop through the main power supply;
when the main power supply is monitored to be abnormal, the main power supply is disconnected, and power is supplied to the target loop through a standby power supply; the standby power supply is obtained by combining an auxiliary power supply with a voltage conversion circuit;
the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage.
2. The power supply method according to claim 1, further comprising:
and when the main power supply and the auxiliary power supply are monitored to be abnormal, stopping supplying power to the target loop.
3. The power supply method according to claim 1 or 2,
the first voltage is 12V, and the second voltage is 3.3V;
correspondingly, the voltage conversion circuit is a booster circuit.
4. A power supply system of an SSD is applied to the SSD conforming to NVMe standard, and comprises a main power supply, a standby power supply obtained by combining a secondary power supply and a voltage conversion circuit, a logic circuit and a monitoring circuit, wherein the logic circuit is used for executing the following actions:
when the monitoring circuit monitors that the main power supply is normal, the main power supply supplies power to a target loop;
when the monitoring circuit monitors that the main power supply is abnormal, the main power supply is disconnected, and the standby power supply supplies power to the target loop;
the voltage values of the main power supply and the standby power supply are both first voltages, and the voltage value of the secondary power supply is a second voltage.
5. The power supply system of claim 4, wherein the logic circuit is further configured to:
and when the monitoring circuit monitors that the main power supply and the standby power supply are abnormal, stopping supplying power to the target loop.
6. The power supply system according to claim 5,
the first voltage is 12V, and the second voltage is 3.3V;
correspondingly, the voltage conversion circuit is a booster circuit.
7. The power supply system according to claim 6, wherein the logic circuit specifically comprises a first MOS transistor, a second MOS transistor, a first resistor, a second resistor, and a third resistor; wherein,
the drain electrode of the first MOS tube is connected with the main power supply, the grid electrode of the first MOS tube is connected with the first output end of the monitoring circuit, and the source electrode of the first MOS tube is connected with the input end of the target loop;
the drain electrode of the second MOS tube is connected with the standby power supply, the grid electrode of the second MOS tube is connected with the second output end of the monitoring loop, and the source electrode of the second MOS tube is connected with the input end of the target loop;
the first end of the first resistor is connected with the main power supply, and the second end of the first resistor is connected with the first end of the second resistor;
the first end of the second resistor is also connected with the first output end of the monitoring circuit, and the second end of the second resistor is grounded;
and the first end of the third resistor is connected with the second output end of the monitoring circuit, and the second end of the third resistor is grounded.
8. The power supply system of claim 7, wherein the logic circuit further comprises: a first diode and a second diode, wherein:
the source electrode of the first MOS tube is connected with the anode of the first diode;
the source electrode of the second MOS tube is connected with the anode of the second diode;
and the cathode of the first diode and the cathode of the second diode are both connected with the target input end.
9. The power supply system of any one of claims 4 to 8, wherein the monitoring circuit is a circuit powered by an independent power source.
10. An SSD, characterized by comprising a power supply system of an SSD according to any of claims 4 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711091493.4A CN107731260B (en) | 2017-11-08 | 2017-11-08 | SSD power supply method and system and SSD |
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| CN201711091493.4A CN107731260B (en) | 2017-11-08 | 2017-11-08 | SSD power supply method and system and SSD |
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| CN107731260B (en) | 2020-11-20 |
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