CN1570794A - Numerical control system for machine tool - Google Patents

Numerical control system for machine tool Download PDF

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Publication number
CN1570794A
CN1570794A CN 200410009095 CN200410009095A CN1570794A CN 1570794 A CN1570794 A CN 1570794A CN 200410009095 CN200410009095 CN 200410009095 CN 200410009095 A CN200410009095 A CN 200410009095A CN 1570794 A CN1570794 A CN 1570794A
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China
Prior art keywords
storer
control
signal
circuit
fpga
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CN 200410009095
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Chinese (zh)
Inventor
王田苗
陈友东
魏洪兴
孙恺
刘淼
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北京博创兴工科技有限公司
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Priority to CN 200410009095 priority Critical patent/CN1570794A/en
Publication of CN1570794A publication Critical patent/CN1570794A/en

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Abstract

This invention discloses a system for digital control of machine, which comprises executive program and hardware circuit, wherein, executive program comprises uC/OS real time operation system and digital control application program based on it; hardware circuit processor responds to the user operations from control panel and performs corresponding digital process. The processing information is transmitted down to FPGA by processor and is converted into analogue signals through DA which is outputted to main-shaft motor of driving circuit control machine of frequency converter. The logic information from processor is outputted to IO interface after being isolated and converted by FPGA. IO interface receives machine signals and feed them back to FPGA after isolation and conversion and is transmitted to processor by FPGA.

Description

The digital control system of lathe

Technical field

The present invention relates to a kind of control system that numerically-controlled machine is controlled, specifically, be meant a kind of digital control system based on arm processor and uC/OS real time operating system.

Background technology

In recent years, the control system of most of numerically-controlled machine adopts chip microcontroller control, but the control circuit structure of single-chip microcomputer is complicated, realize that if desired high performance digital control system need adopt a plurality of (piece) single-chip microcomputer, a plurality of (piece) single machine combination is used reliability, the stability that has reduced system, has increased cost; And the function that system realizes is fairly simple, and interactive capability is poor, and control accuracy is low, thereby has caused the efficiency ratio of work lower; In addition,, limited the further transformation of control system, be not easy to secondary development and use owing to adopt single-chip microcomputer to control.

Summary of the invention

Deficiency based on existing machine tool control system, the invention discloses a kind of control mode that combines based on arm processor and uC/OS real time operating system and control the digital control system of lathe, this digital control system utilization arm processor and FPGA, and the advantage of uC/OS real time operating system, realize a kind of have high integration degree and cost performance, simple in structure, can realize satisfying the numerically-controlled machine control system that can develop use once more of intelligent requirements with comparatively economic array mode.

Machine tool numerical control system of the present invention, the control mode that employing combines based on arm processor and uC/OS real time operating system, digital control system comprises can be for program and the hardware circuit carried out, executive routine comprises uC/OS real time operating system, application program, and hardware circuit comprises arm processor, FPGA, storer, DA converter, driving circuit, IO interface circuit, isolates change-over circuit and system power supply circuit.LCD display connects with arm processor, control panel connects with FPGA, numerical control program based on uC/OS operating system moves on the arm processor platform, the digital control system response is from user's operation of control panel, carry out corresponding digital control processing process, machining information reaches FPGA and DA conversion down after arm processor is handled.Simulating signal after the DA conversion exports the driving circuit of frequency converter to, the spindle motor of control lathe; The servo drive signal that FPGA realizes exports the servo-drive system of lathe to after isolating conversion, the motion of control lathe; Logical message after ARM handles exports the IO interface to after FPGA, isolation conversion, described IO interface is accepted the lathe signal and its signal is fed back to FPGA after being isolated conversion, transfers to ARM after FPGA handles.

Compare with prior art, advantage of the present invention is: (1) has adopted the arm processor that has high speed performance and enrich interface resource, has the integrated level height, the circuit structure characteristic of simple; (2) while has been set up a real time operating system that suitable numerically-controlled machine uses on the disclosed real time operating system μ C/OS of source code basis, has improved the performance and the real time response speed of system, and working stability is reliable; (3) this numerical control system is fit to Subscriber Unit to carrying out new function development, expansion in the product processing, the various needs when making to satisfy new product; (4) this numerical control system kernel is little, real-time, reliable and stable; (5) cheap, simple to operate, many-sided characteristics such as economic and practical.

Description of drawings

Fig. 1 is the functional block diagram of hardware circuit of the present invention.

Fig. 2 is the block diagram that digital control system function of the present invention realizes.

Fig. 3 (a) is the circuit diagram of arm processor of the present invention.

Fig. 3 (b) is the memory expansion circuit of arm processor of the present invention.

Fig. 3 (c) is the change-over circuit of arm processor output signal of the present invention.

Fig. 4 (a) is a FPGA circuit diagram of the present invention.

Fig. 4 (b) is the isolation change-over circuit of FPGA output signal of the present invention.

Fig. 5 is a system power supply circuit of the present invention.

Fig. 6 (a) is that IO interface of the present invention receives the message part circuit.

Fig. 6 (b) is an IO interface output information partial circuit of the present invention.

Fig. 7 is a drive motor circuit diagram of the present invention.

Embodiment

The present invention is done to carry out the detailed description in a step below in conjunction with accompanying drawing.

The present invention is based on a kind of numerical control device that numerically-controlled machine is controlled of arm processor and uC/OS real time operating system, introduces embedded system technology in the present invention, develops a kind of high performance computer numerical control (CNC) system for lathe.Realize the software frame of digital control system, and finish the function of digital control system.

Computerized digital control system is a kind of position control system, and its essence is to go out desirable movement locus according to the data segment interpolation of importing, and outputs to execution unit then, processes the part that needs.Therefore, input, track interpolation, servocontrol become three essential parts (being input-decision-making-three aspects of output of general computer control system) of Computerized digital control system, and all these work are reasonably organized by the system program in computing machine, make that total system is ruly carries out work.

The control system of numerically-controlled machine of the present invention, adopt the control of the real time operating system realization lathe of arm processor and uC/OS, the software platform of its executive routine adopts the uC/OS real time operating system, the operation of executive routine operation response panel, select different modes of operation, carry out corresponding action.Control the motion of lathe in each stage of the corresponding run time version compiling of runtime system automatically, cutter compensation, speed calculation, interpolation, position servo; Arm processor in its control device connects the LCD of lathe, FPGA connects the guidance panel of lathe, numerical control program based on uC/OS operating system moves on arm processor, the digital control system response is from user's operation of control panel keyboard, carry out corresponding digital control processing process, machining information reaches FPGA and DA modular converter down after arm processor is handled.FPGA realizes generation and counting, the scanning of keyboard and the control of IO of pulse signal, and the control signal that produces is transferred to the servomotor of lathe through isolation and change-over circuit; Wherein the DA conversion produces the needed simulating signal of frequency converter, is driven the spindle motor of lathe by frequency converter.(seeing also shown in Figure 1)

In the present invention according to required function of finishing of control system and demand, executive routine has been set six tasks, be man-machine interface, data processing, motion control, logic control, auxiliary control and servocontrol, each task can be divided into littler submodule again.(seeing also shown in Figure 2)

(1) man-machine interface: manage and finish mutual between digital control system and the operator

The operator can be provided with the related parameter that has in the process by " man-machine interface " input processing object, the parameter of cutter is set, and can passes through the processed file of " man-machine interface " managed storage in digital control system." man-machine interface " can also provide the system diagnostics function, finds the possible problem of data system, and offers help for operating process.

(2) logical process: i.e. PLC function, mainly finish operation and simple logical operation that IO is ordered.

(3) motion control: motion control makes lathe according to the instruction of appointment or the motion of parts information generation appointment, and it mainly coordinates each motion, for servo processing provides accurate position command.

(4) auxiliary control: finish main shaft management, tool magazine management, fault diagnosis, network control etc.

(5) data processing: compiling and the cutter compensation function of finishing G code.

(6) servo processing: servo processing is each all necessary methods of axle (refer to lathe each) execution movement instruction in given restriction range, and servocontrol generally is divided into open loop and closed-loop control, and dual mode of the present invention all can.

In the present invention, select the control of different mode of operation realizations according to control panel to lathe.Digital control system is a hardware circuit, and it is installed in the demonstration of lathe and the back of key board unit.Hardware circuit includes: arm processor, FPGA, internal memory expanded circuit, DA converter, driving circuit, IO interface circuit, isolation change-over circuit, system power supply circuit.(seeing also shown in Fig. 3~7)

(1) arm processor

Comprise S3C44BOX type embedded type CPU, clock, reset circuit, jtag interface and real-time clock-RTC (Real Time Counter) circuit, memory interface, lcd controller, asynchronous serial port, synchronous serial interface, universal I interface etc.

What clock adopted is the 6MHz external crystal, utilizes the PLL module in the ARM sheet, the travelling speed of CPU can be brought up to 66MHz.66,65, the 64 termination clock circuits of arm processor UN2001, reset circuit does not use common rc reset, but the special chip UN2002 IMP811T that resets that adopts, this chip has monitoring voltage and hand-reset input function, when system power supply circuit supply voltage less than 3.08V time output reset signal, 2 ends of the 50 termination reset circuit UN2002 of arm processor UN2001, the 3 termination reset switches of reset circuit UN2002, the power supply of 4 termination 3.3V.

(2)FPGA

In order to preserve after the unexpected power down to the losing of data among the FPGA, specially FPGA has been disposed storer, storer E uses ByteBlasterMV to download line to carry out programming, and FPGA is carried out Configuration Online and configuring chip UN3000 is configured FPGA.What wherein ByteBlasterMV downloaded that line carries out programming and FPGA is carried out that Configuration Online uses configuring chip UN3000 is serial JTAG chain, FPGA is configured and can controls configuring chip UN3000 and FPGA simultaneously under the situation that does not change hardware, also can after programming configuring chip UN3000, when powering on, dispose FPGA, greatly facilitate debugging and use by configuring chip UN3000.

What configuring chip used is the EPC2LC20 chip, and this chip is actually serial FLASH, carries out programming by jtag interface.

FPGA uses the external bus of arm processor to communicate, and the signal of the arm processor that need use has: 16 data lines, 8 address wires, reading and writing, sheets select, interrupt.So always have the addressing space of 512 bytes.16 data lines 19 of FPGA UN3001,24-31,36-41,44 ends are connected with 16 data line D0~D15 of arm processor UN2001, article 8, address wire 18,45-47,53-56 end are connected with A0~A7 of arm processor UN2001,17 ends of FPGA UN3001 are connected the look-at-me to arm processor as FPGA with 33 ends of arm processor UN2001,182,80,184,78 ends of FPGA UN3001 are connected with 50,23,15,16 ends of arm processor UN2001 as FPGA the resetting of arm processor, sheet choosing, reading and writing control signal.

(3) storer

Storer A NOR FLASH adopts Am29LV160B, 2MByte, be used to store start-up code, this code is finished the initialization to arm processor, storer B then will based on the digital control system executive routine of uC/OS real time operating system from self-replication to storer C.

Storer B NAND FLASH adopts K9F2808U, 16MByte, and storage is based on the digital control system executive routine of uC/OS real time operating system, and numerical control file.

Storer C SDRAM adopts HY57V561620,32MByte, and as the system dynamics internal memory, program when being used for storage running and constant.

Storer D NVRAM adopts DS1230W, and the 16K byte is used to store the running state parameter of lathe, lost data when preventing unexpected power down.

Wherein, 16 of arm processor data line D0~D15 connect the data line end of storer A and storer C; 8 data line D0~D7 of arm processor connect the data line end of storer B and storer D; The address wire A0 of arm processor~A19 connects A0~A19 end of storer A; The address wire A0 of arm processor~A12 connects A0~A12 end of storer B; The address wire A0 of arm processor~A13 connects A0~A13 end of storer D.

(4) DA conversion

The DA converter adopts AD7243, and this is a 12 bit serial DA converters, has multiple voltage output area and multiple mode of operation.

In order to improve the impedance behavior of simulation output, need to use operational amplifier to handle.Because the output of DA converter is 0~10V voltage, adopt the emitter follower circuit.Amplifier is used the MC4558 chip.(shown in Fig. 3 (c))

(5) Signal Spacing and conversion

Used the ULN2803 chip as driving, the ULN2803 chip is a unit 8 Darlington transistor driver, and the electric current of 1A can be provided.Because FPGA before configuration and the problem of drawing on the pin in the configuration, draws in the input of TLP521 chip, export drop-downly, the input of ULN2803 chip is a low level like this, so his output shows as shutoff, can prevent the misoperation of relay.When realizing the differential to single-ended conversion of signals, on the right positive signal of input signal, to add one 110 ohm resistance, on negative level signal, add one 560 ohm resistance.The recognition capability of signal is improved.(shown in Fig. 4 (b))

(6) system power supply

Power module that can selector has two kinds of linear voltage regulator and switch power modules.The characteristics of linear voltage regulator are that output quality is good, and external circuit is simple, but when the input and output voltage difference was big, output power can be subjected to very big influence.And that the switch power module output power is influenced by the input and output voltage difference is less, but poor quality some, external circuit is more complicated also.

Therefore, use linear voltage regulator to realize the conversion of 5V~3.3V and 5V~2.5V in the present invention, use switch power module to realize the conversion of 24V~5V.It uses the LM1085 chip linear voltage stabilization, and the output current of 1A can be provided.That switch power module uses is LM2575-5, and efficient can reach 80%.(as shown in the figure)

(7) communication interface

What use as the RS232 level conversion of communication interface is UN2000 MAX3232 chip, 11 ends of the 100 termination UN2000 MAX3232 of its arm processor UN2001 S3C44BOX, 104 terminations, 10 ends, 99 terminations, 12 ends, 103 terminations, 9 ends, the level of the compatible 3V~5.5V of this communication interface directly is connected with the arm processor UN2001 of 3.3V.

List the annexation of concrete pin below, but this annexation is not used for limiting the scope that claim of the present invention limits.

It is the chip of S3C44BOX that microprocessor chip of the present invention adopts the model based on the ARM7TDMI kernel.The 119-124 of ARM microprocessor UN2001, the corresponding 45-29 end that is connected to storer AUN4000 of 127-136 end, data-signal as storer A, 1-3,143-151, the corresponding 23-25 that is connected to storer A UN4000 of 153-160 end, 9,16,17,48, the 1-5 end, address signal as storer A, 17,16,15,50 end correspondences are connected to 26 of UN4000,11,28,12 ends, respectively as the chip selection signal of storer A, read-write and reset signal, 119-124, the 127-136 end also is connected to 53 of storer C UN4001 through 10 Ohmages, 51,50,48,47,45,44,42,13,11,10,8,7,5,4,2 ends, data-signal as storer B, 1-3,150,151, the 153-160 end is connected to the 25-23 of storer C UN4001 through 22 Ohmages, 36,35,22, the 34-26 end, address signal as storer C, 7,8,11,12,16,25,27,28 end correspondences are connected to 17 of storer C UN4001,18,15,39,16,19,37,38 ends, control signal as storer C, the 129-136 end is connected to the 44-41 of storer B UN4003, the 32-29 end, data-signal as storer B, corresponding 7 of the storer B UN4003 that is connected to of 115-118 end, 17,16,9 ends, control signal as storer B, 119-124, the corresponding 19-11 end that is connected to storer DUN4004 of 127-136 end, data-signal as storer D, 1-3,148-151, the 153-160 end is also connected to the 8-10 of storer D UN4004,1,26,2,23,21,24,25, the 3-7 end, as the address signal of storer D, 11,15,20 correspondences are connected to 27 of storer D UN4004,22,20 ends.

56,58, the 59 end correspondences of UN2001 are connected to 3,2,4 ends of DA converter UN5000, as clock, synchronous, data-signal.

The 129-136 data-signal end and 15,16,19,32 of UN2001,50 control signal ends can be used as communication interface.

The 1-3 of UN2001,156-160, corresponding 55-53,61,60,58-56,88-85,83,75-73,71-67, the 65-63 end that is connected to FPGAUN3001 of 119-124,127-136 end, as input/output signal, 15,16,23,50 end correspondences are connected to 184,78,80,182 ends of FPGA UN3001, as control signal.

50 of UN2001,60,61,69,70 end correspondences are connected to the 4-8 end of PT2003, the 91-94 end is the 9-12 end of the corresponding LCD of connection of control signal interface PT2003,95-98, the 111-114 end is the 14-17 of the corresponding LCD of connection of data-signal interface PT2003, the 22-25 end, 99,100,103,104 ends are that the two-way serial port correspondence of system connects 12 of UN2000,11,9,10 ends, the 42-46 end is connected to 3 of PT2005 after jtag circuit is handled, 9,7,5,11 ends, the corresponding 2-9 end that connects PT2002 of 75-82 end, 51 ends join with power supply with 10k resistance series connection back, the 52-54 end is by the 10K resistance eutral grounding of series connection crystal oscillator mode selection circuit, 64,65 ends connect external crystal oscillation circuit, the corresponding external clock interface that connects of 66 ends, the outside RTC interface of the corresponding connection of 87-89 end, 83-85 holds with ground connection after the 10Nf capacitances in series.

9,47,67,125 ends of UN2001 are that system power supply connects 3.3V, and 21,34,62,86,109,138 ends are that system power supply connects 2.5V, 10,22,35,48,63,73,74,90,110,126,139,152 end ground connection, and all the other terminals are unsettled.

Described ARM microprocessor is 32 nuclears of low-power consumption, has abundant interface resource, a series of complete general peripheral components (USB interface have been expanded, RS-232 interface, the JTAG debug port, and keyboard interface and LCD interface), it is minimum that system cost is reduced to, and eliminated the needs that increase additional configurations; In addition, the ARM microprocessor extensions a large amount of internal memory and 16M hard-disc storage spaces, accelerated the speed of CPU Processing tasks, help the real-time control of system.

153,4,1,50 ends of FPGA UN3001 are connected with 1,3,5,9 ends of PT3000 with 11,1,3,19 ends of UN3000, form JTAG and download chain, can realize to the programming of UN3001 with to the configuration of UN3001 by the download line PC of this circuit and FPGA.52,105,155,2,156 ends of UN3001 and 8,13,4,9,2 ends of UN3000 connect to form the configuration circuit of UN3000 to UN3001, and UN3000 when system powers on can be configured UN3001 automatically by this circuit.153 of UN3001,183 ends of UN3001 are connected the clock input as UN3001 with 4 ends of JP3001, the 7-16 of UN3001,198-200, the 202-208 end is connected the scan control signal as the control panel upper keyboard with the 31-50 of control panel PT6000,57 of UN3001,58,60,61,63-65,67-71,73-75,83 ends are connected as the output control signal with the 2-9 end of UN10001 and UN10003,122 of UN3001,125,134-136,139-144,147-150,157 are connected the conduct expansion with the 11-18 of PT12043 and PT12044 exports control signal, the 85-89 of UN3001,90,92-97,99,100,111 ends are connected as input signal with the 2-9 end of UN9000 and UN9002, the 101-103 of UN3001,112, the 6-9 of 113 ends and UN8009,2,3 ends connect the input signal as spindle encoder and handwheel scrambler, the 114-116 of UN3001, the 119-127 end is connected as the control signal to motor driver, the 126-128 of UN3001 with the 2-7 end of UN7001, the 131-133 end is connected as the position command signal to motor driver with the 2-7 end of UN7000.

Claims (7)

1, a kind of digital control system of lathe comprises executive routine, the hardware circuit of digital control system at least, and display and control panel, it is characterized in that:
Described executive routine includes the uC/OS real-time oss unifies based on the numerical control application program of uC/OS real time operating system, and its uC/OS real time operating system is responsible for the scheduling and the management of system; Its numerical control application program based on the uC/OS real time operating system is responsible for carrying out digital control system; The I/O instruction manipulation of executive routine response control panel;
Described hardware circuit includes: an arm processor, information, the operation of data of responsible digital control system;
One memory expansion circuit, the program and the data of being responsible for storing above-mentioned arm processor, wherein,
Store the system initialization start-up code among the storer A,
Store digital control system executive routine and the required numerical control program of machine tooling among the storer B based on the uC/OS real time operating system,
Be Dram among the storer C, program and data when storing system's operation,
Store the state parameter of lathe operation and lathe, cutter parameters among the storer D;
One FPGA, responsible positional information with above-mentioned arm processor output exports the servo-drive system of machine motor to, the motion of control lathe; The logical message of its output is controlled the IO interface;
One storer E is responsible for the data of above-mentioned FPGA after power down and preserves;
One D/A converter is responsible for converting the numerical information of above-mentioned arm processor output to analog information;
One drive circuit is responsible for exporting the information of above-mentioned D/A conversion to the lathe frequency converter;
One IO interface circuit, the UNICOM of responsible lathe and digital control system;
One isolates change-over circuit, is responsible for the information of above-mentioned FPGA, IO interface is isolated, changed;
One system power supply circuit is responsible for providing control system and relay required power supply;
Digital control system adopts the control mode that combines based on arm processor and uC/OS real time operating system;
LCD display connects with arm processor, and control panel connects with FPGA, and the machine tool chief axis frequency converter connects with driving circuit, and machine motor connects with isolating change-over circuit;
The digital control system executive routine based on the uC/OS real time operating system among the storer C moves on the arm processor platform, and the arm processor response is carried out corresponding digital control processing process from user's operational order of control panel; Part processing information reaches FPGA and DA modular converter down after ARM handles; Simulating signal after the DA conversion exports the driving circuit of frequency converter to, the spindle motor of control lathe; The servo drive signal that FPGA realizes exports the servo-drive system of lathe to after isolating conversion, the motion of control lathe; Logical message after ARM handles exports the IO interface to after FPGA, isolation conversion, described IO interface is accepted the lathe signal and its signal is fed back to FPGA and ARM after being isolated conversion.
2, machine tool numerical control system according to claim 1 is characterized in that:
Described arm processor can be selected ARM7 series or ARM9 family chip for use;
Described storer A can select FLASH, ROM storer for use;
Storer B can select FLASH, ROM storer for use;
Storer C can select SRAM, SDRAM, DRAM, NVRAM, FRAM storer for use;
Storer D can select FLASH, ROM storer for use;
Storer E can select FLASH, ROM storer for use;
Described FPGA can select ACEX family chip, FLEX family chip, CYCLONE family chip, APEX family chip, STRATIX family chip for use;
3, machine tool numerical control system according to claim 1 is characterized in that: be provided with communication interface circuit.
4, machine tool numerical control system according to claim 3 is characterized in that: communication interface is the RS232 standard data communications.
5, machine tool numerical control system according to claim 1 is characterized in that:
Described arm processor UN2001 selects the S3C44B0X chip for use;
Described storer A UN4000 selects the AM29LV160 chip for use,
Storer B UN4003 selects the K9F2808 chip for use,
Storer C UN4001 selects the HY57V561620 chip for use,
Storer D UN4004 selects the DS1230 chip for use,
Storer E UN3000 selects the EPC2LC20 chip for use;
Described FPGA UN3001 selects the EP1K-QFP208-3 chip for use;
Described DA converter UN5004 selects the AD7243 chip for use, its output valve 0~10V;
Described driving circuit UN5000 selects the 74HC245 chip for use;
Described isolation change-over circuit UN8009 selects the 74HC245 chip for use;
Described IO interface circuit is selected 4 74HC245 chips for use;
Described system power supply circuit is selected 2 LM1085 chips and 1 LM2575 chip for use, be respectively applied for produce 24V, ± 12V, 5V voltage;
Wherein, the 119-124 of ARM microprocessor UN2001, the corresponding 45-29 end that is connected to storer AUN4000 of 127-136 end, data-signal as storer A, 1-3,143-151, the corresponding 23-25 that is connected to storer A UN4000 of 153-160 end, 9,16,17,48, the 1-5 end, address signal as storer A, 17,16,15,50 end correspondences are connected to 26 of UN4000,11,28,12 ends, respectively as the chip selection signal of storer A, read-write and reset signal, 119-124, the 127-136 end also is connected to 53 of storer C UN4001 through 10 Ohmages, 51,50,48,47,45,44,42,13,11,10,8,7,5,4,2 ends, data-signal as storer B, 1-3,150,151, the 153-160 end is connected to the 25-23 of storer C UN4001 through 22 Ohmages, 36,35,22, the 34-26 end, address signal as storer C, 7,8,11,12,16,25,27,28 end correspondences are connected to 17 of storer C UN4001,18,15,39,16,19,37,38 ends, control signal as storer C, the 129-136 end is connected to the 44-41 of storer B UN4003, the 32-29 end, data-signal as storer B, corresponding 7 of the storer B UN4003 that is connected to of 115-118 end, 17,16,9 ends, control signal as storer B, 119-124, the corresponding 19-11 end that is connected to storer DUN4004 of 127-136 end, data-signal as storer D, 1-3,148-151, the 153-160 end is also connected to the 8-10 of storer D UN4004,1,26,2,23,21,24,25, the 3-7 end, as the address signal of storer D, 11,15,20 correspondences are connected to 27 of storer D UN4004,22,20 ends;
56,58, the 59 end correspondences of UN2001 are connected to 3,2,4 ends of DA converter UN5000, as clock, synchronous, data-signal;
The 129-136 data-signal end and 15,16,19,32 of UN2001,50 control signal ends can be used as communication interface;
The 1-3 of UN2001,156-160, corresponding 55-53,61,60,58-56,88-85,83,75-73,71-67, the 65-63 end that is connected to FPGAUN3001 of 119-124,127-136 end, as input/output signal, 15,16,23,50 end correspondences are connected to 184,78,80,182 ends of FPGA UN3001, as control signal;
50 of UN2001,60,61,69,70 end correspondences are connected to the 4-8 end of PT2003, the 91-94 end is the 9-12 end of the corresponding LCD of connection of control signal interface PT2003,95-98, the 111-114 end is the 14-17 of the corresponding LCD of connection of data-signal interface PT2003, the 22-25 end, 99,100,103,104 ends are that the two-way serial port correspondence of system connects 12 of UN2000,11,9,10 ends, the 42-46 end is connected to 3 of PT2005 after jtag circuit is handled, 9,7,5,11 ends, the corresponding 2-9 end that connects PT2002 of 75-82 end, 51 ends join with power supply with 10k resistance series connection back, the 52-54 end is by the 10K resistance eutral grounding of series connection crystal oscillator mode selection circuit, 64,65 ends connect external crystal oscillation circuit, the corresponding external clock interface that connects of 66 ends, the outside RTC interface of the corresponding connection of 87-89 end, 83-85 holds with ground connection after the 10Nf capacitances in series;
9,47,67,125 ends of UN2001 are that system power supply connects 3.3V, and 21,34,62,86,109,138 ends are that system power supply connects 2.5V, 10,22,35,48,63,73,74,90,110,126,139,152 end ground connection;
153,4,1,50 ends of FPGA UN3001 are connected with 1,3,5,9 ends of PT3000 with 11,1,3,19 ends of UN3000, form JTAG and download chain, can realize to the programming of UN3001 with to the configuration of UN3001 by the download line PC of this circuit and FPGA.52,105,155,2,156 ends of UN3001 and 8,13,4,9,2 ends of UN3000 connect to form the configuration circuit of UN3000 to UN3001, and UN3000 when system powers on can be configured UN3001 automatically by this circuit; 153 of UN3001,183 ends of UN3001 are connected the clock input as UN3001 with 4 ends of JP3001, the 7-16 of UN3001,198-200, the 202-208 end is connected the scan control signal as the control panel upper keyboard with the 31-50 of control panel PT6000,57 of UN3001,58,60,61,63-65,67-71,73-75,83 ends are connected as the output control signal with the 2-9 end of UN10001 and UN10003,122 of UN3001,125,134-136,139-144,147-150,157 are connected the conduct expansion with the 11-18 of PT12043 and PT120441 exports control signal, the 85-89 of UN3001,90,92-97,99,100,111 ends are connected as input signal with the 2-9 end of UN9000 and UN9002, the 101-103 of UN3001,112, the 6-9 of 113 ends and UN8009,2,3 ends connect the input signal as spindle encoder and handwheel scrambler, the 114-116 of UN3001, the 119-127 end is connected as the control signal to motor driver, the 126-128 of UN3001 with the 2-7 end of UN7001, the 131-133 end is connected as the position command letter to motor driver with the 2-7 end of UN7000.
6, machine tool numerical control system according to claim 5 is characterized in that: linear interpolation precision:<0.0003mm; Circular interpolation precision:<0.0005mm; Cutting speed of feed error (with setting value):<± 3%; Fast moving velocity error (with setting value):<± 10%; G04 time delay command error:<5ms; Acceleration, deceleration time constant error:<5ms; (with the time is set) trueness error:<5ms of various duration of pulse of system.
7, according to claim 1,5 described machine tool numerical control systems, it is characterized in that: applicable to lathe, milling machine and machining center.
CN 200410009095 2004-05-14 2004-05-14 Numerical control system for machine tool CN1570794A (en)

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