CN100409558C - DC motor controller based on FPGA - Google Patents
DC motor controller based on FPGA Download PDFInfo
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- CN100409558C CN100409558C CNB2006100415518A CN200610041551A CN100409558C CN 100409558 C CN100409558 C CN 100409558C CN B2006100415518 A CNB2006100415518 A CN B2006100415518A CN 200610041551 A CN200610041551 A CN 200610041551A CN 100409558 C CN100409558 C CN 100409558C
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Abstract
This invention relates to one direct current motor control, which uses FPGA as center to integrate motor drive wave, loop control computation, upper communication function to use ROM self programming by upper machine direct motor controller.
Description
Technical field:
The present invention relates to a kind of DC motor controller based on on-site programmable gate array FPGA, particularly a kind of drive three-phase direct-current brushless motor and brush direct current motor, be the DC motor controller able to programme of core and embedded micro controller unit and UART Universal Asynchronous Receiver Transmitter UART interface logic with FPGA.
Background technology:
The electric machine controller of extensive use at present is based on the MCU/DSP design mostly, because disposed the special instruction, interface and the peripheral hardware that are used for Electric Machine Control among some MCU and the DSP, it is comparatively convenient to use, and still, still needs a large amount of peripheral logical circuits to expand its hardware capability in actual applications.The characteristics that the Single Chip Microcomputer (SCM) program serial is carried out have determined the real-time that will have influence on computing that increases of software function.In some special applications, for example, at high temperature, low temperature, strong electromagnetic or have in the space environment of radioactive particle radiation, MCU and DSP just can't operate as normal.And FPGA has the following advantages, and can satisfy the needs of above-mentioned application scenario.(1) FPGA can integrated to greatest extent peripheral logic, realizes the singualtion design, improves the global reliability of system; (2) FPGA can adopt and independently customize arithmetic logic, and the real-time of computing is good; (3) FPGA can adopt hardware sequencer and redundancy logic design easily, to improve interference free performance; (4) the existing chip from bussiness class to space flight level different stage of FPGA, the environment scope of application is extensive.
For this reason, some researchers are applied to FPGA in the Electric Machine Control both at home and abroad, developed can practical application device.
The multidimensional position control system (" ModularMulti-Axis Motion Control And Driving System And Method Thereof " that Hong Kong Dynacity company adopts DSP and FPGA to form, US0100723,11 May2006) in, DSP finishes electric current, the two closed loop control algorithms in position and host computer communication function, FPGA can produce the PWM drive signal according to DSP given pwm value and motor Hall feedback signal.Adopt bus to be connected between FPGA and the DSP, adopt single DSP, many FPGA structure to finish the control of a plurality of motors.Because still realize control algolithm by DSP, the real-time of control will be subjected to the influence of controlled number of motors.
The automation controller (" ROBOTCONTROL DEVICE " that Japan SANYO (Sanyo) company adopts MCU and FPGA to form, JP2001322078,2001-11-20) finish closed loop control algorithm by FPGA, MCU is used for the Configuration Online of host computer communication and FPGA.This system adopts single MCU, many FPGA structure to finish the control of a plurality of motors, has avoided the problem of said system control real-time aspect.But FPGA only realizes control algolithm, and the generation of drive signal still needs other chip to finish, and system configuration complexity and dependence MCU finish host computer communication.
The servo controller (" SERVO CONTROLLER " that Japan TOSHIBA (Toshiba) company adopts MPU (microprocessor) and FPGA to form, JP2000330641,2000-11-30) finish controlled function by MPU, realize the communication Protocol Conversion of position transducer by FPGA, utilize the FPGA reprovision to be set to different serial communication protocol logics, make this controller can adapt to the position transducer of multiple serial communication neatly.The use of FPGA has reduced a large amount of peripheral hardwares of system and has had certain upgradability, and still, the control of system is actual to be to be realized by MPU.
Summary of the invention:
The deficiency that the present invention has avoided said system to exist, providing a kind of is core with FPGA, integrates the generation of motor-driven waveform, closed-loop control computing, host computer communication function in one, but the DC motor controller based on FPGA of online programming.
The characteristics of the technical scheme that technical solution problem of the present invention is adopted are:
The present invention is based on the DC motor controller of on-site programmable gate array FPGA, form by fpga chip, FPGA configuring chip, ADC modulus conversion chip, power module and power amplifier module;
Described electric machine controller utilizes fpga chip that the motor Hall feedback signal of input is decoded, and obtains motor rotor position to drive the three-phase direct-current brushless motor; Or the fpga chip Hall feedback input end predetermined level that is set to fix, to drive brush direct current motor; Electric machine controller is caught the two pulse signals of motor photoelectric code disk by fpga chip, and relatively the two phase place draws the direction of rotation of rotor, and pulse count obtains motor speed; Electric machine controller utilizes fpga chip control ADC modulus conversion chip that the armature supply of motor is carried out the constant cycle sampling;
Driver module, control module and communication module are set respectively in described fpga chip; To velocity setting and speed feedback comparison and computing, draw drive signal pulsewidth set-point by control module; Driver module produces the PWM drive signal that has Dead Time able to programme accordingly according to described pulsewidth set-point and motor rotor position feedback signal, exports power amplifier module to by fpga chip, and drive motors constitutes the closed-loop speed control system; Described communication module comprises an embedded MCU (micro controller unit) that contains UART (UART Universal Asynchronous Receiver Transmitter) interface at least, by the user register in the described MCU management fpga chip, and communicates by letter with host computer by the UART interface; After fpga chip is finished configuration, by described MCU fpga chip is carried out the initialization of internal user register, and send handshake to host computer by described UART interface; Host computer (all-purpose computer or single-chip microcomputer) is communicated by letter with described MCU by the UART interface, and reads and writes the user register in the fpga chip in real time, realizes the Long-distance Control to motor.
The characteristics that the present invention is based on the DC motor controller of FPGA also are:
The embedded MCU of fpga chip adopts instruction fetch-instruction decoding-instruction to carry out three class pipeline and 8 bit instruction buses; Wherein high 4 of the instruction of MCU register write operation is command code, low 4 is several immediately, host computer sends described register write operation instruction by the UART interface MCU register is carried out write operation, and verifies the correctness that instruction is carried out by the numerical value that reads register; It is that command code, low 4 are check codes that all the other command formats are high 4, and the instruction that check code and check errors arranged is got by MCU and referred to that the unit replaces with non-operation instruction.
MCU uses inner distributed memory (Distributed RAM) of FPGA and the outside parallel port ROM of fpga chip jointly as its program storage; The MCU preprogrammed instruction in execution block memory and the external ROM successively finishes the initialization of FPGA work register.
MCU adopts the principal and subordinate PC design of tape verifying logic; Principal and subordinate PC counts synchronously, does not wait as the two numerical value, and principal and subordinate PC will reset simultaneously in the next clock cycle, and MCU gets and refers to that units synchronization stops the instruction fetch operation of next clock cycle.
Control module is to adopt PI (ratio, integration) algorithm to the computing of velocity setting and speed feedback, and in described fpga chip, be embedded the hardware computing module, carry out the real-time parallel computing by described computing module, the coefficient register of described computing module is by the online read-write of host computer.
Driver module is with motor Hall element phase difference, turns to set-point and Hall feedback signal as the address Hall truth table of storing in the described FPGA internal block memory to be tabled look-up to obtain drive signal without pulse-width modulation.
The ADC modulus conversion chip adopts the AD7819 chip with low-power consumption mode and high-speed sampling pattern, described AD7819 chip carries out the switching of low-power consumption mode to the high-speed sampling pattern by the embedded house dog of fpga chip after powering up, and works under the high-speed sampling pattern.
Compared with the prior art, beneficial effect of the present invention is embodied in:
1. the present invention adopts monolithic FPGA to realize controlled function; Inner each the module sequential of FPGA realizes by the hardware sequencer; Global reliability is better than the multi-disc system that adopts the system of general single chip and adopt single-chip microcomputer and FPGA simultaneously.
The present invention can by adopt inner Distributed RAM of FPGA and outside parallel port ROM jointly as the program storage of its embedded MCU to finish the user register initialization, the user only need understand 10 instructions and each user register address of MCU, can be to initialize routine programming in the external ROM, it is satisfied use needs, wherein do not relate to the FPGA original program, with respect to known Programmable Logic Controller, use more simple.
3. the present invention can be by adopting the embedded MCU of two PC structures, and making resetting time only is a clock cycle, is better than the watchdog reset mode that general single chip adopts.
4. control module of the present invention can adopt independently concurrent operation logic realization, and the computing time-delay is little and constant, and the computing real-time is better than adopting single-chip microcomputer to finish the system of control algolithm.
Description of drawings:
Fig. 1 is a system hardware block diagram of the present invention.
Fig. 2 is fpga chip configuration principle figure of the present invention.
Fig. 3 is TTL-LVTTL level shifting circuit figure of the present invention.
Fig. 4 is an analog to digital conversion circuit schematic diagram of the present invention.
Fig. 5 is a TTL-RS232 level shifting circuit schematic diagram of the present invention.
Fig. 6 is a photoelectric isolating circuit schematic diagram of the present invention.
Fig. 7 is a MOSFET power amplification circuit schematic diagram of the present invention.
Fig. 8 is a current sample pre-amplification circuit schematic diagram of the present invention.
Fig. 9 is fpga chip functional module and interface specification.
Figure 10 is a fpga chip driver module block diagram of the present invention.
Figure 11 is a fpga chip communication module block diagram of the present invention.
Figure 12 is a system initialization flow chart of the present invention.
Below pass through embodiment, and the invention will be further described in conjunction with the accompanying drawings.
Embodiment:
Referring to Fig. 1, controlling object has been selected the non-brush permanent-magnet DC motor of 24V/16W for use in the present embodiment, and its built-in Hall element phase difference is 120 degree, is furnished with the axis light code disc of 200 line/circles.Motor is the three-phase ends of the earth, commutates weekly 4 times, and torque fluctuations is less.Controller is made up of two parts: control section is core with the fpga chip, by level conversion, analog-to-digital conversion and charactron show, toggle switch is given etc., and auxiliary circuit is formed; Drive part is made up of photoelectricity isolation, preposition amplification and three-phase MOSFET power bridge.
Fpga chip is selected the SpartanIIS150 of Xilinx company for use in the present embodiment, and its inside comprises about 3888 logical blocks, the twoport block storage BlockRAM of 48Kbit, core voltage 2.5V, adopt initiatively series arrangement pattern, realize that by special chip XCF01 configuration circuit as shown in Figure 2.
The Hall circuit of motor and photoelectric code disk are by extra low-tension supply power supply, and signal is+5V standard Transistor-Transistor Logic level, need be converted to the LVTTL of the 3.3V consistent with fpga chip.Change-over circuit as shown in Figure 3; three road hall signal Hall1, Hall2, Hall3 send into the 74HC14 of 3.3V power supply after filtering, the protection feedback signal Fault_n of two-way photoelectric pulse signal channel_A, channel_B and the self-driven plate of coming directly inserts 74HC14 and is converted to the LVTTL level.
Referring to Fig. 4, the current feedback of motor adopts 8 modulus conversion chip AD7819 to realize that the highest sample rate can reach 200KPS, and its parallel data grabbing card can obtain littler sampling time-delay with respect to serial ports ADC.Provide the reference voltage source of a 2.5V by TL431 for ADC,
Shown in Figure 5, adopt PC in the present embodiment, promptly personal computer is as host computer, and the serial ports level is the RS232 standard, and adopts ICL3232 to carry out level conversion between the fpga chip.Can bear 5V voltage when the input port of SpartanII is configured to the LVTTL standard, therefore, ICL3223 uses 5V or 3.3V power supply all can.
Shown in Figure 6, drive part uses motor power+24V power supply, and PWM input signal and protection feedback signal are all passed through light-coupled isolation.High speed photo coupling 6N137 is used to isolate pwm signal.
The IR2130 based on the floating boom Driving technique is adopted in the driving of power tube, and it can move altogether with the motor high voltage source, thereby realizes the single supply design of power model.This chip can drive 6 N-channel MOS FET simultaneously and form the three phase power bridge, and has excess current protective function, and its typical application principle figure as shown in Figure 7.
Referring to Fig. 8, the pressure drop on the inspection leakage resistance is carried out delivering to the ADC module after the preposition amplification through filtering and by LM358.
Fpga chip has been integrated drive waveforms generation, closed-loop control computing and host computer communication function as controller core.As shown in Figure 9, most Control Parameter can be given jointly by toggle switch and host computer, comprises PWM output enable, brake, commutation, pulsewidth/velocity setting, and input parameter is sent into control and driver module after judging through the fpga chip internal priority.Communication module is then finished the initialization and the Long-distance Control of controller parameter.
The kind of the Hall element phase place base pin selection of fpga chip and Hall feedback pin decision drive motors: when driving brush motor, the Hall phase place selects pin to connect high level, U phase Hall feedback pin connects high level, V, W two low level of joining, drive part constitute the H bridge by U phase, W phase upper and lower bridge arm and drive; When connecing three-phase brushless motor, Hall feedback pin is used to import the rotor-position feedback signal of motor, Hall phase place selection pin should be consistent with the phase place of motor Hall element: when the Hall element phase difference is 60/300, this pin connects high level, connect low level at 120/240 o'clock, and selected the latter in the present embodiment.
Driver module has comprised the PWM waveform generation; motor rotor position decoding, brake and overcurrent protection, dead band are detected, are driven motor open loops such as sequencing control, ADC control state machine, speed feedback pulse counter and charactron display driver and drive required function, referring to Figure 10.
The pulsewidth specified rate of drive signal is 8, and by the decision of numeric ratio in outside toggle switch and the pulse width register (initialization when powering up of described pulse width register also can be read and write by host computer), comparator can select one of them smaller value as effective input variable.When host computer carried out speed governing, outside toggle switch can carry out speed limit.When open/when the closed-loop control position was chosen as closed-loop control, the value of the given register of pulsewidth was used as the velocity setting amount and sends into control module, the pulsewidth specified rate that obtains through computing replaces the value of former pulse width register and sends into driver module.The PWM wave producer produces corresponding PWM carrier wave according to pulsewidth, and carrier frequency is 20.8KHz (cycle 48.1uS), and the duty cycle adjustment scope is 15.6%～95.0%, and corresponding pulsewidth is about 7.5uS～45.7uS.
The rotor-position decoder is selected position, direction of rotation position and three road hall signals to table look-up according to the Hall phase place and is drawn the drive signal of power bridge.The brachium pontis drive signal is modulated carrier wave as the gate-control signal of PWM under three the tunnel, and the brachium pontis signal is not done the PWM modulation on three the tunnel.The hall signal of mistake can be hunted down and be presented on the LED, and all power tubes are cut off simultaneously.
During motor braking, the drive signal of controller output is all ended the brachium pontis power tube, and dynamic braking is carried out in the whole conductings of following brachium pontis, needs to consider the dissipation power of power tube this moment.Also can use power resistor to make the energy consumption element, switch, select the former for use in the present embodiment by output enable foot control system relay.
The drive signal of dc brushless motor can not make upper and lower bridge arm switch simultaneously, and still, there are the possibility that makes the power model bridge arm direct pass in brake and when commutation, and therefore, built-in programmable dead band generator is to avoid the generation of above-mentioned situation.Dead Time is adjustable from 300nS～67.2uS, and this timing definition is minimum Dead Time, and set point should be less than the Dead Time of driven signal.The Dead Time that causes drive signal when brake or commutation is during less than setting-up time, and the dead band occurrence logic can prolong Dead Time to set point.
Dual overcurrent protection is arranged in the present embodiment, finished by outside current foldback circuit and fpga chip internal protection logic respectively, protect when effective when overcurrent, power tube is all ended.The overcurrent protection of power tube is finished by IR2130 on the drive plate, and the about 150nS of its action delay can feed back to FPGA with over-current signal in the time of protection.The internal protection signal is from the current feedback module, and the about 20uS of its action delay is used to protect motor.The current feedback module is made of the state machine of a band house dog, the AD7819 that is used for feedback sample has two kinds of mode of operations: low-power consumption mode and high-speed sampling pattern, powering up back device initialization state is low-power consumption mode, house dog drives its continuous sampling by state machine after making it switch to the high-speed sampling pattern again, when the ADC output valve was maximum, the current feedback module will produce an inner over-current signal.Above-mentioned two kinds of over-current signals all can cause FPGA power output pipe pick-off signal.When the overcurrent feedback signal was invalid, the overcurrent protection logic can be reset by the low level of inner pwm signal, and the next cycle pwm signal will normally be exported.
Frequent brake and output are transformed into the time-delay detection that normal output has 320mS by the restriction that can be activated time sequence control logic by brake or cut-off state, and the given signal of control that pulsewidth is lower than this value can not make the driving logic produce corresponding action.
The speed feedback of motor is by an output step-by-step counting with the photoelectric code disk of motor coaxle installation is realized.This code-disc is an increment type traying, and output A, B two-way have the pulse signal of 90 degree phase differences during the motor rotation.10mS timer control counter counts to get rotating speed to the feedback pulse of photoelectric code disk, and direction of rotation is then by detecting the polarity judging of A, B two-way pulse phase difference.The rotating speed that calculates drives charactron through the decoding back by scanning logic and shows in real time, also delivers to control module to finish the closed loop computing simultaneously.
Control module adopts the PI control algolithm, can be expressed as:
Above-mentioned expression formula is carried out real-time operation by the hardware computing module in the FPGA, and ratio, integral coefficient can be by the host computer online change.The integral operation circuit has the limit of integration and detects logic and cause system oscillation to prevent that integration is saturated, and after output reached minimum pulse width, the integration accumulator was only done addition, did not add otherwise then only subtract.
What communication module was used to finish register in driver module and the control module powers up initialization and host computer communication function, and its core is an embedded MCU that has the UART mouth, sees Figure 11.
The UART baud rate is 9600Bd, and promptly each data bit period is about 104us.Its transmission, reception data format are: a start bit (low level), and 8 bit data positions, a position of rest (high level), start bit detects logic can discern the low level interference signal that pulsewidth is lower than 52us.
MCU adopts instruction fetch, instruction decoding, instruction to carry out three class pipeline structure, dominant frequency 10MHz.Totally 8 of MCU instructions, wherein high 4 of the instruction of MCU register write operation is command code, low 4 is several immediately, and all the other command formats are: high 4 is that command code, low 4 are check codes, has the instruction of check code and check errors to be got by MCU and refers to that the unit replaces with non-operation instruction.
Have two eight bit registers to be respectively applied for the address in the MCU and deposit with data and deposit, in the register manipulation instruction 4 count immediately that gradation write the address, high 4 and low 4 of data register is formed 8 bit address and data.MCU uses above-mentioned register and user register to carry out exchanges data, and maximum can be managed 256 8 user registers, and these user registers are independent assortment neatly also, for example is defined as 128 16 bit registers.
The enable bit of MCU status word is ' 0 ' after the system power-up initialization, get refer to the unit promptly from program storage instruction fetch see Figure 12 to finish the initialization that powers up of register.Instruction address is provided by main PC (program counter), the numerical value of counting synchronously from PC and main PC is sent into the PC check logic together and is compared, the check errors signal will make PC at next clock-reset, and stop the instruction fetch operation (during pile line operation, the instruction of main PC current address correspondence will be taken out in the next clock cycle) of next clock cycle.Program storage is made up of inner DistributedRAM of FPGA and outside parallel port ROM, store the default parameters that presets in the internal RAM and need not the information that the user changes, external ROM is by user program, the instruction of the last item of program should be changed to ' 1 ' with the initialization enable bit, thereby makes MCU enter hardware query State to the UART receiver.Reserved the ROM interface in the present embodiment and only used internal RAM as program storage.
After initialization was finished, controller entered operating state, and the given of the initial value of user register and outside toggle switch judged the running parameter specified rate of back as controller through priority.When controller worked alone, it is given that the user can carry out controlled quentity controlled variable by toggle switch; When adopting PC control, toggle switch should be predisposed to the state specified rate of low priority, and this moment, controller parameter was determined by the value in the user register fully.
When the UART interface received the host computer instruction, MCU was instruction fetch and carries out, otherwise inserts non-operation instruction.By the numerical value in the read-write user register, host computer can online adapter control module be realized long-range speed closed loop control, thereby realizes the upgrading of control algolithm.
Claims (7)
1. the DC motor controller based on FPGA is characterized in that being made up of fpga chip, FPGA configuring chip, ADC modulus conversion chip, power module and power amplifier module;
Described electric machine controller utilizes fpga chip that the motor Hall feedback signal of input is decoded, and obtains motor rotor position to drive the three-phase direct-current brushless motor; Or the fpga chip Hall feedback input end predetermined level that is set to fix, to drive brush direct current motor; Electric machine controller is caught the two pulse signals of motor photoelectric code disk by fpga chip, and relatively the two phase place draws the direction of rotation of rotor, and pulse count obtains motor speed; Electric machine controller utilizes fpga chip control ADC modulus conversion chip that the armature supply of motor is carried out the constant cycle sampling;
Driver module, control module and communication module are set respectively in described fpga chip; To velocity setting and speed feedback comparison and computing, draw drive signal pulsewidth set-point by control module; Driver module produces the PWM drive signal that has Dead Time able to programme accordingly according to described pulsewidth set-point and motor rotor position feedback signal, exports power amplifier module to by fpga chip, and drive motors constitutes the closed-loop speed control system; Described communication module comprises an embedded MCU that contains the UART interface at least, by the user register in the described MCU management fpga chip, and communicates by letter with host computer by the UART interface; After fpga chip is finished configuration, by described MCU fpga chip is carried out the initialization of internal user register, and send handshake to host computer by described UART interface; Host computer is communicated by letter with described MCU by the UART interface, and reads and writes the user register in the fpga chip in real time, realizes the Long-distance Control to motor.
2. DC motor controller according to claim 1 is characterized in that the embedded MCU of described fpga chip adopts instruction fetch-instruction decoding-instruction to carry out three class pipeline and 8 bit instruction buses; Wherein high 4 of the instruction of MCU register write operation is command code, low 4 is several immediately, host computer sends described register write operation instruction by the UART interface MCU register is carried out write operation, and verifies the correctness that instruction is carried out by the numerical value that reads register; It is that command code, low 4 are check codes that all the other command formats are high 4, and the instruction that check code and check errors arranged is got by MCU and referred to that the unit replaces with non-operation instruction.
3. DC motor controller according to claim 2 is characterized in that described MCU uses inner distributed memory of FPGA and the outside parallel port ROM of fpga chip jointly as its program storage; MCU carries out the initialization that preprogrammed instruction in inner distributed memory of FPGA and the outside parallel port ROM of fpga chip is finished the FPGA work register successively.
4. DC motor controller according to claim 2 is characterized in that described MCU adopts the principal and subordinate PC design of tape verifying logic; Principal and subordinate PC counts synchronously, does not wait as the two numerical value, and principal and subordinate PC will reset simultaneously in the next clock cycle, and MCU gets and refers to that units synchronization stops the instruction fetch operation of next clock cycle.
5. DC motor controller according to claim 1, it is characterized in that described control module is to adopt the PI algorithm to the computing of velocity setting and speed feedback, and in described fpga chip, be embedded the hardware computing module, carry out the real-time parallel computing by described computing module, the coefficient register of described computing module is by the online read-write of host computer.
6. DC motor controller according to claim 3 is characterized in that described driver module is with motor Hall element phase difference, turns to set-point and Hall feedback signal as the address Hall truth table of storing in the inner distributed memory of described FPGA to be tabled look-up to obtain drive signal without pulse-width modulation.
7. DC motor controller according to claim 1, it is characterized in that described ADC modulus conversion chip adopts the AD7819 chip with low-power consumption mode and high-speed sampling pattern, described AD7819 chip carries out the switching of low-power consumption mode to the high-speed sampling pattern by the embedded house dog of fpga chip after powering up, and works under the high-speed sampling pattern.
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| JP2000330641A (en) * | 1999-05-18 | 2000-11-30 | Toshiba Mach Co Ltd | Servo controller |
| US6281657B1 (en) * | 1999-03-24 | 2001-08-28 | Olympus Optical Co., Ltd. | Image detecting apparatus and method |
| JP2001322078A (en) * | 2000-05-15 | 2001-11-20 | Sanyo Electric Co Ltd | Robot control device |
| CN1570794A (en) * | 2004-05-14 | 2005-01-26 | 北京博创兴工科技有限公司 | Numerical control system for machine tool |
| JP2005102377A (en) * | 2003-09-24 | 2005-04-14 | Gifu Univ | Multishaft motor control system |
| CN1808319A (en) * | 2005-12-13 | 2006-07-26 | 天津大学 | Parallel connection equipment opening type motion control card based on two-stage DSP and control method thereof |
-
2006
- 2006-09-15 CN CNB2006100415518A patent/CN100409558C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281657B1 (en) * | 1999-03-24 | 2001-08-28 | Olympus Optical Co., Ltd. | Image detecting apparatus and method |
| JP2000330641A (en) * | 1999-05-18 | 2000-11-30 | Toshiba Mach Co Ltd | Servo controller |
| JP2001322078A (en) * | 2000-05-15 | 2001-11-20 | Sanyo Electric Co Ltd | Robot control device |
| JP2005102377A (en) * | 2003-09-24 | 2005-04-14 | Gifu Univ | Multishaft motor control system |
| CN1570794A (en) * | 2004-05-14 | 2005-01-26 | 北京博创兴工科技有限公司 | Numerical control system for machine tool |
| CN1808319A (en) * | 2005-12-13 | 2006-07-26 | 天津大学 | Parallel connection equipment opening type motion control card based on two-stage DSP and control method thereof |
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| CN1929288A (en) | 2007-03-14 |
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