CN106789507A - It is a kind of to realize the method and apparatus that central processing unit communicates with functional chip - Google Patents
It is a kind of to realize the method and apparatus that central processing unit communicates with functional chip Download PDFInfo
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- CN106789507A CN106789507A CN201611174968.1A CN201611174968A CN106789507A CN 106789507 A CN106789507 A CN 106789507A CN 201611174968 A CN201611174968 A CN 201611174968A CN 106789507 A CN106789507 A CN 106789507A
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- order
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- ethernet frame
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
Abstract
The method and apparatus that central processing unit communicates with functional chip are realized this application provides a kind of, the method includes：When FPGA receives the order ethernet frame of central processing unit transmission, cached；When a complete order ethernet frame is cached, the operational order in the order ethernet frame is read from caching, and produced on local bus the signal corresponding with functional chip and sequential to be operated according to the operational order；Data are read from local bus and store；When the operational order in completing the complete order ethernet frame, according to predefined frame structure, the return ethernet frame of return implementing result is generated using the data and operational order of storage, and be sent to central processing unit.The technical scheme can extend the range of management of central processing unit, reduce the complexity of system, improve the operating rate of central processing unit.
Description
Technical field
It is more particularly to a kind of to realize the method that central processing unit communicates with functional chip the present invention relates to communication technical field
And device.
Background technology
In a communication equipment for complexity, often it is made up of master control borad and polylith various functions tributary card, and every piece
There is multi-plate chip to realize various functions on plate.
On general master control borad processor by local bus (local bus) be connected to each chip be controlled, state reporting,
Or the function such as other information transmissions realizes co-ordination, but this method has certain limitation, if desired for more
Line, and because cabling is more long, rate-constrained has dragged down processor operating rate；Cable run distance is more long to also result in stability
Also easily go wrong；The larger direct management of span can not be realized, system scale is limited.
Can also be by the way of multiprocessor, the functional chip around each processor management passes through between processor again
Certain mode communication-cooperation works, and so considerably increases system complexity.
The content of the invention
In view of this, the application offer is a kind of realizes the method and apparatus that central processing unit communicates with functional chip, to solve
Certainly system complex, dimension-limited, the low problem of operating efficiency.
In order to solve the above technical problems, what the technical scheme of the application was realized in：
It is a kind of to realize the method that central processing unit communicates with functional chip, increase and pass through ether Netcom with central processing unit
Letter, the FPGA for passing through Local bus communication with functional chip, the method includes：
When the FPGA receives the order ethernet frame of central processing unit transmission, cached；
When a complete order ethernet frame is cached, the operation life in the order ethernet frame is read from caching
Order, and produced on local bus the signal corresponding with functional chip and sequential to be operated according to the operational order；
Data are read from local bus and store；
When the operational order in completing the complete order ethernet frame, according to predefined frame structure, using depositing
The return ethernet frame of data and operational order the generation return implementing result of storage, and it is sent to central processing unit.
A kind of to realize the device that central processing unit communicates with functional chip, the device is applied to increase and leads to central processing unit
Ethernet communication is crossed, on the FPGA for passing through Local bus communication with functional chip, the device includes：Receiving unit, memory cell,
Processing unit, generation unit and transmitting element；
The receiving unit, for receiving order ethernet frame；
The memory cell, during for the order ethernet frame that central processing unit transmission is received when the receiving unit,
Cached；The data storage that the processing unit is read from local bus；
The processing unit, for when the memory cell caches a complete order ethernet frame, from caching
Read the operational order in the order ethernet frame, and produced on local bus according to the operational order relative with functional chip
The signal and sequential answered are operated；And read data from local bus；
The generation unit, for when the operational order in the processing unit completion complete order ethernet frame
When, according to predefined frame structure, the return ethernet frame of return implementing result is generated using the data and operational order of storage；
The transmitting element, for the return ethernet frame that the generation unit is generated to be sent into central processing unit.
As can be seen from the above technical solution, Ethernet and local bus are changed by using FPGA in the application, in realization
Operation of the central processor to each functional chip register, can extend the range of management of central processing unit, reduce the complexity of system
Property, improve the operating rate of central processing unit.
Brief description of the drawings
Fig. 1 is system structure diagram in the embodiment of the present application；
Fig. 2 is predefined frame structure in the embodiment of the present application；
Fig. 3 realizes the schematic flow sheet that central processing unit communicates with functional chip for the embodiment of the present application；
Fig. 4 is applied to the apparatus structure schematic diagram of above-mentioned technology for the application.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, develop simultaneously embodiment below in conjunction with the accompanying drawings,
Technical scheme is described in detail.
, it is necessary to many various functions chips coordinate work in a complication system, system allomeric function is realized,
Central processing unit is needed to be managed control to each functional chip for this.
When systematic comparison is huge, central processing unit is directly connected to each functional chip by local bus relatively difficult, this Shen
When please implement, in each functional module divided according to the concrete structure of system, a field-programmable gate array is placed
Row (FPGA, Field Programmable Gate Array), FPGA passes through ethernet communication with central processing unit, by this
Ground bus communicates with each functional chip.
Referring to Fig. 1, Fig. 1 is system structure diagram in the embodiment of the present application.The FPGA numbers increased newly in Fig. 1 are according to system
The functional module of division determines.
The local bus mentioned in the application are central processing unit (CPU) local bus, and functional chip is to realize function
Chip.When implementing, the modular structure divided using communication system no longer repartitions module to the application.One mould
Block may correspond to the functional chip for realizing One function, it is also possible to which correspondence realizes the functional chip of multiple functions, One function core
Piece can be the chip for realizing One function, or the chip for realizing multiple functions, in this regard, the application is not restricted.
Now mostly central processing unit there is Ethernet interface, when the application is implemented, directly using it is already present with
Too network interface receives and dispatches ethernet frame.
Predefined frame structure is pre-configured with central processing unit and FPGA, so that central processing unit and FPGA can be mutual
Mutually recognize the ethernet frame for receiving.
Referring to Fig. 2, Fig. 2 is predefined frame structure in the embodiment of the present application.
DA, SA in Fig. 2, fill purpose and source media access control (MAC) address, are the MAC of central processing unit and FPGA
Address.When FPGA receives the order ethernet frame of central processing unit transmission, target MAC (Media Access Control) address is the MAC Address of FPGA, source
MAC Address is the MAC Address of central processing unit；When FPGA generations and the return ethernet frame to central processing unit transmission, source MAC
Address is the MAC Address of FPGA, and target MAC (Media Access Control) address is the MAC Address of central processing unit.
Type：Frame type, selects a numerical value different from agreement is currently known.
Protocol：Protocol number.
Order：Frame number, the frame number of order ethernet frame can with realization incremented by successively, return ethernet frame with it is corresponding
The frame number of order ethernet frame is consistent, so that central processing unit easily determines whether order ethernet frame is lost.
Operate code：Command code.
Ind：
Bit3-0：1H：Write operation；2H：Read operation；3H：Write operation echo back data；4H：Read operation echo back data.
Addr：Address, can distinguish chip with high address, and low order address is used for register in chip.
Data：Read-write data.To write data when order is write, order is filled with 0 when reading, and is loopback reserved location.During loopback
It is register readout.
The length of Addr and Data can specifically need regulation according to system.A frame can include one or more as needed
operate code。
End：Present frame operates end mark, is fixed as 0.
Pad：Region filling, if frame not enough minimum Ethernet frame length filling 0.
FCS：CRC (CRC, Cyclic Redundancy Check) check code.
Below in conjunction with the accompanying drawings, describe the application in detail and the mistake that central processing unit communicates with functional chip is realized by FPGA
Journey.
Referring to Fig. 3, Fig. 3 realizes the schematic flow sheet that central processing unit communicates with functional chip for the embodiment of the present application.Tool
Body step is：
Step 301, when FPGA receives the order ethernet frame of central processing unit transmission, is cached.
FPGA is received after the order ethernet frame of central processing unit transmission, before being cached, is further performed such as
Lower treatment：
The FPGA carries out CRC check to the order ethernet frame, the order ethernet frame of deletion error, and according to predetermined
The domains such as DA, SA, Type in the frame structure check command ethernet frame of justice, i.e. verification frame, only retain to functional chip operation
Order ethernet frame；Other frames are all abandoned, and prevent maloperation.
Step 302, when the FPGA caches a complete order ethernet frame, reads the order Ethernet from caching
Operational order in frame, and produced on local bus the signal corresponding with functional chip and sequential to enter according to the operational order
Row operation.
The speed of chip operation is mismatched due to ethernet frame and by local bus, therefore, because first caching Ethernet
Frame, one complete ethernet frame of start to process after a whole frame has been received.
The operational order in the order ethernet frame is read from caching in this step, and according to the operational order local
When the generation signal corresponding with functional chip and sequential are operated in bus, if operational order is to read, from function core
Data are read in piece；If operational order is to write, read the register of write-once data after writing data in functional chip again.
Step 303, the FPGA reads data and stores from local bus.
Step 304, the FPGA when the operational order in completing the complete order ethernet frame, according to predefined
Frame structure, generates the return ethernet frame of return implementing result, and be sent to centre using the data and operational order of storage
Reason device.
FPGA generates return and performs knot according to predefined frame structure using the data and operational order of storage in this step
During the return ethernet frame of fruit, CRC check code is also produced, and carried in ethernet frame is returned, so that central processing unit can
Carry out CRC check.
The FPGA generates returning for return implementing result according to predefined frame structure using the data and operational order of storage
During report ethernet frame, the frame number consistent with the frame number of correspondence order ethernet frame is carried in ethernet frame is returned, so that
Central processing unit judges whether order ethernet frame is lost according to frame number.
If receiving the return ethernet frame of the frame number for carrying correspondence order ethernet frame, it is determined that the order Ethernet
Frame is not lost；Otherwise, it determines the order ethernet frame is lost.
The unit of above-described embodiment can be integrated in one, it is also possible to be deployed separately；A unit can be merged into, also may be used
To be further split into multiple subelements.
In sum, the application changes Ethernet and local bus by using FPGA, realizes central processing unit to each work(
The operation of energy chip register, can extend the range of management of central processing unit, reduce the complexity of system, improve center treatment
The operating rate of device.
Based on same inventive concept, the application also proposes a kind of to realize the dress that central processing unit communicates with functional chip
Put, the device is applied to increase with central processing unit by ethernet communication, with functional chip by Local bus communication
On FPGA.Referring to Fig. 4, Fig. 4 is applied to the apparatus structure schematic diagram of above-mentioned technology for the application.The device includes：Receiving unit
401st, memory cell 402, processing unit 403, generation unit 404 and transmitting element 405；
Receiving unit 401, for receiving order ethernet frame；
Memory cell 402, during for the order ethernet frame that central processing unit transmission is received when receiving unit 401, enters
Row caching；The data storage that processing unit 403 is read from local bus；
Processing unit 403, for when memory cell 402 caches a complete order ethernet frame, reading from caching
The operational order gone out in the order ethernet frame, and produced on local bus according to the operational order corresponding with functional chip
Signal and sequential operated；And read data from local bus；
Generation unit 404, for completing the complete order ethernet frame when processing unit 403 in operational order
When, according to predefined frame structure, the return ethernet frame of return implementing result is generated using the data and operational order of storage；
Transmitting element 405, the return ethernet frame for generation unit 404 to be generated is sent to central processing unit.
It is preferred that
Processing unit 403, specifically for reading the operational order in the order ethernet frame from caching, and according to the behaviour
When ordering that the generation signal corresponding with functional chip and sequential are operated on local bus, if operational order is
Read, then data are read from functional chip；If operational order is to write, write-once is read again after writing data in functional chip
The register of data.
It is preferred that
The field that the predefined frame structure includes is：Purpose and source MAC, frame type, protocol number, frame sequence
Number, command code, present frame operation end mark, check code；Wherein, when frame structure is the corresponding frame structure of order ethernet frame
When, padding order in command code；When frame structure frame structure corresponding for return ethernet frame, padding in command code
As a result.
It is preferred that
Processing unit 403, is further used for being received in receiving unit 401 the order ethernet frame of central processing unit transmission
Afterwards, before memory cell 402 is cached, CRC check, the order ether of deletion error are carried out to the order ethernet frame
Net frame, and according to predefined frame structure check command ethernet frame, only retain the order ethernet frame to functional chip operation；
Generation unit 404, is further used for according to predefined frame structure, is generated using the data and operational order of storage
When returning the return ethernet frame of implementing result, CRC check code is produced, and carry in ethernet frame is returned.
It is preferred that
Generation unit 404, is further used for according to predefined frame structure, is generated using the data and operational order of storage
When returning the return ethernet frame of implementing result, the frame number one with corresponding order ethernet frame is carried in ethernet frame is returned
The frame number of cause, so that central processing unit judges whether order ethernet frame is lost according to frame number.
General Ethernet transmission information is used in the embodiment of the present application, localbus bus access is converted to by FPGA
The register of each functional chip；And operating result is passed back to processor by Ethernet；Using DA, SA, Type, Protocol
Deng domain identification information filtering useless ethernet frame；Add frame number to determine whether the information frame lost using to ethernet frame, make
Can be with the range of management of extensible processor with multiple FPGA.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, it is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (10)
1. it is a kind of to realize the method that central processing unit communicates with functional chip, it is characterised in that increase passes through with central processing unit
Ethernet communication, the on-site programmable gate array FPGA for passing through Local bus communication with functional chip, the method includes：
When the FPGA receives the order ethernet frame of central processing unit transmission, cached；
When a complete order ethernet frame is cached, the operational order in the order ethernet frame is read from caching, and
The signal corresponding with functional chip and sequential is produced on local bus to be operated according to the operational order；
Data are read from local bus and store；
When the operational order in completing the complete order ethernet frame, according to predefined frame structure, storage is used
The return ethernet frame of data and operational order generation return implementing result, and it is sent to central processing unit.
2. method according to claim 1, it is characterised in that the behaviour read from caching in the order ethernet frame
Order, and produced on local bus the signal corresponding with functional chip and sequential to be operated according to the operational order
When, if operational order is to read, data are read from functional chip；If operational order is to write, write in functional chip
Read the register of write-once data after data again.
3. method according to claim 1 and 2, it is characterised in that
The field that the predefined frame structure includes is：Purpose and source MAC address, frame type, agreement are compiled
Number, frame number, command code, present frame operation end mark, check code；Wherein, when frame structure is that order ethernet frame is corresponding
During frame structure, padding order in command code；When frame structure frame structure corresponding for return ethernet frame, filled out in command code
Fill operating result.
4. method according to claim 3, it is characterised in that the FPGA receive the order of central processing unit transmission with
Too after net frame, it is described cached before, methods described is further included：
It is circulated redundancy check code CRC check to the order ethernet frame, the order ethernet frame of deletion error, and according to
Predefined frame structure check command ethernet frame, only retains the order ethernet frame to functional chip operation；
It is described according to predefined frame structure, use the data and operational order of storage to generate the return ether of return implementing result
During net frame, methods described is further included：CRC check code is produced, and is carried in ethernet frame is returned.
5. method according to claim 3, it is characterised in that described according to predefined frame structure, uses the number of storage
During according to returning the return ethernet frame of implementing result with operational order generation, methods described is further included：
The frame number of the return ethernet frame is consistent with the frame number of the corresponding order ethernet frame for receiving, so that central processing unit
Judge whether order ethernet frame is lost according to frame number.
6. it is a kind of to realize the device that central processing unit communicates with functional chip, it is characterised in that the device is applied to increase with
Central processor on the on-site programmable gate array FPGA for passing through Local bus communication with functional chip, is somebody's turn to do by ethernet communication
Device includes：Receiving unit, memory cell, processing unit, generation unit and transmitting element；
The receiving unit, for receiving order ethernet frame；
The memory cell, during for the order ethernet frame that central processing unit transmission is received when the receiving unit, is carried out
Caching；The data storage that the processing unit is read from local bus；
The processing unit, for when the memory cell caches a complete order ethernet frame, being read from caching
Operational order in the order ethernet frame, and produced on local bus according to the operational order corresponding with functional chip
Signal and sequential are operated；And read data from local bus；
The generation unit, for being completed when the processing unit during operational order in the complete order ethernet frame,
According to predefined frame structure, the return ethernet frame of return implementing result is generated using the data and operational order of storage；
The transmitting element, for the return ethernet frame that the generation unit is generated to be sent into central processing unit.
7. device according to claim 6, it is characterised in that
The processing unit, specifically for reading the operational order in the order ethernet frame from caching, and according to the operation
Order when producing the signal corresponding with functional chip and sequential to be operated on local bus, if operational order is reading,
Data are then read from functional chip；If operational order is to write, write-once number is read again after writing data in functional chip
According to register.
8. the device according to claim 6 or 7, it is characterised in that
The field that the predefined frame structure includes is：Purpose and source MAC address, frame type, agreement are compiled
Number, frame number, command code, present frame operation end mark, check code；Wherein, when frame structure is that order ethernet frame is corresponding
During frame structure, padding order in command code；When frame structure frame structure corresponding for return ethernet frame, filled out in command code
Fill operating result.
9. device according to claim 8, it is characterised in that
The processing unit, be further used for the receiving unit receive central processing unit transmission order ethernet frame it
Afterwards, before the memory cell is cached, redundancy check code CRC check is circulated to the order ethernet frame, is deleted
The order ethernet frame of mistake, and according to predefined frame structure check command ethernet frame, only retain and functional chip is operated
Order ethernet frame；
The generation unit, is further used for according to predefined frame structure, is generated back using the data and operational order of storage
When reporting the return ethernet frame of implementing result, CRC check code is produced, and carry in ethernet frame is returned.
10. device according to claim 8, it is characterised in that
The generation unit, is further used for according to predefined frame structure, is generated back using the data and operational order of storage
When reporting the return ethernet frame of implementing result, carry consistent with the frame number of correspondence order ethernet frame in ethernet frame is returned
Frame number so that central processing unit judges whether order ethernet frame is lost according to frame number.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611174968.1A CN106789507A (en) | 2016-12-19 | 2016-12-19 | It is a kind of to realize the method and apparatus that central processing unit communicates with functional chip |
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| CN201611174968.1A CN106789507A (en) | 2016-12-19 | 2016-12-19 | It is a kind of to realize the method and apparatus that central processing unit communicates with functional chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111427811A (en) * | 2020-03-19 | 2020-07-17 | 上海御渡半导体科技有限公司 | Device and method for improving communication rate of DDR controlled by PCIE |
| CN113179216A (en) * | 2021-04-23 | 2021-07-27 | 北京物芯科技有限责任公司 | Remote configuration method of register, computer equipment and storage medium |
| CN115964333A (en) * | 2023-03-17 | 2023-04-14 | 之江实验室 | Communication method of multi-chip neural network algorithm based on FPGA (field programmable Gate array) master control |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1558332A (en) * | 2004-01-18 | 2004-12-29 | 中兴通讯股份有限公司 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
| CN1929288A (en) * | 2006-09-15 | 2007-03-14 | 合肥工业大学 | DC motor controller based on FPGA |
| CN101917316A (en) * | 2010-09-13 | 2010-12-15 | 北京航空航天大学 | Communication method and device for high-speed real-time industrial Ethernet |
| CN102377778A (en) * | 2011-10-17 | 2012-03-14 | 中国人民解放军国防科学技术大学 | Remote asymmetric end communication method based on Ethernet |
| CN103701707A (en) * | 2013-12-03 | 2014-04-02 | 杭州华三通信技术有限公司 | Network equipment |
-
2016
- 2016-12-19 CN CN201611174968.1A patent/CN106789507A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1558332A (en) * | 2004-01-18 | 2004-12-29 | 中兴通讯股份有限公司 | Device and method for implementing automatically reading and writing internal integrated circuit equipment |
| CN1929288A (en) * | 2006-09-15 | 2007-03-14 | 合肥工业大学 | DC motor controller based on FPGA |
| CN101917316A (en) * | 2010-09-13 | 2010-12-15 | 北京航空航天大学 | Communication method and device for high-speed real-time industrial Ethernet |
| CN102377778A (en) * | 2011-10-17 | 2012-03-14 | 中国人民解放军国防科学技术大学 | Remote asymmetric end communication method based on Ethernet |
| CN103701707A (en) * | 2013-12-03 | 2014-04-02 | 杭州华三通信技术有限公司 | Network equipment |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111427811A (en) * | 2020-03-19 | 2020-07-17 | 上海御渡半导体科技有限公司 | Device and method for improving communication rate of DDR controlled by PCIE |
| CN113179216A (en) * | 2021-04-23 | 2021-07-27 | 北京物芯科技有限责任公司 | Remote configuration method of register, computer equipment and storage medium |
| CN115964333A (en) * | 2023-03-17 | 2023-04-14 | 之江实验室 | Communication method of multi-chip neural network algorithm based on FPGA (field programmable Gate array) master control |
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Application publication date: 20170531 |