CN106776372B - Emulation data access method and device based on FPGA - Google Patents
Emulation data access method and device based on FPGA Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/28—Using a specific disk cache architecture
- G06F2212/282—Partitioned cache
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Abstract
The invention discloses a kind of emulation data access method and device based on FPGA, this method comprises: establishing buffer state table, buffer state table is used to describe the state of each buffer area in memory, each in state table all records the state of a buffer area in corresponding memory；Subaddressing state table is established, the description information of data buffer zone under the subaddressing that each list item record emulator of subaddressing state table currently emulates；It receives the deposit of emulation data or extracts node address therein, subaddress information when reading application；Using node address, subaddress information as input parameter, subaddressing state table entry address is obtained through Hash compression mapping algorithm；Subaddressing state table is searched according to the entry address, obtains the record list item and buffer zone address of subaddressing, emulation data are stored in the corresponding buffer area of the buffer zone address or reads emulation data from the corresponding buffer area of the buffer zone address；Buffer state table and subaddressing state table list item information are updated after deposit or reading.The present invention greatly improved single emulator and support the number of nodes of parallel artificial, while also improve the service efficiency of memory.
Description
Technical field
The present invention relates to Bus simulator the field of test technology, and in particular to it is a kind of for high-speed bus emulator based on
The emulation data access method and device of FPGA.
Background technique
High-speed bus emulator is mainly used in avionics Bus simulator and test macro, develops for avionics system
Half associative simulation in kind is tested, matter emulation is tested etc. is carried out in journey.Avionics system is used in rugged environment, it is ensured that avionics system
The completeness for functions of the equipments of uniting and the reliability of performance are the core missions in avionics system development process.It is ground in avionics system
During system, need to carry out various l-G simulation tests on ground, to verify entire avionics system function, whether performance is up to standard.
With the development of avionics bus system, high speed avionics bus of new generation is in terms of supporting node quantity, communication bandwidth
It greatly improves, this also increases the design difficulty of high-speed bus emulator, and the storage management for emulating data is therein one
A Major Difficulties.
Summary of the invention
In order to solve the difficult point of the above-mentioned prior art, the invention proposes it is a kind of for high-speed bus emulator based on
The memory management method and device of FPGA.
According to an aspect of the invention, there is provided a kind of emulation data access method based on FPGA comprising following
Step:
S1: establishing buffer state table, and buffer state table is used to describe the state of each buffer area in memory, state
Each in table all records the state of a buffer area in corresponding memory；
S2: establishing subaddressing state table, each list item of subaddressing state table records emulator currently emulates one
The description information of data buffer zone under a subaddressing；
S3: receiving the deposit of emulation data or extracts node address therein, subaddress information when reading application；
S4: using node address, subaddress information as input parameter, subaddressing state is obtained through Hash compression mapping algorithm
Table entry address；
S5: subaddressing state table is searched according to the entry address, with obtaining record list item and the buffer area of subaddressing
Emulation data are stored in the corresponding buffer area of the buffer zone address or read from the corresponding buffer area of the buffer zone address by location
Emulate data；
S6: buffer state table and subaddressing state table list item information are updated after deposit or reading.
According to another aspect of the present invention, a kind of emulation data access device based on FPGA is provided comprising:
Buffer state table establishes module, describes the shape of each buffer area in memory for establishing buffer state table
State, each in state table all record the state of a buffer area in corresponding memory；
Subaddressing state table establishes module, for establishing subaddressing state table, each list item note of subaddressing state table
The description information of data buffer zone under the subaddressing that record emulator currently emulates；
Subaddressing state table entry address obtains module, for extracting when receiving the deposit of emulation data or reading application
Node address therein, subaddress information compress mapping through Hash and calculate using node address, subaddress information as input parameter
Method obtains subaddressing state table entry address；
Data access module is used to search subaddressing state table according to the entry address, obtains the record sheet of subaddressing
And buffer zone address, emulation data are stored in the corresponding buffer area of the buffer zone address or from the buffer zone address pair
Emulation data are read in the buffer area answered, and buffer state table and subaddressing state table list item are updated after deposit or reading
Information.
Compared with prior art, the present invention having the advantage that
Host computer is not involved in the memory management of emulation data, alleviates the burden of host computer, reduces upper computer software
Design difficulty improve efficiency the characteristics of work using each modular concurrent inside FPGA.
It can be emulated simultaneously using the access that the present invention carries out emulation data several hundred to thousands of a channels, list greatly improved
The number of nodes of one emulator support parallel artificial.
Using memory dice management, the scheme of dynamic allocation, compared to using fixed size Buffer allocation scheme
Improve the service efficiency of memory.
Detailed description of the invention
Fig. 1 shows the principle of the present invention schematic diagram.
Fig. 2 shows the list items of subaddressing state table of the invention to define schematic diagram.
Fig. 3 shows data buffer zone under subaddressing of the invention and manages schematic diagram.
Fig. 4 shows emulation data deposit flow chart of the invention.
Fig. 5 shows emulation reading data flow chart of the invention.
Specific embodiment
Emulation data storage and management method based on FPGA of the invention realizes multiple sections for high-speed bus emulator
Point emulates the management of data under each node when multiple subchannel parallel artificial functions.The source of emulation data includes but unlimited
In operating in general purpose computer, embedded computer, dsp processor, arm processor, power pc processor etc., with FPGA
Interface include but is not limited to PCIE, rapid io, AXI and customized interconnection etc., the memory used can be DRAM,
Block ram etc. in SRAM, FPGA.
Present invention is further described in detail with reference to the accompanying drawing.
Fig. 1 is the original of the emulation data storage and management method based on FPGA for high-speed bus emulator of the invention
Manage schematic diagram.
Wherein, storage space size is distributed according to practical application, it is desirable that is continuous memory space, memory is with fixation
The piecemeal of size is managed, and the size of piecemeal can be determined according to the agreement feature that high-speed bus emulator is realized, is led to
Often set according to bus protocol, it is general to require to be greater than the agreement maximum frame size, and require to be byte.Each piecemeal is used as one
A data buffer zone.
Buffer state table is established in fpga logic, is realized using Block ram resource inside FPGA.Buffer state
Table is used to describe the state of each piecemeal (buffer area) in memory, each in state table all records one in corresponding memory
The state of a buffer area.If the buffer area piecemeal is occupied, corresponding record position is 1, if otherwise the buffer area piecemeal is not occupied
With corresponding record position is 0.
It realizes that stand-by buffer area is inquired in fpga logic, needs acquisition one unappropriated slow first before new data deposit
Regional address is rushed, stand-by buffer area enquiry module inquires buffer state table in advance, obtains a certain number of stand-by buffer zone address
To be used in deposit inactive data buffer area table, such mode avoids each new data deposit and all removes inquiry buffer state
Table improves efficiency.
The corresponding buffer area of pointer in deposit inactive data buffer area table will record position in buffer state table to be set to
1, show that this buffer area is occupied.
After data buffer zone releases in the chained list of subaddressing buffer area, by the buffer area in buffer state table
Record position 0 shows that this buffer area has been recovered, available.
Present invention is mainly used for high speed data bus to emulate the more subchannels of multinode, such as in FC-AE-1553 bus protocol
Node address bit wide is 24bit, and subaddressing (subchannel) bit wide is 32bit.Bus simulator would generally emulate multiple simultaneously
Node, address of node with no restrictions, while can support multiple subaddressings under each node, the value of subaddressing is with no restrictions.It is imitative
When true need that a data buffer records will be established for each subaddressing under each node.
Subaddressing (subchannel) state table is established in fpga logic, is realized using Block ram resource inside FPGA, son
Each list item of address state table records the description information of data buffer zone under the subaddressing that emulator currently emulates,
Record information format as shown in Fig. 2, the depth of subaddressing state table determine emulator and meanwhile support emulate simulation node,
The quantity of subaddressing.
Mapping algorithm is compressed using Hash in fpga logic, due to node address and the spliced addressing space of subaddressing
It is far longer than the address space of subaddressing state table, direct mapping can not be established, therefore compression mapping is carried out using hash algorithm.
Node address and subaddressing splicing are obtained into the key of regular length by hash algorithm, using obtained key as the subaddressing number
According to storage address of the buffer description information in subaddressing state table, wherein the length of key should be with subaddressing state table
Depth is consistent.
The management to data buffer zone under each subaddressing (subchannel), buffer area under subaddressing are completed in fpga logic
Using one-dimensional chained list way to manage, schematic diagram is as shown in Figure 3.It is slow to record this in the corresponding subaddressing state list item of subaddressing
Rush under area head buffer zone address, tail buffer zone address, buffer area number etc. in data buffer zone.Each buffering in memory
Qu Zhongyou individual region stores next data buffer address pointer information in the chained list of buffer area.It compiles the data buffer zone newly applied
Enter chained list tail portion；After head buffer data use, discharges the buffer area and update a buffer zone address.
The deposit process for emulating data is as shown in Figure 4, the specific steps are as follows:
Step 1, node address, subaddress information are extracted after receiving downlink emulation data packet；
Step 2, with node address, subaddress information obtains subaddressing as input parameter, through Hash compression mapping algorithm
State table entry address；
Step 3, matched and searched is carried out in subaddressing state table, if finding occurrence, is carried out in next step；If not searching
To occurrence and the address it is unoccupied, then the record list item of this subaddressing is established in this address；If not finding occurrence
And the address is occupied, then calculates next entry address according to collision algorithm, then repeatedly step 3；
Step 4, a buffer zone address is obtained in stand-by buffer area table, and emulation data are stored in the data buffer zone；
If current no-buffer under this subaddressing, using this data buffer address as the head buffer zone address of buffer area chained list；It is no
Then, buffer area chained list tail portion is added in this buffer area, corresponding operation is to insert this in the specific description area of current tail buffer area
Buffer zone address, data length information；
Step 5, by the data buffer zone in buffer state table record position 1；
Step 6, subaddressing state table list item information, including head buffer zone address, head buffer data length are updated, tail delays
Regional address, buffer area number etc. are rushed, if wherein a certain information does not change and can not update.
The reading process of data is emulated as shown in figure 5, specific step is as follows:
Step 1, emulation reading data application is received, node address, subaddress information are extracted；
Step 2, with node address, subaddress information obtains subaddressing as input parameter, through Hash compression mapping algorithm
State table entry address；
Step 3, matched and searched is carried out in subaddressing state table, if finding occurrence, if subaddressing state table list item
The buffer area number of middle record is 0, then returns to error message, is otherwise carried out in next step；If not finding occurrence and the address
It is unoccupied, then error message is returned to, such situation shows not setting up buffer records under the subaddressing；If not finding matching
And the address it is occupied, then next entry address is calculated according to collision algorithm, then repeatedly step 3；
Step 4, head buffer zone address is obtained in subaddressing state list item, the information such as head buffer data length are read
The data of buffer area in corresponding external memory, while obtaining the address of next data buffer zone；
Step 5, the buffer area is discharged after the completion, and respective operations are to record the data buffer zone in buffer state table
Position 0.
Step 6, subaddressing state table list item information, including head buffer zone address, head buffer data length, buffering are updated
Area's number etc..
Emulation data storage and management method through the invention is, it can be achieved that multinode, more subaddressings (subchannel) emulate number
According to management, the node of support, the quantity of subaddressing mainly determines by the depth of subaddressing state table, Block ram in FPGA
Resource very abundant, it is different according to FPGA model, it can realize that several k to more than ten k depth, therefore can be realized several hundred to thousands of easily
The management of subaddressing.The buffer area under each subaddressing, which is realized, simultaneously dynamically distributes, and is finished and releases immediately, memory service efficiency
It is very high.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.It is deposited moreover, the present invention can be used to can be used in the computer that one or more wherein includes computer usable program code
The form for the computer program product implemented on storage media (including but not limited to magnetic disk storage and optical memory etc.).
The present invention be referring to according to the method for the embodiment of the present invention with the flowchart and/or the block diagram of computer program product
Come what is described.It should be understood that can be realized by computer program instructions each flow and/or block in flowchart and/or the block diagram,
And the combination of the process and/or box in flowchart and/or the block diagram.These computer program instructions be can provide to general meter
Calculation machine, special purpose computer, Embedded Processor or other programmable data processing devices processor to generate a machine, make
It obtains and is generated by the instruction that computer or the processor of other programmable data processing devices execute for realizing in flow chart one
The device for the function of being specified in a process or multiple processes and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.Obviously, those skilled in the art can carry out the present invention various
Modification and variation is without departing from the spirit and scope of the present invention.In this way, if these modifications and changes of the present invention belongs to this hair
Within the scope of bright claim and its equivalent technologies, then the present invention is also intended to include these modifications and variations.
Claims (14)
1. a kind of emulation data access method based on FPGA, which comprises the following steps:
S1: establishing buffer state table, and buffer state table is used to describe the state of each buffer area in memory, in state table
Each all record the state of a buffer area in corresponding memory；
S2: subaddressing state table, the son that each list item record emulator of subaddressing state table currently emulates are established
The description information of data buffer zone under address；
S3: receiving the deposit of emulation data or extracts node address therein, subaddress information when reading application；
S4: using node address, subaddress information as input parameter, show that subaddressing state table enters through Hash compression mapping algorithm
Port address；
S5: searching subaddressing state table according to the entry address, obtain the record list item and buffer zone address of subaddressing, will
Data are emulated to be stored in the corresponding buffer area of the buffer zone address or read emulation from the corresponding buffer area of the buffer zone address
Data；
S6: buffer state table and subaddressing state table list item information are updated after deposit or reading.
2. the emulation data access method based on FPGA as described in claim 1, which is characterized in that also wrapped before step S1
It includes step S0: memory is divided into the piecemeal of fixed size, the size of piecemeal is set greater than the agreement most according to bus protocol
Big frame length, and beByte, n are positive integer, regard each piecemeal as a data buffer zone.
3. the emulation data access method based on FPGA as described in claim 1, which is characterized in that if a certain buffer area piecemeal
Occupied, corresponding record position is set as 1 in the buffer state table, if the buffer area piecemeal on the contrary is unoccupied,
Corresponding record position is set as 0.
4. the emulation data access method based on FPGA as described in claim 1, which is characterized in that if step S3 receive be
Data deposit application is emulated, in step s 5, when matched and searched is carried out in subaddressing state table according to the entry address, if
Occurrence is not found and the entry address is unoccupied, then the record list item of this subaddressing is established in this address；If not looking into
It finds occurrence and the entry address is occupied, then next entry address is calculated according to collision algorithm, then repeatedly step S5.
5. the emulation data access method based on FPGA as described in claim 1, which is characterized in that if step S3 receive be
Reading data application is emulated, in step s 5, if the buffer area number recorded in the subaddressing record list item obtained is 0,
Then return to error message；If not finding occurrence and the entry address being unoccupied, error message is returned；If not finding
With item and the entry address it is occupied, then next entry address is calculated according to collision algorithm, then repeatedly step S5.
6. the emulation data access method based on FPGA as described in claim 1, which is characterized in that the subaddressing state table
List item information includes that node address, subaddressing, subaddressing status information, head buffer pointer, head buffer data length, tail are slow
Rush Qu Zhizhen, buffer area number.
7. the emulation data access method based on FPGA as described in claim 1, which is characterized in that inquire buffer area shape in advance
State table, obtains to be used in a certain number of stand-by buffer zone address deposit inactive data buffer area tables, is carrying out emulation data
A unappropriated buffer zone address is obtained when deposit directly from the table of inactive data buffer area.
8. a kind of emulation data access device based on FPGA characterized by comprising
Buffer state table establishes module, describes the state of each buffer area in memory for establishing buffer state table,
Each in state table all records the state of a buffer area in corresponding memory；
Subaddressing state table establishes module, and for establishing subaddressing state table, each list item record of subaddressing state table is imitative
The description information of data buffer zone under the subaddressing that true equipment currently emulates；
Subaddressing state table entry address obtains module, for extracting wherein when receiving the deposit of emulation data or reading application
Node address, subaddress information, using node address, subaddress information as input parameter, through Hash compression mapping algorithm obtain
Subaddressing state table entry address out；
Data access module, be used to according to the entry address search subaddressing state table, obtain the record list item of subaddressing with
And buffer zone address, data will be emulated and be stored in the corresponding buffer area of the buffer zone address or corresponding from the buffer zone address
Emulation data are read in buffer area, and buffer state table and subaddressing state table list item letter are updated after deposit or reading
Breath.
9. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that further include data buffer zone
Division module, for memory to be divided into the piecemeal of fixed size, the size of piecemeal is set greater than the association according to bus protocol
Maximum frame size is discussed, and isByte, n are positive integer, regard each piecemeal as a data buffer zone.
10. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that if a certain buffering is distinguished
Block is occupied, and corresponding record position is set as 1 in the buffer state table, if otherwise the buffer area piecemeal is not occupied
With corresponding record position is set as 0.
11. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that if what is received is emulation
Data deposit application, when data access module carries out matched and searched according to the entry address in subaddressing state table, if not
It finds occurrence and the entry address is unoccupied, then the record list item of this subaddressing is established in this address, if not searching
To occurrence and the entry address it is occupied, then next entry address is calculated according to collision algorithm, then re-use described in
Entry address carries out matched and searched in subaddressing state table.
12. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that if what is received is emulation
Reading data application, when data access module carries out matched and searched according to the entry address in subaddressing state table, if obtaining
The buffer area number recorded in the subaddressing record list item taken is 0, then returns to error message；If do not find occurrence and
The entry address is unoccupied, returns to error message；If not finding occurrence and the entry address being occupied, according to punching
Prominent algorithm calculates next entry address, then re-uses the entry address and carries out matched and searched in subaddressing state table.
13. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that the subaddressing state
Table list item information includes node address, subaddressing, subaddressing status information, head buffer pointer, head buffer data length, tail
Buffer pointer, buffer area number.
14. the emulation data access device based on FPGA as claimed in claim 8, which is characterized in that further include buffering for use
Area's enquiry module, for inquiring buffer state table, deposit inactive data is slow after obtaining a certain number of stand-by buffer zone address
Rush it is to be used in area's table, carry out emulation data deposit when directly from the table of inactive data buffer area obtain one it is unappropriated
Buffer zone address.
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| CN104133784A (en) * | 2014-07-24 | 2014-11-05 | 大唐移动通信设备有限公司 | Message buffer management method and message buffer management device |
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| US20120284501A1 (en) * | 2011-05-06 | 2012-11-08 | Xcelemor, Inc. | Computing system with hardware reconfiguration mechanism and method of operation thereof |
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| CN102629914A (en) * | 2012-04-27 | 2012-08-08 | 深圳市邦彦信息技术有限公司 | Method and device for buffering Ethernet data packets |
| CN104133784A (en) * | 2014-07-24 | 2014-11-05 | 大唐移动通信设备有限公司 | Message buffer management method and message buffer management device |
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