CN102629914A

CN102629914A - Method and device for buffering Ethernet data packets

Info

Publication number: CN102629914A
Application number: CN201210128718XA
Authority: CN
Inventors: 高胜; 封华明; 秦波
Original assignee: Shenzhen Bangyan Information Technology Co Ltd
Current assignee: Shenzhen Bangyan Information Technology Co Ltd
Priority date: 2012-04-27
Filing date: 2012-04-27
Publication date: 2012-08-08

Abstract

The invention discloses a method for buffering Ethernet data packets, comprising providing a DRAM to act as a cached entity, wherein the DRAM is divided into a plurality of memory blocks; controlling the DRAM through an FPGA controller, wherein the FPGA controller includes memory block state tables which maps correspondingly to start addresses of the memory blocks. The invention further discloses a device for buffering Ethernet data packets. The method for buffering Ethernet data packets provided by the invention divides the DRAM into a plurality of memory blocks, meets the requirement that storage of data packets does not span pages, and buffers the Ethernet data packets with a low processing latency, which achieves objectives of quick access, big storage capacity, and low implementation cost.

Description

A kind of Ethernet data bag caching method and device

Technical field

The present invention relates to the Ethernet data transmission field, be specifically related to a kind of Ethernet data bag way to play for time and device.

Background technology

Ethernet is present popular a kind of local area network technology, slowly is applied to metropolitan area network or core net high-speed transfer in recent years.Ethernet speed has experienced 10Mpbs, 100Mpbs, 1GMpbs, common up till now 10G Mpbs.Along with the popularization of packet transmission networks, the application of Ethernet will be more and more widely.

The lifting significantly of transmission rate is to transmission medium, and transmitting and receiving module and switching equipment etc. has all proposed very high requirement.In two-layer switching equipment, the route switching process has been passed through in the slave unit output again of Ethernet data bag access arrangement, in this process, need packet be carried out buffer memory, waits for switching engine result sense data bag from buffering area again.

Along with the raising of transmission rate, the requirement of the processing speed of switching equipment is also increasingly high, and general packet buffering method becomes the bottleneck that processing speed further promotes gradually.

Summary of the invention

In order to solve the technical problem of prior art, the invention provides a kind of Ethernet data bag way to play for time nuclear device of carrying out the access of Ethernet data bag with lower time-delay.

The technical scheme of technical solution problem of the present invention comprises: a kind of Ethernet data bag way to play for time comprises providing dynamic random access memory (DRAM) as buffer entity that said DRAM is divided into a plurality of memory blocks; Control said DRAM through the FPGA controller, said FPGA controller comprises and the corresponding memory block state table of said memory block initial address mapping.

The present invention also provides a kind of Ethernet data bag buffer unit; It comprises the FPGA controller; Said FPGA controller comprises arbitration modules, fifo module, internal memory recycling module, memory block state table, bit width conversion module and address mapping module, said bit width conversion module, and address mapping module; Be connected to the DRAM interface; And can read and write data to DRAM, and it is consistent with the bit wide of dram controller that said bit width conversion module is used for Ethernet data bag bit width conversion, said address mapping module is used for exporting the memory block of Ethernet data packet address to DRAM according to the instruction of arbitration modules; Said arbitration modules is used for control to memory block read/write Ethernet data bag; Said internal memory recycling module is used to reclaim the memory block of inefficacy, and said fifo module is used to store the memory block information that is recovered, and said memory block state table is used to store the address information of DRAM memory block.

Compared to prior art; The present invention combines characteristic and the Ethernet data bag characteristics of DRAM; DRAM is divided into a plurality of memory blocks, and Ethernet data bag storage do not stride page or leaf, with lower processing time-delay buffer memory Ethernet data bag; It is fast to have access speed, the big and low advantage of implementation cost of memory capacity.

Description of drawings

Fig. 1 is that the memory block of an embodiment of a kind of Ethernet data bag of the present invention way to play for time is divided sketch map;

Fig. 2 is the memory block STA representation intention of the said embodiment of Fig. 1;

Fig. 3 is memory block state table and the DRAM memory block initial address Mapping Examples of the said embodiment of Fig. 1;

Fig. 4 is the sketch map of an embodiment of a kind of Ethernet data bag of the present invention buffer unit.

Embodiment

Below in conjunction with accompanying drawing and embodiment the present invention is explained further details.

Among the embodiment of a kind of Ethernet data way to play for time of the present invention; With dynamic random access memory (DRAM; Dynamic Random Access Memory) as storage medium; Said DRAM is divided into the individual memory block of N (N is a natural number), and each memory block size is 2048 bytes, and each memory block can only be put an Ethernet data bag.Because the maximum bag length of Ethernet data bag is 1518 bytes, so memory block always has unfilled byte.Every row on the DRAM bit array is counted as one page, and in order to reduce the indegree of writing of row address, memory block is divided can not stride page or leaf, writes or read an Ethernet data bag at every turn like this, only needs to transmit a row address, to reduce the processing time-delay of read-write DRAM.

Use FPGA to realize control among the embodiment according to the invention, comprise read-write control and management DRAM to DRAM.Wherein, FPGA is included in the memory block state table in the inner RAM foundation; Management through to the memory block state table realizes the block management data to DRAM, because FPGA reading and writing internal RAM only needs a clock cycle, so the loss of time that can avoid direct control DRAM to bring.

Seeing also Fig. 1, is the division sketch map of the internal storage data piece of one embodiment of the invention.According to the bit wide of DRAM, can learn the initial address N of each data block, need satisfy each data block is 2048 bytes (byte), each byte length 8 bit (bit), N satisfies following formula:

DRAM capacity=N * 2048 * 8 (bits) (1)

Seeing also Fig. 2, is the sketch map of memory block state table.In the table each parameter corresponding the management information of a memory block.Finite data length in position [10:0] the expression memory block, the just length of Ethernet data bag.Expression life span in position [14:11] in Ethernet data bag write memory piece, is then set life span, whenever reads a memory block life span and subtracts 1, and when life span was 0, the data in the memory block will be regarded as inefficacy.Position 15 expression memory blocks reclaim state, when being 1, represent to be recovered, and 0 expression is not recovered.

Seeing also Fig. 3, is memory block state table and DRAM memory block initial address mapping sketch map.The initial address of the address of memory block state table and DRAM memory block exists fixing mapping relations, and concrete mapping relations are then relevant with the bit wide of DRAM.

As to use bit wide be 8 DRAM, then can push away by equality (1):

Memory block initial address=memory block state list item address * 2048 (2)

As to use bit wide be 16 DRAM, then can push away by equality (1):

Memory block initial address=memory block state list item address * 1024 (3)

Among the present invention, the memory block that had lost efficacy need be recovered.Life span in the memory block state table is a certain is 0, and reclaims and be masked as 0, and then identifying this memory block can be recovered, and by the address that the outside internal memory recycling module of memory block state table reads this list item, will reclaim sign afterwards and be rewritten as 1, accomplishes recovery.

With reference to figure 4; The block diagram of an embodiment of a kind of Ethernet data bag of the present invention buffer unit; Comprise the FPGA controller; Said FPGA controller comprises arbitration modules 10, first in first out (FIFO, First-In First-Out) module 20, internal memory recycling module 30, memory block state table 40, bit width conversion module 50 and address mapping module 60.Said bit width conversion module 50 is connected to the DRAM interface with address mapping module 60, and reads and write data to DRAM.Said bit width conversion module 50 is used for converting into the bit wide of dram controller Ethernet data bag bit wide (8) consistent.Said address mapping module 60 is used for exporting the memory block of Ethernet data packet address to DRAM according to the instruction of arbitration modules 10.Said arbitration modules 10 is used for control to memory block read/write Ethernet data bag.Said internal memory recycling module 30 is used to reclaim the memory block of inefficacy.Said fifo module 20 is used to store the memory block information that is recovered, as is recovered memory block corresponding address in memory block state table 40.Said internal memory recycling module 30 poll memory block state tables 40; As finding memory block untapped and that do not reclaim is arranged; Then said untapped and memory block corresponding address in memory block state table 40 that do not reclaim is imported said fifo module, and the recovery sign of said memory block is put 1.Said memory block state table 40 is used to store the address information of DRAM memory block.For example, in one embodiment of the invention, the memory block that address 0x9 is corresponding in the memory block state table is recovered, and so just 0x9 is write FIFO, if FIFO is empty before this, 0x9 just has been placed on the foremost of FIFO so.

Write data as port request to memory block; Select through arbitration modules 10 with regard to needs; Write request instruction when this port sends to arbitration modules 10, arbitration modules 10 is read free memory block number 0x9 (address of memory block state table just) from FIFO.Arbitration modules feeds back to the request end with 0x9, and sends the signal of response request, can write data to memory block, and the request port need be noted the memory block numbering of feedback, so that read the data of memory block afterwards.

Afterwards 0x9 is mapped as the base address of memory block, the bit wide of supposing DRAM is 16, and then according to formula (3), the base address that counts out is 0x2400.At this moment the Ethernet data bag of arbitration modules 10 beginning receiving ports, and the length of record data bag in the write memory bulk state table, writes life span simultaneously.Because Ethernet data bag transmit port is 8, and dram controller interface bit wide is decided by selected DRAM, so need do bit width conversion.

, need equally to weigh selection from the memory block reading of data as port request,, utilize the memory block numbering of writing fashionable feedback to carry out data and read when this port gets access to arbitration through arbitration modules.Memory block as obtaining in the above-mentioned example is numbered 0x9, then imports numbering into arbitration modules, is transferred to address mapping module again, begins to obtain the Ethernet data bag of memory block, then life span corresponding in the memory block table is subtracted 1 after completion is read.

As stated, said FPGA controller has just been accomplished the operation of the write and read of one whole to DRAM.In the above embodiment of the present invention, the type of said DRAM can be SDRAM, DDR SDRAM, DDR2 SDRAM or DDR3 SDRAM.

Compared to prior art, the present invention is divided into a plurality of memory blocks with DRAM, and satisfies the packet storage and do not stride page or leaf, and with lower processing time-delay buffer memory Ethernet data bag, it is fast to reach access speed, the big and low purpose of implementation cost of memory capacity.

Above execution mode is only in order to explaining technical scheme of the present invention, but not to its restriction; Although the present invention has been carried out detailed explanation with reference to aforementioned embodiments; Those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned embodiments is put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these are revised or replacement, do not make the spirit and the scope of each execution mode technical scheme of essence disengaging the present invention of relevant art scheme.

Claims

1. Ethernet data bag way to play for time comprises:

Provide dynamic random access memory (DRAM) as buffer entity, said DRAM is divided into a plurality of memory blocks;

Control said DRAM through the FPGA controller, said FPGA controller comprises and the corresponding memory block state table of said memory block initial address mapping.

2. Ethernet data bag way to play for time according to claim 1 is characterized in that each memory block size is 2048 bytes.

3. Ethernet data bag way to play for time according to claim 2 is characterized in that said each memory block is used to store an Ethernet bag.

4. Ethernet data bag way to play for time according to claim 3 is characterized in that, page or leaf is not striden in the storage/access of each Ethernet data bag.

5. Ethernet data bag way to play for time according to claim 2 is characterized in that said FPGA controller also comprises the internal memory recycling module, and said internal memory recycling module is used to reclaim the memory block of inefficacy.

6. Ethernet data bag way to play for time according to claim 4; It is characterized in that the life span in a certain item of memory block state table is 0, and recovery is masked as 0; Then identifying this memory block can be recovered; By the address that the outside internal memory recycling module of memory block state table reads this list item, will reclaim sign afterwards and be rewritten as 1, accomplish and reclaim.

7. Ethernet data bag way to play for time according to claim 4 is characterized in that said FPGA controller also comprises arbitration modules, and said arbitration modules is used for control to memory block read/write Ethernet data bag.

8. Ethernet data bag way to play for time according to claim 4 is characterized in that the capacity that said DRAM is every page is not less than 2048 bytes, and the type of said DRAM can be SDRAM, DDR SDRAM, DDR2SDRAM or DDR3SDRAM.

9. Ethernet data bag buffer unit; It is characterized in that, comprise the FPGA controller, said FPGA controller comprises arbitration modules, fifo module, internal memory recycling module, memory block state table, bit width conversion module and address mapping module; Said bit width conversion module; And address mapping module, be connected to the DRAM interface, and can read and write data to DRAM; Said bit width conversion module is used for Ethernet data bag bit width conversion for consistent with the bit wide of dram controller; Said address mapping module is used for exporting the memory block of Ethernet data packet address to DRAM according to the instruction of arbitration modules, and said arbitration modules is used for control to memory block read/write Ethernet data bag, and said internal memory recycling module is used to reclaim the memory block of inefficacy; Said fifo module is used to store the memory block information that is recovered, and said memory block state table is used to store the address information of DRAM memory block.