CN102541769B - Memory interface access control method and device - Google Patents

Memory interface access control method and device Download PDF

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CN102541769B
CN102541769B CN201010586872.2A CN201010586872A CN102541769B CN 102541769 B CN102541769 B CN 102541769B CN 201010586872 A CN201010586872 A CN 201010586872A CN 102541769 B CN102541769 B CN 102541769B
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write command
read write
instruction queue
storer
address
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CN102541769A (en
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黄科
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ZTE Corp
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ZTE Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller

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Abstract

The invention discloses a memory interface access control method and device. The device comprises an address controller, an instruction queue and an instruction queue scanner which are sequentially connected, wherein the address controller is connected with a data storage application layer, the instruction queue scanner is connected with an interface controller of a memory, the address controller is used for respectively mapping an instruction sent by the data storage application layer into different spaces of the memory and sending read write instructions of different spaces into corresponding instruction queues; each instruction queue is used for caching received read write instructions; and the queue scanner is used for sequentially reading the read write instructions from each instruction queue and sending the read write instructions into the interface controller of the memory. By adopting the memory interface access control method and device disclosed by the invention, throughput width of a DDRX (discontinuous dynamic recrystallization) memory can be effectively improved, the same effect can be realized on a read operation and a write operation, and access efficiency of the memory can be improved, thus overall performance of equipment is enhanced.

Description

A kind of memory interface access control method and device
Technical field
The present invention relates to DDR (Double Data Rate, Double Data Rate synchronous DRAM) technical field, more specifically, relate to a kind of memory interface access method and device.
Background technology
DDRX type memory is used widely in various communication facilitiess, comprise that DDR, DDRII and DDRIII etc. adopt the data bus storer of Double Data Rate, with respect to SSRAM (Synchronous Static Random Access Memory, synchronous static RAM), with unit storage density large (individual particle can reach 1Gbit), interface rate high (reaching as high as 1.333Ghz), cost is low, etc. advantage, become one of most important device in storer.
In order to realize above-mentioned all excellent specific properties, in the design of device, also must need to pay a lot of costs.For realizing the more index of large storage capacity of monolithic, need to adopt as far as possible transistor (the each storage unit of SSRAM at least needs six transistors) still less in each storage unit, but also make the complicacy of access control circuit improve simultaneously.For improving interface rate, need to adopt higher pre-access multiple.Because individual particle address space improves, for reducing the quantity of address pins, external address addressing all adopts ranks addressing mode, and addressed command is decomposed to two steps and complete, etc.These technology make the read and write access interface of storer increasingly sophisticated, and instruction bandwidth ratio is also along with improve.
DDRX memory interface speed has been brought up to the GHz order of magnitude, but actual interface access bandwidth but can not reach very high utilization factor.Fig. 1 shows a typical DDRX interface read and write access sequential chart, and main operation steps comprises: power-up initializing, mode register loading, Active (activation), Write (writing), Read (reading), Precharge (precharge), Refresh (refreshing) etc.Power-up initializing and mode register are only carried out once when Power up (powering on), little to effectiveness affects.Therefore, the unit access of storage is mainly launched round Active, Write, Read, Precharge, these orders of Refresh.Taking DDR device as example, Burst (burst) length is 8 o'clock, effective bandwidth 44%, and Burst length is 4 o'clock, and it is 2 o'clock that effective bandwidth drops to 22%, Burst length, and effective bandwidth drops to 11%.Certainly, if make the read/write address all the time can both continued operation, readwrite bandwidth theory can reach 99%, but this only limits to the theoretical value of device, and to distribute be random to read/write address in actual applications.Except necessary overhead operations, DDRX accessing time sequence also has some restrictions, and taking DDR device as example, the major parameter relating to is as shown in table 1 below.
Table 1
Wherein the main parameter that affects performance is tRC (being the time interval of Active to Active), and when Burst length is that 8, one secondary burst read-write length are 9tCK (tCK refers to the clock period), tRC does not also become restriction bottleneck.And in the time that Burst length is 2, a secondary burst read-write length is 6tCK, now need to increase by 3 NOP (sky) operation, could meet tRC requirement, this further reduces valid data throughput.
In actual DDR reservoir designs, for improving the interface bandwidth type of device that adopt 32 bit wides more, be that 2 one secondary bursts can 8 byte content of access at Burst, in the shorter application of some data table items, adopt higher Burst length to there is no benefit to raising the efficiency.Thus, under existing application scenario, DDRX effective bandwidth is very low, the no matter interface of many two-forties, and bandwidth resources practical efficiency only has 1/10th left and right.
Summary of the invention
The technical matters that the present invention solves is to provide a kind of memory interface access control method and device, improves the access efficiency of DDR storer, effectively improves bandwidth of memory utilization factor.
For solving the problems of the technologies described above, the invention provides a kind of memory access interface control device, described device comprises successively and to be connected: address control unit, instruction queue and instruction queue scanner, wherein, described address control unit is connected with data-storage applications layer, described instruction queue scanner is connected with the interface controller of described storer
Described address control unit is used for, and the instruction that described data-storage applications layer is sent is mapped to respectively the different spaces of storer, and the read write command of different spaces is sent in corresponding instruction queue;
Instruction queue is used for, the read write command that buffer memory is received;
Queue scanner is used for, and reads read write command successively from described each instruction queue, sends to the interface controller of described storer.
Further, described address control unit is used for, and according to the data-storage applications layer reference address in described read write command, the address of described read write command is mapped in the corresponding space of described storer.
Further, the number of the number of described instruction queue and the sheet of described storer (BANK) is identical.
Further, described address control unit is used for, and in such a way described read write command is mapped in the different spaces of described storer:
If the address addressing space size of data-storage applications layer is M, the space size of storer is P, and the BANK number of storer is N, and data-storage applications layer reference address m reference address m ' after conversion after mapping is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round[x] be rounding operation.
Further, described queue scanner is used for, scan successively each instruction queue, if present instruction queue is not empty, from present instruction queue, read in the buffer that a read write command deposits described queue scanner inside in, if present instruction queue is empty, scan next instruction queue;
If after 2 times or 2 times all instruction queues scan above, judge and only have an instruction queue all the time not for empty, and it is empty that other instruction queues are always, increase the number that at every turn reads read write command from instruction queue, the read write command continuous address of reading is merged into a read write command, and adjust burst (Burst) parameter of read write command.
The present invention also provides a kind of memory interface access control method, and described method comprises:
The read write command that data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
Read read write command from each space of described storer successively, send in the interface controller of described storer.
Further, in the different spaces that described read write command is mapped to described storer after, described method also comprises:
The read write command of the different spaces of described storer is sent to respectively in corresponding instruction queue, and the number of wherein said instruction queue is identical with the number of the BANK of described storer;
From described each instruction queue, read read write command successively, send to the interface controller of described storer.
Further, according to the data-storage applications layer reference address in described read write command, the address of described read write command is mapped in the corresponding space of described storer.
Further, in such a way described read write command is mapped in the different spaces of described storer:
If the address addressing space size of data-storage applications layer is M, the space size of storer is P, and the BANK number of storer is N, and data-storage applications layer reference address m reference address m ' after conversion after mapping is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round[x] be rounding operation.
Further, in the time reading read write command successively from described each instruction queue, scan successively each instruction queue, if present instruction queue is not empty, from present instruction queue, reading a read write command deposits in internal buffer, if present instruction queue is empty, scan next instruction queue;
If after 2 times or 2 times all instruction queues scan above, judge and only have an instruction queue all the time not for empty, and it is empty that other instruction queues are always, increase the number that at every turn reads read write command from instruction queue, the read write command continuous address of reading is merged into a read write command, and adjust the Burst parameter of read write command.
Compared with prior art, the present invention can effectively improve the bandwidth of handling up of DDRX storer, and all can reach effect same to read operation and write operation, and has improved the access efficiency of storer, thus the overall performance of lifting means.
Brief description of the drawings
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms the application's a part, and schematic description and description of the present invention is used for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the DDR access interface sequential schematic diagram that comprises read-write;
Fig. 2 is the composition schematic diagram of the memory interface access control apparatus of the embodiment of the present invention;
Fig. 3 is the algorithm schematic diagram of the queue scanner of the embodiment of the present invention;
Fig. 4 realizes DDR2 memory access interface schematic diagram according to the embodiment of the present invention;
Fig. 5 is the DDR access interface schematic diagram of continuous read operation while not adopting the present invention program;
Fig. 6 is the DDR access interface schematic diagram of continuous read operation after employing the present invention program.
Embodiment
Basic thought of the present invention is, utilize the tRRD of DDRX device less, generally only have the characteristic of 2 tCK, the address space random read-write sequence of operation to DDRX is converted to the access process of control, adjacent read-write operation is distributed on different BANK (sheet).Like this, make random read-write operation, be converted to orderly, controllable operation, thereby effectively improved bandwidth availability ratio.
Based on above-mentioned thought, the invention provides a kind of memory interface access control method, specifically adopt following technical scheme:
The instruction that data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
From each space reading command of described storer, send in the interface controller of described storer successively.
Wherein, described instruction comprises and reads instruction or write command.
Wherein, according to the data-storage applications layer reference address in described read write command, the address of described read write command is mapped in the corresponding space of described storer.
Further, in the different spaces that described read write command is mapped to described storer after, described method also comprises:
The read write command of the different spaces of described storer is sent to respectively in corresponding instruction queue, and the number of wherein said instruction queue is identical with the number of the BANK of described storer;
From described each instruction queue, read read write command successively, send to the interface controller of described storer.
Further, can in such a way described read write command be mapped in the different spaces of described storer:
If the address addressing space size of data-storage applications layer is M, the space size of storer is P, and the BANK number of storer is N, and data-storage applications layer reference address m reference address m ' after conversion after mapping is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round[x] be rounding operation.
For the ease of setting forth the present invention, below with reference to drawings and the specific embodiments, the enforcement of technical solution of the present invention is described in further detail.It should be noted that, in the situation that not conflicting, the combination in any mutually of the feature in embodiment and embodiment in the application.
Embodiment mono-
The memory interface access control apparatus that the embodiment of the present invention provides is located between data-storage applications layer and DDRX interface controller, read write command is sent as required from data-storage applications layer, and the control of DDRX interface is converted to read write command the access interface of DDRX.After the read write command of data storage application layer being sent by apparatus of the present invention is processed, then read write command after treatment is sent to DDRX interface controller.
As shown in Figure 2, the memory interface access control apparatus of the embodiment of the present invention mainly comprises three parts: address control unit, instruction queue and queue scanner.
Remap in address in the read write command that address control unit is mainly used in data-storage applications layer to send.Concrete mapping method can be according to following steps:
The address addressing space size of tentation data storage application layer is M, and the space size of DDRX device is P, and the BANK number of DDRX device is N.
By address addressing space: be mapped to device space:
By address addressing space: be mapped to device space:
……
By address addressing space: be mapped to device space:
Address control unit completes after the mapping of address, and the read write command of different address spaces is sent in corresponding instruction queue.
In the present embodiment, as shown in Figure 2, have 4 instruction queues: space interior read write command sends in instruction queue 1, space interior read write command sends in instruction queue 2, space interior read write command sends in instruction queue 3, space interior read write command sends in instruction queue 4.
The input of instruction queue is connected to the output of address control unit, and the quantity setting of instruction queue is relevant with DDRX type of device, for example can be identical with the BANK quantity of DDRX device.Scheduling is waited in the instruction first in first out cushioning in queue.
Queue scanner scans each instruction queue (hereinafter also referred to as queue) successively according to timeticks, if queue does not deposit in the buffer of scanner inside for sky just reads an instruction from the output of queue, if being sky, queue just scans next queue.
Preferably, if through after 2 times or above whole queue scanning, judge and only have a queue all the time not for empty, and other queues are always empty, increase and read read write command number in queue at every turn, and read or write command is merged into a read write command continuous address, adjust Burst length, re-send to the processing of DDRX interface controller.
Fig. 3 shows the concrete operations flow process of embodiment of the present invention squadron column scan device, and as shown in Figure 3, this flow process is described below:
Step 1, scan instruction queue;
Step 2, whether decision instruction queue is empty, empty if, moves to next instruction queue and scans; If be not empty, continue next step;
Step 3 is taken out an instruction from current queue;
Step 4, judges whether, after continuous 2 whole queue scannings, to only have current queue not for empty, if so, performs step 5, otherwise, from current queue, take out after an instruction, move to next instruction queue to scan;
Step 5, increases and once takes out the number parameter k of instruction, and the continuous instruction folding in address in this k bar read write command is become to an instruction.
Embodiment bis-
An embodiment of this patent is described as an example of DDRII device example shown in Fig. 4.Memory access by application layer is initiated read-write requests by three groups of signals, comprising: the write command signal of wr_en, cmd, wr_data, wr_addr composition; The read command signal of rd_en, cmd, rd_addr composition; The read data effective index signal of rd_data, data_valid composition.Wherein write command signal and read command signal, through corresponding wr_cmd_fifo and rd_cmd_fifo, are dredged the visit order stream of application layer, are convenient to instruction control unit and dispatch.
Need to shine upon processing through cmd_fifo reference address after treatment, its effect is that address table in application layer is mapped in the different B ANK in DDRII storer, makes the data uniform mapping of access in 8 different BANK.The synthetic visit order field of address after mapping and corresponding command group, imports respectively for No. ANK according to different B in 1～8 instruction queue, is used for distinguishing output for unique serial number of every read access command field distribution simultaneously.
Instruction field is taken out successively in 8 queues successively according to instruction execution cycle in access instruction buffer zone from wr_cmd_fifo and rd_cmd_fifo, wherein for reading, instruction need to according to the order of taking out, to increase a sequence number painted again, finally instruction is pressed into and in buffer zone, treats that ddr interface controller processes, be converted to the access interface sequential of DDRII device.
The data of reading from DDRII device, except output data useful signal data_valid, also need to go painted processing according to painted sequence number, make it data output and meet the order that order is initiated.
Adopt design proposal of the present invention, can effectively improve effective access bandwidth of DDRX storer, as shown in Figure 5, the access interface that does not adopt the present invention to design, reading 8 data needs 18 tCK; As shown in Figure 6, adopt the access interface of the present invention's design, reading 8 data only needs 9 tCK.Visible employing the present invention program's the more original scheme of effective access bandwidth improves 50%, and effect is remarkable.
These are only preferred case study on implementation of the present invention; be not limited to the present invention; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art can make according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Obviously, those skilled in the art should be understood that, above-mentioned of the present invention each module or each step can realize with general calculation element, they can concentrate on single calculation element, or be distributed on the network that multiple calculation elements form, alternatively, they can be realized with the executable program code of calculation element, thereby, they can be stored in memory storage and be carried out by calculation element, and in some cases, can carry out shown or described step with the order being different from herein, or they are made into respectively to each integrated circuit modules, or the multiple modules in them or step are made into single integrated circuit module to be realized.The present invention is not restricted to any specific hardware and software combination.

Claims (8)

1. a memory access interface control device, it is characterized in that, described device comprises successively and to be connected: address control unit, instruction queue and instruction queue scanner, wherein, described address control unit is connected with data-storage applications layer, described instruction queue scanner is connected with the interface controller of described storer
Described address control unit is used for, and the instruction that described data-storage applications layer is sent is mapped to respectively the different spaces of storer, and the read write command of different spaces is sent in corresponding instruction queue;
Instruction queue is used for, the read write command that buffer memory is received;
Queue scanner is used for, and reads read write command successively from described each instruction queue, sends to the interface controller of described storer;
Described address control unit is used for, and in such a way described read write command is mapped in the different spaces of described storer:
If the address addressing space size of data-storage applications layer is M, the space size of storer is P, and the BANK number of storer is N, and data-storage applications layer reference address m reference address m ' after conversion after mapping is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round[x] be rounding operation.
2. device as claimed in claim 1, is characterized in that,
Described address control unit is used for, and according to the data-storage applications layer reference address in described read write command, the address of described read write command is mapped in the corresponding space of described storer.
3. device as claimed in claim 1 or 2, is characterized in that,
The number of described instruction queue is identical with the number of the sheet of described storer (BANK).
4. device as claimed in claim 1 or 2, is characterized in that,
Described queue scanner is used for, scan successively each instruction queue, if present instruction queue is not empty, from present instruction queue, read in the buffer that a read write command deposits described queue scanner inside in, if present instruction queue is empty, scan next instruction queue;
If after 2 times or 2 times all instruction queues scan above, judge and only have an instruction queue all the time not for empty, and it is empty that other instruction queues are always, increase the number that at every turn reads read write command from instruction queue, the read write command continuous address of reading is merged into a read write command, and adjust burst (Burst) parameter of read write command.
5. a memory interface access control method, is characterized in that, described method comprises:
The read write command that data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
Read read write command from each space of described storer successively, send in the interface controller of described storer;
In such a way described read write command is mapped in the different spaces of described storer:
If the address addressing space size of data-storage applications layer is M, the space size of storer is P, and the BANK number of storer is N, and data-storage applications layer reference address m reference address m ' after conversion after mapping is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round[x] be rounding operation.
6. method as claimed in claim 5, is characterized in that, in the different spaces that described read write command is mapped to described storer after, described method also comprises:
The read write command of the different spaces of described storer is sent to respectively in corresponding instruction queue, and the number of wherein said instruction queue is identical with the number of the BANK of described storer;
From described each instruction queue, read read write command successively, send to the interface controller of described storer.
7. the method as described in claim 5 or 6, is characterized in that,
According to the data-storage applications layer reference address in described read write command, the address of described read write command is mapped in the corresponding space of described storer.
8. method as claimed in claim 6, is characterized in that,
In the time reading read write command successively from described each instruction queue, scan successively each instruction queue, if present instruction queue is not empty, from present instruction queue, reads a read write command and deposit in internal buffer, if present instruction queue is empty, scan next instruction queue;
If after 2 times or 2 times all instruction queues scan above, judge and only have an instruction queue all the time not for empty, and it is empty that other instruction queues are always, increase the number that at every turn reads read write command from instruction queue, the read write command continuous address of reading is merged into a read write command, and adjust the Burst parameter of read write command.
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Publication number Priority date Publication date Assignee Title
CN102819506B (en) * 2012-08-03 2015-06-10 中国人民解放军国防科学技术大学 Monitoring answer processing method on basis of double correlation chains
CN104346285B (en) * 2013-08-06 2018-05-11 华为技术有限公司 Internal storage access processing method, apparatus and system
CN104461956B (en) * 2013-09-18 2017-10-24 华为技术有限公司 The method of access synchronized dynamic RAM, apparatus and system
CN105045722B (en) * 2015-08-26 2018-06-05 东南大学 A kind of DDR2-SDRAM controllers and its low latency optimization method
CN112035056B (en) * 2020-07-09 2022-11-29 苏州浪潮智能科技有限公司 Parallel RAM access equipment and access method based on multiple computing units
CN114281247B (en) * 2021-11-29 2022-10-14 深圳三地一芯电子有限责任公司 Flash bandwidth allocation method and device based on mixed media

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101340365A (en) * 2008-08-11 2009-01-07 杭州瑞纳科技有限公司 Design method of DDR2 SDRAM controller of high bandwidth utilization
CN101840374A (en) * 2010-04-28 2010-09-22 福建星网锐捷网络有限公司 Processing device, information searching system and information searching method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
US6938133B2 (en) * 2001-09-28 2005-08-30 Hewlett-Packard Development Company, L.P. Memory latency and bandwidth optimizations
US7698498B2 (en) * 2005-12-29 2010-04-13 Intel Corporation Memory controller with bank sorting and scheduling
CN101192195B (en) * 2006-11-22 2011-08-03 北京华旗资讯数码科技有限公司 Packet management method for electronic hard disk memory space
CN101576853B (en) * 2008-05-06 2011-12-21 群联电子股份有限公司 Data access method and controller and memory system using same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101340365A (en) * 2008-08-11 2009-01-07 杭州瑞纳科技有限公司 Design method of DDR2 SDRAM controller of high bandwidth utilization
CN101840374A (en) * 2010-04-28 2010-09-22 福建星网锐捷网络有限公司 Processing device, information searching system and information searching method

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