CN102541769A - Memory interface access control method and device - Google Patents

Memory interface access control method and device Download PDF

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CN102541769A
CN102541769A CN2010105868722A CN201010586872A CN102541769A CN 102541769 A CN102541769 A CN 102541769A CN 2010105868722 A CN2010105868722 A CN 2010105868722A CN 201010586872 A CN201010586872 A CN 201010586872A CN 102541769 A CN102541769 A CN 102541769A
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write command
read write
storer
instruction
instruction queue
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CN102541769B (en
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黄科
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ZTE Corp
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    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Abstract

The invention discloses a memory interface access control method and device. The device comprises an address controller, an instruction queue and an instruction queue scanner which are sequentially connected, wherein the address controller is connected with a data storage application layer, the instruction queue scanner is connected with an interface controller of a memory, the address controller is used for respectively mapping an instruction sent by the data storage application layer into different spaces of the memory and sending read write instructions of different spaces into corresponding instruction queues; each instruction queue is used for caching received read write instructions; and the queue scanner is used for sequentially reading the read write instructions from each instruction queue and sending the read write instructions into the interface controller of the memory. By adopting the memory interface access control method and device disclosed by the invention, throughput width of a DDRX (discontinuous dynamic recrystallization) memory can be effectively improved, the same effect can be realized on a read operation and a write operation, and access efficiency of the memory can be improved, thus overall performance of equipment is enhanced.

Description

A kind of memory interface access control method and device
Technical field
The present invention relates to DDR (Double Data Rate, Double Data Rate synchronous DRAM) technical field, more specifically, relate to a kind of memory interface access method and device.
Background technology
The DDRX type memory is used widely in various communication facilitiess, comprises that DDR, DDRII and DDRIII etc. adopt the data bus storer of Double Data Rate, with respect to SSRAM (Synchronous Static Random Access Memory; Synchronous static RAM); With unit storage density big (individual particle can reach 1Gbit), interface rate high (reaching as high as 1.333Ghz), cost is low; Etc. advantage, become one of most important device in the storer.
In order to realize above-mentioned all excellent specific properties, in the design of device, also must pay a lot of costs.For realizing the more index of large storage capacity of monolithic, need adopt transistor (each storage unit of SSRAM needs six transistors at least) still less as far as possible in each storage unit, but also make the complicacy of access control circuit improve simultaneously.For improving interface rate, then need adopt higher prestoring to get multiple.Because the individual particle address space improves, for reducing the quantity of address pins, the ranks addressing mode is all adopted in the external address addressing, addressed command was decomposed for two steps accomplish, or the like.These technology make that the read and write access interface of storer is increasingly sophisticated, and instruction bandwidth ratio is also along with improve.
DDRX memory interface speed has been brought up to the GHz order of magnitude, but the actual interface access bandwidth but can not reach very high utilization factor.Fig. 1 shows a typical DDRX interface read and write access sequential chart, and main operation steps comprises: power-up initializing, mode register loading, Active (activation), Write (writing), Read (reading), Precharge (precharge), Refresh (refreshing) etc.Power-up initializing and mode register are only carried out once when Power up (powering on), and be little to effectiveness affects.Therefore, the unit access of storage is mainly launched round Active, Write, Read, Precharge, these several orders of Refresh.With the DDR device is example, and Burst (burst) length is 8 o'clock, effective bandwidth 44%, and Burst length is 4 o'clock, and effective bandwidth drops to 22%, and Burst length is 2 o'clock, and effective bandwidth drops to 11%.Certainly, if make the read/write address all the time can both continued operation, the readwrite bandwidth theory can reach 99%, but this only limits to the theoretical value of device, and read/write address distributes and is at random in practical application.Except necessary overhead operations, the DDRX accessing time sequence also has some restrictions, is example with the DDR device, and the major parameter that relates to is as shown in table 1 below.
Table 1
Figure BDA0000037883690000021
The wherein main parameter that influences performance is tRC (being the time interval of Active to Active), and when Burst length is 8, once burst read-write length is 9tCK (tCK refers to the clock period), and tRC does not also become the restriction bottleneck.And when Burst length was 2, once burst read-write length was 6tCK, and needing this moment increases by 3 NOP (sky) operation, could satisfy the tRC requirement, and this makes the valid data throughput further reduce.
In the DDR of reality reservoir designs; For improving the interface bandwidth type of device that adopt 32 bit wides more; At Burst is that 2 one secondary bursts can 8 byte content of access, in the short application of some data table items, adopts higher Burst length not have benefit to raising the efficiency.Thus, under the existing application occasion, DDRX effective bandwidth is very low, the interface of many two-forties no matter, and the bandwidth resources practical efficiency has only about 1/10th.
Summary of the invention
The technical matters that the present invention solves provides a kind of memory interface access control method and device, improves the access efficiency of DDR storer, effectively improves the bandwidth of memory utilization factor.
For solving the problems of the technologies described above; The invention provides a kind of memory access interface control device; Said device comprises continuous successively: address control unit, instruction queue and instruction queue scanner, and wherein, said address control unit links to each other with the data-storage applications layer; Said instruction queue scanner links to each other with the interface controller of said storer
Said address control unit is used for, and the instruction that said data-storage applications layer is sent is mapped to the different spaces of storer respectively, and the read write command of different spaces is sent in the corresponding instruction formation;
Instruction queue is used for, the read write command that buffer memory is received;
The formation scanner is used for, and from said each instruction queue, reads read write command successively, sends to the interface controller of said storer.
Further, said address control unit is used for, according to the data-storage applications layer reference address in the said read write command, with the map addresses of said read write command in the additional space of said storer.
Further, the number of said instruction queue is identical with the number of the sheet (BANK) of said storer.
Further, said address control unit is used for, and in such a way said read write command is mapped in the different spaces of said storer:
If the accessed space of data-storage applications layer size is M, the space size of storer is P, and the BANK number of storer is N, and the reference address m ' after then data-storage applications layer reference address m changes through the mapping back is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round [x] is a rounding operation.
Further; Said formation scanner is used for; Scan each instruction queue successively,, then from the present instruction formation, read a read write command and deposit in the inner buffer of said formation scanner if the present instruction formation is not empty; If the present instruction formation is empty, then scan the next instruction formation;
If after all instruction queue scans more than 2 times or 2 times; Judge and have only an instruction queue all the time not for empty; And it is empty that other instruction queues are always; Then increase the bar number that at every turn from instruction queue, reads read write command, the read write command that the address of reading is continuous is merged into a read write command, and burst (Burst) parameter of adjustment read write command.
The present invention also provides a kind of memory interface access control method, and said method comprises:
The read write command that the data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
Read read write command from each space of said storer successively, send in the interface controller of said storer.
Further, in the different spaces that said read write command is mapped to said storer after, said method also comprises:
The read write command of the different spaces of said storer is sent to respectively in the corresponding instruction formation, and the number of wherein said instruction queue is identical with the number of the BANK of said storer;
From said each instruction queue, read read write command successively, send to the interface controller of said storer.
Further, according to the data-storage applications layer reference address in the said read write command, with the map addresses of said read write command in the additional space of said storer.
Further, in such a way said read write command is mapped in the different spaces of said storer:
If the accessed space of data-storage applications layer size is M, the space size of storer is P, and the BANK number of storer is N, and the reference address m ' after then data-storage applications layer reference address m changes through the mapping back is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round [x] is a rounding operation.
Further; When from said each instruction queue, reading read write command successively; Scan each instruction queue successively,, then from the present instruction formation, read a read write command and deposit in the internal buffer if the present instruction formation is not empty; If the present instruction formation is empty, then scan the next instruction formation;
If after all instruction queue scans more than 2 times or 2 times; Judge and have only an instruction queue all the time not for empty; And it is empty that other instruction queues are always; Then increase the bar number that at every turn from instruction queue, reads read write command, the read write command that the address of reading is continuous is merged into a read write command, and the Burst parameter of adjustment read write command.
Compared with prior art, the present invention can effectively improve the bandwidth of handling up of DDRX storer, and all can reach effect same to read operation and write operation, and has improved the access efficiency of storer, thus the overall performance of lifting means.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the DDR access interface sequential synoptic diagram that comprises read-write;
Fig. 2 is the composition synoptic diagram of the memory interface access control apparatus of the embodiment of the invention;
Fig. 3 is the algorithm synoptic diagram of the formation scanner of the embodiment of the invention;
Fig. 4 is the realization DDR2 memory access interface synoptic diagram according to the embodiment of the invention;
Fig. 5 is the DDR access interface synoptic diagram of continuous read operation when not adopting the present invention program;
Fig. 6 is the DDR access interface synoptic diagram of continuous read operation behind employing the present invention program.
Embodiment
Basic thought of the present invention is; Utilize the tRRD of DDRX device less; The characteristic of generally having only 2 tCK will convert the access process of control to the address space random read-write sequence of operation of DDRX into, and adjacent read-write operation is distributed on the different BANK (sheet).Like this, feasible read-write operation at random converts orderly, controllable operation into, thereby has effectively improved bandwidth availability ratio.
Based on above-mentioned thought, the present invention provides a kind of memory interface access control method, specifically adopts following technical scheme:
The instruction that the data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
From each exception instruction fetch of said storer, send in the interface controller of said storer successively.
Wherein, said instruction comprises and reading instruction or write command.
Wherein, according to the data-storage applications layer reference address in the said read write command, with the map addresses of said read write command in the additional space of said storer.
Further, in the different spaces that said read write command is mapped to said storer after, said method also comprises:
The read write command of the different spaces of said storer is sent to respectively in the corresponding instruction formation, and the number of wherein said instruction queue is identical with the number of the BANK of said storer;
From said each instruction queue, read read write command successively, send to the interface controller of said storer.
Further, can in such a way said read write command be mapped in the different spaces of said storer:
If the accessed space of data-storage applications layer size is M, the space size of storer is P, and the BANK number of storer is N, and the reference address m ' after then data-storage applications layer reference address m changes through the mapping back is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round [x] is a rounding operation.
For the ease of setting forth the present invention, below will combine accompanying drawing and specific embodiment that the enforcement of technical scheme of the present invention is described in further detail.Need to prove that under the situation of not conflicting, embodiment among the application and the characteristic among the embodiment be combination in any each other.
Embodiment one
The memory interface access control apparatus that the embodiment of the invention provides is located between data-storage applications layer and the DDRX interface controller; Read write command is sent from the data-storage applications layer as required, and the control of DDRX interface converts read write command into the access interface of DDRX.After the read write command of data storages application layer being sent through apparatus of the present invention was handled, the read write command after will handling again sent to the DDRX interface controller.
As shown in Figure 2, the memory interface access control apparatus of the embodiment of the invention mainly comprises three parts: address control unit, instruction queue and formation scanner.
Remap in the address that address control unit is mainly used in the read write command that the data-storage applications layer is sent.Concrete mapping method can be according to following steps:
The accessed space size of tentation data storage application layer is M, and the space size of DDRX device is P, and the BANK number of DDRX device is N.
Will address access space: maps to the device space:
Figure BDA0000037883690000072
Will address access space: maps to the device space:
Figure BDA0000037883690000074
……
Will address access space:
Figure BDA0000037883690000075
maps to the device space:
Figure BDA0000037883690000076
After address control unit is accomplished map addresses, the read write command of different address spaces is sent in the corresponding instruction queue.
In the present embodiment; As shown in Figure 2; Have 4 instruction queues; Then: the read write command in space
Figure BDA0000037883690000077
sends in the instruction queue 1; Read write command in the space
Figure BDA0000037883690000078
sends in the instruction queue 2; Read write command in the space
Figure BDA0000037883690000079
sends in the instruction queue 3, and the read write command in space sends in the instruction queue 4.
The input of instruction queue is connected to the output of address control unit, and the quantity setting of instruction queue is relevant with the DDRX type of device, for example can be identical with the BANK quantity of DDRX device.Scheduling is waited in the instruction first in first out that cushions in the formation.
The formation scanner scans each instruction queue (hereinafter also abbreviating formation as) successively according to timeticks, if formation does not deposit in the inner buffer of scanner for sky just reads an instruction from the output of formation, just scans next formation if formation is a sky.
Preferably; If, judge and have only a formation, and other formations are always empty all the time for empty through after 2 times or the above whole formation scanning; Then increase and read read write command bar number in the formation at every turn; And with the address continuous read or write command is merged into a read write command, adjustment Burst length re-sends to the DDRX interface controller and handles.
Fig. 3 shows the concrete operations flow process of embodiment of the invention squadron column scan device, and is as shown in Figure 3, and this flow process is described below:
Step 1, the scan instruction formation;
Step 2, whether the decision instruction formation is empty, if be empty, then move to the next instruction formation and scans; If be not empty, then continue next step;
Step 3 is taken out an instruction from current queue;
Step 4, judge whether continuous 2 whole formations scanning after, have only current queue for empty, if then execution in step 5, otherwise, from current queue, take out an instruction after, move to the next instruction formation to scan;
Step 5 increases the bar that once takes out instruction and counts parameter k, and the continuous instruction in address in this k bar read write command is merged into an instruction.
Embodiment two
Shown in Figure 4 is the embodiment that example is described this patent with the DDRII device.Memory access by application layer is initiated read-write requests through three groups of signals, comprising: the write command signal that wr_en, cmd, wr_data, wr_addr form; The read command signal that rd_en, cmd, rd_addr form; The read data effective index signal that rd_data, data_valid form.Wherein write command signal and read command signal are dredged the visit order stream of application layer through corresponding wr_cmd_fifo and rd_cmd_fifo, are convenient to instruction control unit and dispatch.
Reference address through after the cmd_fifo processing need carry out mapping treatment, and its effect is that address table in the application layer is mapped among the different B ANK in the DDRII storer, and the data of visit evenly are mapped among 8 different BANK.Address after the mapping and the synthetic visit order field of corresponding command group according to importing respectively for different B ANK number in 1～8 the instruction queue, are used for distinguishing output for unique serial number of every read access command field simultaneously.
The access instruction buffer zone takes out instruction field in 8 formations successively successively according to instruction execution cycle from wr_cmd_fifo and rd_cmd_fifo; It is painted wherein need to increase a sequence number again according to the order of taking out for reading instruction; At last instruction is pressed into and treats in the buffer zone that the ddr interface controller handles, convert the access interface sequential of DDRII device into.
The data of from the DDRII device, reading also need be gone painted processing according to painted sequence number except output data useful signal data_valid, make it data output and meet the order that order is initiated.
Adopt design proposal of the present invention, can effectively improve effective access bandwidth of DDRX storer, as shown in Figure 5, the access interface that does not adopt the present invention to design, reading 8 data needs 18 tCK; Access interface as shown in Figure 6, as to adopt the present invention to design, reading 8 data only needs 9 tCK.It is thus clear that adopt the more original scheme of effective access bandwidth of the present invention program to improve 50%, effect is remarkable.
More than be merely preferred case study on implementation of the present invention; Be not limited to the present invention; The present invention also can have other various embodiments; Under the situation that does not deviate from spirit of the present invention and essence thereof, those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Obviously, it is apparent to those skilled in the art that above-mentioned each module of the present invention or each step can realize with the general calculation device; They can concentrate on the single calculation element; Perhaps be distributed on the network that a plurality of calculation element forms, alternatively, they can be realized with the executable program code of calculation element; Thereby; Can they be stored in the memory storage and carry out, and in some cases, can carry out step shown or that describe with the order that is different from here by calculation element; Perhaps they are made into each integrated circuit modules respectively, perhaps a plurality of modules in them or step are made into the single integrated circuit module and realize.The present invention is not restricted to any specific hardware and software and combines.

Claims (10)

1. memory access interface control device; It is characterized in that; Said device comprises continuous successively: address control unit, instruction queue and instruction queue scanner, and wherein, said address control unit links to each other with the data-storage applications layer; Said instruction queue scanner links to each other with the interface controller of said storer
Said address control unit is used for, and the instruction that said data-storage applications layer is sent is mapped to the different spaces of storer respectively, and the read write command of different spaces is sent in the corresponding instruction formation;
Instruction queue is used for, the read write command that buffer memory is received;
The formation scanner is used for, and from said each instruction queue, reads read write command successively, sends to the interface controller of said storer.
2. device as claimed in claim 1 is characterized in that,
Said address control unit is used for, according to the data-storage applications layer reference address in the said read write command, with the map addresses of said read write command in the additional space of said storer.
3. according to claim 1 or claim 2 device is characterized in that,
The number of said instruction queue is identical with the number of the sheet of said storer (BANK).
4. device as claimed in claim 3 is characterized in that,
Said address control unit is used for, and in such a way said read write command is mapped in the different spaces of said storer:
If the accessed space of data-storage applications layer size is M, the space size of storer is P, and the BANK number of storer is N, and the reference address m ' after then data-storage applications layer reference address m changes through the mapping back is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round [x] is a rounding operation.
5. according to claim 1 or claim 2 device is characterized in that,
Said formation scanner is used for; Scan each instruction queue successively,, then from the present instruction formation, read a read write command and deposit in the inner buffer of said formation scanner if the present instruction formation is not empty; If the present instruction formation is empty, then scan the next instruction formation;
If after all instruction queue scans more than 2 times or 2 times; Judge and have only an instruction queue all the time not for empty; And it is empty that other instruction queues are always; Then increase the bar number that at every turn from instruction queue, reads read write command, the read write command that the address of reading is continuous is merged into a read write command, and burst (Burst) parameter of adjustment read write command.
6. a memory interface access control method is characterized in that, said method comprises:
The read write command that the data-storage applications layer is sent is mapped to respectively in the different spaces of storer;
Read read write command from each space of said storer successively, send in the interface controller of said storer.
7. method as claimed in claim 6 is characterized in that, in the different spaces that said read write command is mapped to said storer after, said method also comprises:
The read write command of the different spaces of said storer is sent to respectively in the corresponding instruction formation, and the number of wherein said instruction queue is identical with the number of the BANK of said storer;
From said each instruction queue, read read write command successively, send to the interface controller of said storer.
8. like claim 6 or 7 described methods, it is characterized in that,
According to the data-storage applications layer reference address in the said read write command, with the map addresses of said read write command in the additional space of said storer.
9. method as claimed in claim 8 is characterized in that,
In such a way said read write command is mapped in the different spaces of said storer:
If the accessed space of data-storage applications layer size is M, the space size of storer is P, and the BANK number of storer is N, and the reference address m ' after then data-storage applications layer reference address m changes through the mapping back is:
m ′ = round [ m M × N ] × P N + m - round [ m M × N ] × M N ;
Wherein, round [x] is a rounding operation.
10. method as claimed in claim 7 is characterized in that,
When from said each instruction queue, reading read write command successively; Scan each instruction queue successively,, then from the present instruction formation, read a read write command and deposit in the internal buffer if the present instruction formation is not empty; If the present instruction formation is empty, then scan the next instruction formation;
If after all instruction queue scans more than 2 times or 2 times; Judge and have only an instruction queue all the time not for empty; And it is empty that other instruction queues are always; Then increase the bar number that at every turn from instruction queue, reads read write command, the read write command that the address of reading is continuous is merged into a read write command, and the Burst parameter of adjustment read write command.
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