CN104281539A - Cache managing method and device - Google Patents
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Abstract
The invention discloses a cache managing method and device. The method is applied to a process of realizing an AFDX (Avionics Full Duplex Switched Ethernet) communication protocol by an FPGA (Field Programmable Gate Array). Under a scene of an FPGA managing storage, the method comprises the following steps: confirming a starting address and an ending address of a continuous address section used by a storage; slicing the storage within the scope of the starting address and the ending address according to the length of a predefined memory sheet, thereby acquiring the memory sheet; storing a first address of the memory sheet acquired by slicing; after receiving a distribution applying signal sent by a memory request party, inquiring if a usable memory sheet exists; if yes, distributing the memory sheet to the memory request party according to the size of the memory requested by the memory request party and sending the first address of the distributed memory sheet to the memory request party. According to the invention, the effective distribution and releasing of the cache during the realizing process of the FPGA of the AFDX communication protocol are realized.
Description
Technical field
The present invention relates to the realization of avionics full duplex real-time ethernet communication protocol, particularly relate to a kind of buffer memory management method and device.
Background technology
AFDX(Avionics Full Duplex Switched Ethernet, avionics full duplex real-time ethernet) be Airbus SAS according to ARINC664 specification, for the aircraft data network determined (Aircraft Data Networks) realize technology.Be widely used in the electronic system interconnected in aviation aircraft at present, as engine, flight-control component, cruise system etc.Up to now, AFDX is used in A380, in A400M and Boeing B787 project.
In the implementation procedure of this agreement, jumbo storer is needed to carry out buffer memory to packet, so with regard to needing, the storage space of this mass storage is managed, if use FPGA(Field Programmable Gate Array, field programmable gate array) carry out the management of storer, there is no suitable mode at present, or be not suitable for the data buffer storage management in AFDX protocol realization process.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of buffer memory management method and device, in the FPGA implementation procedure of AFDX communication protocol, can realize FPGA diode-capacitor storage.
For solving the problems of the technologies described above, a kind of buffer memory management method of the present invention, is applied to on-site programmable gate array FPGA and realizes, in the process of avionics full duplex real-time ethernet AFDX communication protocol, under the scene of FPGA diode-capacitor storage, comprising:
Determine start address and the end address of the spendable continuation address section of storer, according to predefined Memory slice length, in the scope of described start address and end address, burst is carried out to storer and obtain Memory slice, preserve the first address of the Memory slice that burst obtains;
After the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, and the first address of the Memory slice of distribution is sent to memory request side.
Further, the first address of the Memory slice that described preservation burst obtains, comprising: the first address write administration queue of the Memory slice obtained by burst;
Whether described inquiry has available Memory slice, comprising: inquire about the first address that whether there is Memory slice in described administration queue, if existed, then defines available Memory slice;
After the first address of the Memory slice by distribution sends to memory request side, from described administration queue, delete the first address of the Memory slice distributed.
Further, the storer that described predefined Memory slice length manages according to different FPGA is determined, the identical length of each Memory slice of the storer of same FPGA management is same.
Further, also comprise:
When the size of described memory request side's request internal memory is greater than the size of a Memory slice, for described memory request side distributes multiple Memory slice, and described memory request side sets up the contact between multiple Memory slices of distribution.
Further, also comprise:
Discharge in described memory request side the Memory slice applied for and the first address of the Memory slice of release be written to after in release queue corresponding to memory request side, the first address of the Memory slice in release queue corresponding for memory request side is write described administration queue, and deletes from release queue.
Further, also comprise:
When the first address of the Memory slice by distribution sends to memory request side, to internal memory, requesting party sends address valid signal, is indicated the first address of the Memory slice of transmission effective by address valid signal to internal memory requesting party.
Further, a kind of cache management device, is applied to on-site programmable gate array FPGA and realizes in the process of avionics full duplex real-time ethernet AFDX communication protocol, under the scene of FPGA diode-capacitor storage, comprise: administration queue initialization module and memory allocating module, wherein:
Described administration queue initialization module, for determining start address and the end address of the spendable continuation address section of storer, according to predefined Memory slice length, in the scope of described start address and end address, burst is carried out to storer and obtain Memory slice, preserve the first address of the Memory slice that burst obtains;
Described memory allocating module, for after the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, and the first address of the Memory slice of distribution is sent to memory request side.
Further, described administration queue initialization module, the first address specifically for the Memory slice obtained by burst writes administration queue;
Described memory allocating module, specifically for inquiring about the first address that whether there is Memory slice in described administration queue, if existed, then defines available Memory slice; Also for after the first address of the Memory slice by distribution sends to memory request side, from described administration queue, delete the first address of the Memory slice distributed.
Further, the storer that described predefined Memory slice length manages according to different FPGA is determined, the identical length of each Memory slice of the storer of same FPGA management is same.
Further, this device also comprises internal memory release management module, wherein:
Described internal memory release management module, for the release application of described memory request side to Memory slice and by after in release queue corresponding for the first address write memory requesting party of the Memory slice of release, the first address of the Memory slice in release queue corresponding for memory request side is write described administration queue, and deletes from release queue.
In sum, the present invention is by carrying out burst to the spendable continuation address section of storer, for memory request side's storage allocation sheet, realize the management of FPGA to storer, effective distribution and the release of buffer memory in the FPGA implementation procedure of AFDX communication protocol can be realized.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of the buffer memory management method of embodiment of the present invention;
Fig. 2 is the Organization Chart of the cache management device of embodiment of the present invention.
Embodiment
For making the object of the application, technical scheme and advantage clearly understand, hereinafter will by reference to the accompanying drawings the embodiment of the application be described in detail.It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combination in any mutually.
As shown in Figure 1, the buffer memory management method of present embodiment comprises under being applied to and carrying out the scene of cache management to the FPGA in the FPGA implementation procedure of AFDX communication protocol:
Step 101: administration queue initialization, administration queue initialization module determines start address and the end address of operable continuation address section;
The operable continuation address section of storer refers to that the contiguous memory space at this point location segment limit can use.
In present embodiment by abstract for the different types of storer used in implementation procedure become one by addressing of address, with the storer of data input/output interface, the management like this for address will simplify a lot of program.
Step 102: according to predefined Memory slice length, carry out burst to continuation address section, preserves the first address of the Memory slice that burst obtains;
Preserve the first address of the Memory slice that burst obtains, comprising: the first address write administration queue of the Memory slice that burst is obtained.Preserving the first address of Memory slice by administration queue in present embodiment can managing internal memory sheet easily, corresponding Memory slice can be navigated to easily by the first address of Memory slice, preserved the first address of Memory slice by administration queue, the operation such as the inquiry of Memory slice service condition and Memory slice distribution can be carried out easily.
To the process of storer burst until complete to the memory headroom burst within the scope of start address and end address, or administration queue is full, namely completes the initialization of administration queue.
The process of burst is a process calculated, and calculates the first address of each Memory slice within the scope of start address and end address according to predefined Memory slice length gauge.
Such as, for the continuation address section of a 8K, predefined Memory slice length 2K, so can go out 4 Memory slices by burst, the first address of 4 Memory slices order is write in administration queue.
When considering in present embodiment that use FPGA realizes memory management, carrying out managing for scattered or elongated internal memory is be difficult to realize, so storer is carried out the process of fixed length burst in implementation procedure, at every turn according to the size of memory request side's request internal memory, use one or more Memory slice.
The determination of predefined Memory slice length, determine according to the storer that different FPGA manages, the different storeies predefined Memory slice length managed for different FPGA can not be identical, and the length of each Memory slice of the storer of a FPGA management is identical.
Because address be all with 2 Nth power alignment, so the size of Memory slice also need be 2 Nth power be only reasonably.Consider that each packet of AFDX communication protocol is maximum and be no more than 1518 bytes, so the Memory slice length that can define in present embodiment is 2K byte, use in units of 2K byte when also namely using at every turn.
Administration queue can adopt First Input First Output, after operable continuation address section being carried out burst in system initialization process, is managed by the first address of each Memory slice stored in First Input First Output.Storer needs constantly to recycle, and used Memory slice needs constantly to reuse, and is dispensed by Memory slice during use, when Memory slice does not re-use, then is returned in administration queue.Because each Memory slice does not use in order, order is given back, adopt First Input First Output, the Memory slice that first address is introduced into administration queue is first used, and ensures the orderly use of Memory slice.
Step 103: memory allocating module is after the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, the first address of the Memory slice of distribution is sent to memory request side;
Whether inquiry has available Memory slice, comprising: the first address that whether there is Memory slice in searching and managing queue, if existed, then defines available Memory slice; Further, in present embodiment, after the first address of the Memory slice by distribution sends to memory request side, also the first address of the Memory slice of distribution is deleted from administration queue.
When administration queue adopts First Input First Output, if there is the first address of multiple Memory slice in administration queue, and memory request side only needs a Memory slice, then Memory slice corresponding for the first address entering administration queue in the first address of the multiple Memory slices in administration queue is at first distributed to memory request side.
When the first address of the Memory slice by distribution sends to memory request side, memory allocating module also sends address valid signal to internal memory requesting party, is indicated the first address of the Memory slice of transmission effective by address valid signal to internal memory requesting party.
Three key signals are had in the distribution of internal memory, application distributing signal, address valid signal and allocation address output signal (carrying the first address of the Memory slice of distribution), often receive once the application distributing signal that effective memory request side sends, if there is the first address of Memory slice in administration queue, be then memory request side's storage allocation sheet, send the first address of the Memory slice of address valid signal and distribution to internal memory requesting party, complete address assignment; If administration queue has been empty, namely do not have available Memory slice to distribute, then needing wait to have during Memory slice is memory request side's storage allocation sheet again.Until when having the memory request side of releasing memory sheet, just have available Memory slice, in present embodiment, one stand-by period threshold value can be set, when arriving stand-by period threshold value, so there is no available Memory slice if appointed, then sending distribution failure response to internal memory requesting party.
When the internal memory of memory request side's request is greater than the size of a Memory slice, for memory request side distributes multiple Memory slice, and, the contact between the multiple Memory slices distributed is set up by memory request side.
Contacting and can be set up by the mode of allocation index before Memory slice and Memory slice, allocation index refers to that memory request side stores the first address of a Memory slice next in previous Memory slice.
Step 104: internal memory release management module memory request side release application to Memory slice and the first address of the Memory slice of release is written to after in release queue corresponding to memory request side, by the first address of the Memory slice in release queue corresponding for memory request side write administration queue, and from release queue, delete the first address of Memory slice.
The process of internal memory release is that each needs the corresponding release queue of the module (memory request side) of releasing memory, the first address of the Memory slice that this release queue buffer memory needs the module of releasing memory to discharge, internal memory release management module is regularly or after needing the module request of releasing memory, the first address of the Memory slice in the buffer queue needing the module of releasing memory corresponding is write administration queue, and delete the first address of Memory slice from release queue.The main cause arranging buffer queue, when preventing disparate modules from needing releasing memory sheet simultaneously, operates simultaneously and produce conflict, cause internal memory normally not discharge, thus cause RAM leakage administration queue.
As shown in Figure 2, present embodiment also discloses a kind of cache management device, is applied to FPGA and realizes, in the process of AFDX communication protocol, under the scene of FPGA diode-capacitor storage, comprising: administration queue initialization module and memory allocating module, wherein:
Administration queue initialization module, for determining start address and the end address of the spendable continuation address section of storer, according to predefined Memory slice length, in the scope of start address and end address, burst is carried out to storer and obtain Memory slice, preserve the first address of the Memory slice that burst obtains;
Memory allocating module, for after the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, and the first address of the Memory slice of distribution is sent to memory request side.
Administration queue initialization module, the first address specifically for the Memory slice obtained by burst writes administration queue;
Memory allocating module, specifically for whether there is the first address of Memory slice in searching and managing queue, if existed, then defines available Memory slice; Also for after the first address of the Memory slice by distribution sends to memory request side, from administration queue, delete the first address of the Memory slice distributed.
The storer that predefined Memory slice length manages according to different FPGA is determined, the identical length of each Memory slice of the storer of same FPGA management is same.
This device also comprises internal memory release management module, wherein:
Internal memory release management module, for the release application of memory request side to Memory slice and by after in release queue corresponding for the first address write memory requesting party of Memory slice of release, by the first address of the Memory slice in release queue corresponding for memory request side write administration queue, and delete from release queue.
The all or part of step that one of ordinary skill in the art will appreciate that in said method is carried out instruction related hardware by program and is completed, and described program can be stored in computer-readable recording medium, as ROM (read-only memory), disk or CD etc.Alternatively, all or part of step of above-described embodiment also can use one or more integrated circuit to realize, and correspondingly, each module/unit in above-described embodiment can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.The application is not restricted to the combination of the hardware and software of any particular form.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the application.
Claims (10)
1. a buffer memory management method, is characterized in that, is applied to on-site programmable gate array FPGA and realizes, in the process of avionics full duplex real-time ethernet AFDX communication protocol, under the scene of FPGA diode-capacitor storage, comprising:
Determine start address and the end address of the spendable continuation address section of storer, according to predefined Memory slice length, in the scope of described start address and end address, burst is carried out to storer and obtain Memory slice, preserve the first address of the Memory slice that burst obtains;
After the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, and the first address of the Memory slice of distribution is sent to memory request side.
2. the method for claim 1, is characterized in that:
The first address of the Memory slice that described preservation burst obtains, comprising: the first address write administration queue of the Memory slice obtained by burst;
Whether described inquiry has available Memory slice, comprising: inquire about the first address that whether there is Memory slice in described administration queue, if existed, then defines available Memory slice;
After the first address of the Memory slice by distribution sends to memory request side, from described administration queue, delete the first address of the Memory slice distributed.
3. the method for claim 1, is characterized in that, the storer that described predefined Memory slice length manages according to different FPGA is determined, the identical length of each Memory slice of the storer of same FPGA management is same.
4. the method for claim 1, is characterized in that, also comprises:
When the size of described memory request side's request internal memory is greater than the size of a Memory slice, for described memory request side distributes multiple Memory slice, and described memory request side sets up the contact between multiple Memory slices of distribution.
5. the method for claim 1, is characterized in that, also comprises:
Discharge in described memory request side the Memory slice applied for and the first address of the Memory slice of release be written to after in release queue corresponding to memory request side, the first address of the Memory slice in release queue corresponding for memory request side is write described administration queue, and deletes from release queue.
6. the method for claim 1, is characterized in that, also comprises:
When the first address of the Memory slice by distribution sends to memory request side, to internal memory, requesting party sends address valid signal, is indicated the first address of the Memory slice of transmission effective by address valid signal to internal memory requesting party.
7. a cache management device, it is characterized in that, be applied to on-site programmable gate array FPGA and realize in the process of avionics full duplex real-time ethernet AFDX communication protocol, under the scene of FPGA diode-capacitor storage, comprise: administration queue initialization module and memory allocating module, wherein:
Described administration queue initialization module, for determining start address and the end address of the spendable continuation address section of storer, according to predefined Memory slice length, in the scope of described start address and end address, burst is carried out to storer and obtain Memory slice, preserve the first address of the Memory slice that burst obtains;
Described memory allocating module, for after the application distributing signal receiving the transmission of memory request side, whether inquiry has available Memory slice, if had, be then memory request side's storage allocation sheet according to the size of memory request side's request internal memory, and the first address of the Memory slice of distribution is sent to memory request side.
8. device as claimed in claim 7, is characterized in that:
Described administration queue initialization module, the first address specifically for the Memory slice obtained by burst writes administration queue;
Described memory allocating module, specifically for inquiring about the first address that whether there is Memory slice in described administration queue, if existed, then defines available Memory slice; Also for after the first address of the Memory slice by distribution sends to memory request side, from described administration queue, delete the first address of the Memory slice distributed.
9. device as claimed in claim 7, is characterized in that: the storer that described predefined Memory slice length manages according to different FPGA is determined, the identical length of each Memory slice of the storer of same FPGA management is same.
10. device as claimed in claim 7, it is characterized in that, this device also comprises internal memory release management module, wherein:
Described internal memory release management module, for the release application of described memory request side to Memory slice and by after in release queue corresponding for the first address write memory requesting party of the Memory slice of release, the first address of the Memory slice in release queue corresponding for memory request side is write described administration queue, and deletes from release queue.
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