CN108366111B - Data packet low-delay buffer device and method for switching equipment - Google Patents
Data packet low-delay buffer device and method for switching equipment Download PDFInfo
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- CN108366111B CN108366111B CN201810117265.8A CN201810117265A CN108366111B CN 108366111 B CN108366111 B CN 108366111B CN 201810117265 A CN201810117265 A CN 201810117265A CN 108366111 B CN108366111 B CN 108366111B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
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- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/12—Avoiding congestion; Recovering from congestion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/50—Queue scheduling
Abstract
A low-delay data packet buffer device and method for switching device is prepared as setting data packet aggregation module, scheduler module, data receiving module, buffer module, dynamic internal memory distribution module, data sending module, internal memory block state table module and idle internal memory block first-in first-out queue module. The method comprises the following steps: the aggregation module aggregates the data packets into aggregation data blocks with fixed sizes, and the scheduler module allocates cache addresses for the aggregation data blocks. The dynamic memory block management module maintains the use information of the memory blocks, and the data receiving module moves the aggregated data blocks to the corresponding DRAM cache units. And the output port sends a reading application to the scheduler module, and the data sending module outputs the data packet to the outside from the buffer after collision detection. The invention reduces the time delay of the buffer and improves the processing speed of the switching equipment.
Description
Technical Field
The invention belongs to the technical field of communication, and further relates to a low-delay data packet caching device and method for switching equipment in the technical field of communication networks. The invention can be used for the switching equipment to realize the fast low-delay caching of the data packet and effectively improve the performance of the switching equipment.
Background
With the increasing development of communication technology, people have higher and higher requirements on data transmission rate. The great increase of the transmission rate brings greater challenges to the reading and writing rate and capacity of the buffer in the Ethernet switch or the router line card. On the one hand, as link rates and switching network rates increase, packets are required to enter and leave the on-line card buffers at faster and faster rates. The data bus for memory reading and writing is usually shared, a packet arrives and is written into the buffer first, and the process of the packet arriving at the buffer and leaving the buffer requires the buffer bus to have twice the link rate. On the other hand, to reduce the loss rate, the line card capacity is at least the product of the link rate R and the end-to-end round trip delay RRT, so that the required memory capacity is about 10 gbytes. Therefore, a buffer memory unit with large capacity, high bandwidth and fast access is needed to absorb data fluctuation in the network.
The buffer usually uses a hierarchical memory structure consisting of a static random access memory SRAM with limited capacity and small time delay and a dynamic random access memory DRAM with large capacity and large read-write time delay, the SRAM temporarily stores the packets needing to be transmitted between the input and output links and the DRAM and divides queues for the packets needing to be enqueued and dequeued, and the problem of multi-queue storage of the variable-length packets is solved; the DRAM is used as a cache entity to provide a large-capacity storage space, and the two are matched with each other to simultaneously meet the requirements of speed and capacity. The specific functions of the buffer include that the aggregation module segments the data packets transmitted by each data stream and aggregates the data packets into aggregation data blocks with fixed sizes, and the scheduler module allocates buffer addresses for the aggregation data blocks. The dynamic memory block management module maintains queue information and allows the tail and head of the queue to dynamically share memory block information. And when detecting that the queue state is not empty, the data receiving module moves the aggregated data block to a corresponding DRAM cache unit.
Shenzhen Shang bang Yangxiang data technology Limited company in the patent document 'a method and device for buffering Ethernet data packet' (application number: 201210128718.X publication number: CN 102629914A) proposed by Shenzhen Shang Yan information technology Limited company. The device comprises an arbitration module, a first-in first-out queue (FIFO) module, a memory recovery module, a memory block state table, a bit width conversion module and an address mapping module, wherein the bit width conversion module is used for converting the bit width of an Ethernet data packet into the bit width consistent with that of a dynamic random access memory controller, the address mapping module is used for outputting the address of the Ethernet data packet to a memory block of the dynamic random access memory according to the instruction of the arbitration module, the arbitration module is used for controlling the reading/writing of the Ethernet data packet to the memory block, the memory recovery module is used for recovering the failed memory block, the first-in queue (FIFO) module is used for storing the information of the recovered memory block, and the memory block state table is used for storing the address information of the memory block. The device has the disadvantages that a transmission mechanism of a request port to a dynamic memory allocation module is lacked, the request port needs to firstly apply for a memory block address when writing data into a memory block and then transmit the data, so that the processing speed is reduced, and congestion and even packet loss can be caused in a high-speed switch.
The method disclosed in this patent includes the steps of first, dividing the DRAM into a plurality of memory blocks, and satisfying the requirement of packet storage without page crossing; secondly, the request port sends a write request instruction to the arbitration module, and the arbitration module reads out the number of the idle memory block from the idle queue as the address of the memory block; thirdly, the arbitration module sends a signal responding to the request, data can be written into the memory block, the data can be written into a memory block state table, meanwhile, the survival time is written and is added with 1, and the request port records the serial number of the memory block; fourthly, when a port requests to read data from the memory block, the arbitration module performs balance selection, when the port acquires arbitration, data reading is performed by using the memory block number fed back during writing, and after reading is completed, the corresponding survival time in the memory block table is reduced by 1; fifthly, when the lifetime is 0, the memory recovery module recovers the memory block and returns the address of the memory to the FIFO module. The method caches the Ethernet data packet with lower processing delay, and achieves the purposes of high access speed, large storage capacity and low implementation cost. The method has the disadvantages that a storage area is statically divided for each data packet with an indefinite length, fragments in the memory are formed when the length of the data packet is smaller than that of a memory block, and the fragments cannot be utilized by other queues, so that the storage space is wasted.
The patent document 'packet buffer management method and apparatus' (application number: 201010591757.4, publication number: CN 102025634 a) filed by zhongxing communication corporation, the apparatus includes an instruction receiving unit, a buffer mode determining unit and a packet processing unit, an external buffer device and an internal buffer device; wherein the instruction processing apparatus comprises. The instruction receiving unit is used for receiving a write instruction, acquiring information of a data packet in the write instruction and a preset cache strategy to determine a cache mode of the data packet, wherein the cache modes include two types, one type is an external cache mode, and the other type is an internal and external combined cache mode combining an external cache and an internal cache; the data packet reading and writing unit is used for caching the data packet according to the determined caching mode; the external cache device and the internal cache device are used for caching the data packet. The device has the defects that a dynamic memory allocation module is lacked, only dequeue or enqueue operation can be processed at the same time, parallel processing cannot be achieved, the processing speed is limited, and on the other hand, when the data packet arrival speed is increased, the mode can cause data packet waiting during write-in operation, so that congestion occurs or even packet loss occurs.
The method disclosed in the patent comprises the steps that, in the first step, the communication equipment receives a write command and acquires data packet information; secondly, the communication equipment determines the caching mode of the data packet according to the data packet information and a preset caching strategy; and thirdly, the communication equipment caches the data packet to an external cache device or the external cache device and an internal cache device according to the determined cache mode. The method has the disadvantages that after the communication equipment acquires the data packet, the communication equipment judges the cache mode according to the data packet information and then transmits the data, so that the processing speed is reduced, the realization complexity is increased, and the mode can generate congestion and even packet loss in a high-speed switch.
Disclosure of Invention
The present invention aims to provide a low-latency buffer device and method for data packets of a switching device, which are used for aggregating the data packets, buffering the data packets into the whole line memory area of a memory, dynamically allocating memory blocks, reducing the latency of an external buffer, and realizing the low-latency buffer of high-speed data packets.
The invention aims to provide a buffer memory with the specific functions that an aggregation module segments data packets transmitted by each data stream and aggregates the data packets into aggregation data blocks with fixed sizes, and a scheduler module allocates buffer addresses for the aggregation data blocks. The dynamic memory block management module maintains queue information and allows the tail and head of the queue to dynamically share memory block information. And when detecting that the queue state is not empty, the data receiving module moves the aggregated data block to a corresponding DRAM cache unit. The reading unit sends a reading application to the scheduler module, and after the conflict detection module detects that no writing conflict exists, the data sending module reads out the data packet from the cache region and outputs the data packet to the outside to finish the forwarding.
The device comprises a scheduler module, an idle memory block first-in first-out queue module, a memory block state table module, a data receiving module, a cache region module and a data sending module; the device is characterized by also comprising a data packet aggregation module and a dynamic memory allocation module; the scheduler module is respectively connected with the data packet aggregation module and the dynamic memory allocation module through a control bus, the dynamic memory allocation module is respectively connected with the memory block state table module and the idle memory block first-in first-out queue module through the control bus, and the data packet aggregation module is connected with the data receiving module through a data bus; the scheduler module is respectively connected with the data receiving module and the data sending module through a control bus; the data receiving module and the data sending module are connected with the cache region module interface through a data bus; wherein:
the data packet aggregation module is used for setting an aggregation counter to zero when initializing; receiving a write-in application of a data packet, and respectively extracting a destination port number and an effective length of the data packet from the write-in application; numbering the queue number sequence of the data packet by using a binary numerical value sequence of a destination port number, and writing the numbered queue number sequence into a queue number field of a first-in first-out queue of the aggregated block information; when the data packets are aggregated, taking the binary number value of the number of bytes occupied by the row memory space of the DRAM as the aggregation upper limit value; taking the binary value of the quotient of the system bandwidth of the data packet cache device and the number of bytes in the row storage space as the upper counting limit value of the aggregation counter; a merging module in the data packet aggregation module reads the data packet input by the input port and writes the data packet into an aggregation block memory; the merging module acquires the byte number in the aggregated block memory by using a byte number calculation method; judging whether the byte number in the aggregation block memory reaches an aggregation upper limit value, and if so, applying for a cache space; otherwise, the operation is finished; judging whether the byte number in the aggregation block memory reaches an aggregation upper limit value, and if so, applying for a cache space; otherwise, continuing to write the data packet into the aggregation block memory; judging whether the count value of the aggregation counter is greater than the count upper limit value, if so, applying for a cache space; otherwise, after the count value of the aggregation counter is added by 1, applying for a cache space until the count value reaches the upper limit value of the count; the merging module stops writing data packets into the aggregation block memory and sets an aggregation counter to be zero; adding 1 to the numerical value in the number field of the aggregation block information FIFO queue; writing the byte number in the aggregation block memory into an effective length field of an aggregation block information first-in first-out queue; sending a write request application to a scheduler module;
the scheduler module is used for reading the aggregation block information of the aggregation block information first-in first-out queue; taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the idle memory block first-in first-out queue; writing the initial address of the memory block into a cache address field of an aggregation block information first-in first-out queue; receiving a write request sent by a data packet aggregation module, acquiring a memory block address from an idle memory block first-in first-out queue module, and allocating a cache address for an aggregated data packet; reading the starting address of the memory block of the request buffer, and sending the starting address of the memory block to the dynamic memory allocation module;
the dynamic memory allocation module is configured to set a memory block state table entry address during initialization, where a high bit of the address indicates a queue number and a low bit of the address indicates a memory block label; taking the hexadecimal numerical sequence of the product value of the state table entry address of the memory block and the byte number of the row storage area as the initial address sequence of the memory block in the cache area; sequentially writing the initial address sequence of the memory block in each cache region into a first-in first-out queue module of the idle memory block; after receiving the application for changing the memory block state table, writing the effective length of the aggregated block into an aggregated block effective length field of the memory block state table; writing the initial address of the memory block into a cache address field of a memory block state table; adding 1 to a memory block survival time field of a memory block state table; setting a memory block recovery state field of a memory block state table to be 0; setting a write completion field of the memory block state table to 0; for changing the memory block state table; and if the value of the memory block recovery field of the memory block state table is 1, writing the initial address of the memory block into the first-in first-out queue of the idle memory block. The memory block state table is used for storing the information of the memory block; if the write completion field of the memory block state table is 0, sending the initial address of the memory block to the data sending module;
the memory block state table module is used for storing the occupation condition, the effective bytes, the idle state and the living space information of the DRAM memory block; subtracting 1 from the memory block survival time field of the memory block state table; setting a memory block recovery state field of a memory block state table to be 1;
the idle memory block first-in first-out queue module is used for storing the starting address of the unused memory block;
the data receiving module is used for reading the initial address of the memory block and the effective caching length from the aggregation block information first-in first-out queue; setting a write completion field of a memory block state table to 1; the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus; sending an application for changing a memory block state table to a dynamic memory allocation module;
the data sending module is used for reading the starting address of the memory block of the request buffer; the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus; sending an idle cache address updating application to a dynamic memory allocation module;
and the buffer area module is used for storing the data packet.
The method comprises the following specific steps:
(1) initialization:
(1a) the buffer area module sets all address spaces of the storage area of the buffer area module to zero;
(1b) setting an aggregation counter in a data packet aggregation module to zero;
(2) dividing the memory blocks:
(2a) the dynamic memory allocation module sets a memory block state table entry address, wherein the high order of the address represents a queue number, and the low order of the address represents a memory block label;
(2b) the dynamic memory allocation module uses a binary numerical value sequence of a product value of the state table entry address of the memory block and the byte number of the row storage area as a memory block initial address sequence of a cache area;
(2c) sequentially writing the initial address sequence of the memory block in each cache region into a first-in first-out queue module of the idle memory block;
(3) reading data packet information:
(3a) the data packet aggregation module receives a writing application of a data packet, and respectively extracts a destination port number of the data packet and an effective length of the data packet from the writing application;
(3b) numbering the queue number sequence of the data packet by using a binary numerical value sequence of a destination port number, and writing the numbered queue number sequence into a queue number field of a first-in first-out queue of the aggregated block information;
(4) aggregating data packets:
(4a) taking a binary number value of the number of bytes occupied by a row memory space of a Dynamic Random Access Memory (DRAM) as an aggregation upper limit value;
(4b) taking the binary number value of the quotient of the bandwidth of the cache device and the number of bytes in the row storage space as the upper limit value of the counting of the aggregation counter;
(4c) a merging module in the data packet aggregation module reads the data packet input by the input port and writes the data packet into an aggregation block memory;
(4d) the merging module acquires the byte number in the aggregated block memory by using a byte number calculation method;
(4e) judging whether the number of bytes in the aggregation block memory reaches an aggregation upper limit value, if so, executing the step (5); otherwise, executing the step (4 f);
(4f) judging whether the count value of the aggregation counter is larger than the upper limit value of the aggregation counter, if so, executing the step (5); otherwise, executing the step (4 g);
(4g) adding 1 to the count value of the aggregation counter and then executing the step (4 f);
(5) applying for a cache space:
(5a) the merging module stops writing data packets into the aggregation block memory and sets an aggregation counter to be zero;
(5b) adding 1 to the numerical value in the number field of the aggregation block information FIFO queue;
(5c) writing the byte number in the aggregation block memory into an effective length field of an aggregation block information first-in first-out queue;
(5d) the data packet aggregation module sends a write request application to the scheduler module;
(6) allocating a cache address:
(6a) the scheduler module reads the aggregation block information of the aggregation block information first-in first-out queue;
(6b) taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the idle memory block first-in first-out queue;
(6c) writing the initial address of the memory block into a cache address field of an aggregation block information first-in first-out queue;
(7) moving the data packet:
(7a) the data receiving module reads the initial address of the memory block and the effective cache length from the aggregation block information first-in first-out queue;
(7b) the data receiving module sets a write completion field of the memory block state table to be 1;
(7c) the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus;
(7d) sending an application for changing a memory block state table to a dynamic memory allocation module;
(8) updating the state information of the memory blocks:
(8a) after receiving the application for changing the memory block state table, the dynamic memory allocation module writes the effective length of the aggregated block into an aggregated block effective length field of the memory block state table;
(8b) writing the initial address of the memory block into a cache address field of a memory block state table;
(8c) setting a memory block survival time field of a memory block state table to be 1;
(8d) setting a memory block idle state field of a memory block state table to be 0;
(8e) setting a write completion field in a memory block state table to 0;
(9) responding to the read request:
(9a) the output port sends a request for reading data to the scheduler module;
(9b) the output port writes the memory block address to be read into the request buffer;
(10) and (3) detecting a conflict:
(10a) the scheduler module reads the starting address of the memory block of the request buffer and sends the starting address of the memory block to the dynamic memory allocation module;
(10b) the dynamic memory allocation module takes the initial address of the memory block as a read address and reads the information of the memory block from the memory block state table;
(10c) if the write completion field of the memory block state table is 0, the dynamic memory allocation module sends the initial address of the memory block to the data sending module;
(11) reading the data block:
(11a) the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus;
(11b) sending an idle cache address updating application to a dynamic memory allocation module;
(12) and updating the idle cache address:
(12a) the dynamic memory allocation module changes a memory block state table;
(12b) and if the value of the memory block recovery field of the memory block state table is 1, writing the initial address of the memory block into the first-in first-out queue of the idle memory block.
Compared with the prior art, the invention has the following advantages:
first, since the device allocates the address of the free memory block to the aggregated data block during the write processing of the aggregated data block after the initialization of the dynamic memory allocation module, and updates the first-in first-out queue of the free memory block after the use of the device, the problem that the processing speed is limited because the memory block address needs to be applied first and then data transmission needs to be performed when a request port writes data into the memory block in the prior art is overcome, so that the device has the advantage of high data processing speed, and can be applied to a higher-speed switching system.
Secondly, because the dynamic memory allocation module in the device of the invention has the function of detecting whether data transmission conflicts when data is output, and the write-in or read-out operation can be processed at the same time, the processing speed is improved, and the defects that the dynamic memory allocation module is lacked in the prior art, only the dequeue or enqueue operation can be processed at the same time, parallel processing cannot be realized, and the processing speed is limited are overcome, so that the device has the advantages of conflict-free data processing, and the congestion can be reduced.
Thirdly, because the data packet aggregation module in the method of the present invention can merge the data packets with uncertain length into the aggregated block with the same size as the memory block, and no fragment is generated during writing and reading, the problem that the dynamic random access memory DRAM is divided into the memory blocks with fixed length in the prior art, and the fragment in the memory is caused by the uncertain length of the data packet, is overcome, so that the device of the present invention has the advantage of high storage utilization rate.
Fourthly, because the dynamic memory allocation module in the method of the invention can adopt a hierarchical storage mode to store the information of the head, the tail and the like of the queue in the SRAM, and store the data packet in the DRAM without increasing the hardware logic for judging the cache mode of the data packet, the problem that the processing speed is reduced because the communication equipment judges the cache mode according to the information of the data packet and then transmits the data after acquiring the data packet in the prior art is solved, and the implementation complexity of the invention is reduced.
Drawings
FIG. 1 is a block diagram of the apparatus of the present invention;
FIG. 2 is a flow chart of the method of the present invention;
fig. 3 is a flow chart of the step of aggregating packets in the method of the present invention.
FIG. 4 is a flowchart of the step of the dynamic memory allocation module changing the memory block status table in the method of the present invention
Detailed Description
The invention is further described below with reference to the accompanying drawings.
The apparatus of the present invention is further described with reference to figure 1.
The device comprises an idle memory block first-in first-out queue module, a memory block state table module, a data receiving module, a buffer area module, a data sending module, a scheduler module, a data packet aggregation module and a dynamic memory allocation module; the scheduler module is respectively connected with the data packet aggregation module and the dynamic memory allocation module through control buses, the dynamic memory allocation module is respectively connected with the idle memory block first-in first-out queue module and the memory block state table module through the control buses, and the data packet aggregation module is connected with the data receiving module through data buses; the scheduler module is respectively connected with the data receiving module and the data sending module through a control bus; the buffer area module interface is respectively connected with the data receiving module and the data sending module through data buses.
The data packet aggregation module is used for setting an aggregation counter to zero when initializing; receiving a write-in application of a data packet, and respectively extracting a destination port number and an effective length of the data packet from the write-in application; numbering the queue number sequence of the data packet by using a binary numerical value sequence of a destination port number, and writing the numbered queue number sequence into a queue number field of a first-in first-out queue of the aggregated block information; when the data packets are aggregated, taking the binary number value of the number of bytes occupied by the row memory space of the DRAM as the aggregation upper limit value; taking the binary value of the quotient of the system bandwidth of the data packet cache device and the number of bytes in the row storage space as the upper counting limit value of the aggregation counter; a merging module in the data packet aggregation module reads a data packet input by an input port, writes the data packet into an aggregation block memory, and acquires the number of bytes in the aggregation block memory by using a byte number calculation method; judging whether the byte number in the aggregation block memory reaches an aggregation upper limit value, and if so, applying for a cache space; otherwise, continuing to write the data packet into the aggregation block memory; judging whether the count value of the aggregation counter is greater than the upper limit value of the aggregation counter, and if so, applying for a cache space; otherwise, after the count value of the aggregation counter is added by 1, applying for a cache space until the count value reaches the upper limit value of the count; the merging module stops writing data packets into the aggregation block memory and sets an aggregation counter to be zero; adding 1 to the numerical value in the number field of the aggregation block information FIFO queue; writing the byte number in the aggregation block memory into an effective length field of an aggregation block information first-in first-out queue; and sending a write request application to a scheduler module.
The scheduler module is used for reading the aggregation block information of the aggregation block information first-in first-out queue; taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the idle memory block first-in first-out queue; writing the initial address of the memory block into a cache address field of an aggregation block information first-in first-out queue; receiving a write request sent by a data packet aggregation module, acquiring a memory block address from an idle memory block first-in first-out queue module, and allocating a cache address for an aggregated data packet; and reading the memory block starting address of the request buffer, and sending the memory block starting address to the dynamic memory allocation module.
The dynamic memory allocation module is used for setting a memory block state table entry address when initializing, wherein the high order of the address represents a queue number, and the low order of the address represents a memory block label; taking the hexadecimal numerical sequence of the product value of the state table entry address of the memory block and the byte number of the row storage area as the initial address sequence of the memory block in the cache area; sequentially writing the initial address sequence of the memory block in each cache region into a first-in first-out queue module of the idle memory block; after receiving the application for changing the memory block state table, writing the effective length of the aggregated block into an aggregated block effective length field of the memory block state table; writing the initial address of the memory block into a cache address field of a memory block state table; adding 1 to a memory block survival time field of a memory block state table; setting a memory block recovery state field of a memory block state table to be 0; setting a write completion field of the memory block state table to 0; for changing the memory block state table; and if the value of the memory block recovery field of the memory block state table is 1, writing the initial address of the memory block into the first-in first-out queue of the idle memory block. The memory block state table is used for storing the information of the memory block; and if the write completion field of the memory block state table is 0, sending the initial address of the memory block to the data sending module.
The memory block state table module is used for storing the occupation condition, the effective bytes, the idle state and the living space information of the DRAM memory block; subtracting 1 from the memory block survival time field of the memory block state table; the memory block recycling status field of the memory block status table is set to 1.
The data receiving module is used for reading the initial address of the memory block and the effective caching length from the aggregation block information first-in first-out queue; setting a write completion field of a memory block state table to 1; the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus; and sending an application for changing the memory block state table to the dynamic memory allocation module.
The idle memory block first-in first-out queue module is used for storing the starting address of the unused memory block;
the data sending module is used for reading the starting address of the memory block of the request buffer; the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus; and sending an application for updating the idle cache address to the dynamic memory allocation module.
And the buffer area module is used for storing the data packet.
The method of the invention is further described with reference to figure 2.
And step 1, initializing.
The buffer area module sets the whole address space of the storage area of the buffer area module to zero.
And setting an aggregation counter in the data packet aggregation module to be zero.
And 2, dividing the memory blocks.
The dynamic memory allocation module sets a memory block state table entry address, the high order of which represents a queue number and the low order of which represents a memory block label.
The dynamic memory allocation module uses the binary value sequence of the product value of the state table entry address of the memory block and the byte number of the row storage area as the memory block starting address sequence of the cache area.
And sequentially writing the initial address sequence of the memory block in each cache region into the first-in first-out queue module of the idle memory block.
And 3, reading the data packet information.
And the data packet aggregation module receives a writing application of the data packet, and respectively extracts a destination port number of the data packet and the effective length of the data packet from the writing application.
The write request of the data packet comprises a data packet input port field, a destination port field and a cache effective length field.
And numbering the queue number sequence of the data packet by using the binary numerical value sequence of the destination port number, and writing the numbered queue number sequence into a queue number field of the aggregation block information first-in first-out queue.
And 4, aggregating the data packets.
This step is described in further detail below with reference to fig. 3.
And (4.1) taking the binary number value of the number of bytes occupied by the row memory space of the DRAM as the upper aggregation limit value.
And (4.2) taking the binary value of the quotient value of the bandwidth of the cache device and the number of bytes of the line storage space as the upper limit value of the counting of the aggregation counter.
And (4.3) a merging module in the data packet aggregation module reads the data packet input by the input port and writes the data packet into the aggregation block memory.
And (4.4) the merging module acquires the byte number in the memory of the aggregation block by using a byte number calculation method.
The byte number calculating method comprises the following steps:
and step 1, resetting the length register.
And step 2, registering the length value of the currently received data packet into a length register.
And 3, adding the length value in the extracted length register with the length value of the currently received data packet, registering the addition result in the length register, and taking the value in the length register as the byte number of the aggregated data packet.
(4.5) judging whether the number of bytes in the aggregation block memory reaches an aggregation upper limit value, if so, executing the step 5, otherwise, executing the step (4.6).
And (4.6) judging whether the count value of the aggregation counter is larger than the upper limit value of the aggregation counter, if so, resetting the count value to zero and then executing the step 5, otherwise, continuously increasing the count value of the aggregation counter and executing the step (4.7).
And (4.7) adding 1 to the count value of the aggregation counter and executing (4.6).
And 5, applying for a cache space.
And the merging module stops writing data packets into the aggregation block memory, resets the aggregation counter to zero, and adds 1 to the numerical value in the number field of the first-in first-out queue of the aggregation block information.
And writing the byte number in the aggregation block memory into an effective length field of the aggregation block information FIFO queue.
And the data packet aggregation module sends a write request application to the scheduler module.
And 6, allocating a cache address.
And the scheduler module reads the aggregation block information of the aggregation block information FIFO queue.
The aggregation block information includes an aggregation block queue number, an aggregation block number, an effective length, and a memory block start address.
And taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the free memory block first-in first-out queue.
And writing the initial address of the memory block into a cache address field of the aggregation block information FIFO queue.
And 7, moving the data packet.
The data receiving module reads the initial address of the memory block and the effective length of the cache from the aggregation block information first-in first-out queue.
The data receiving module sets a write completion field of the memory block state table to 1.
And the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus.
And sending a request for changing the memory block state table to the dynamic memory allocation module.
And 8, updating the state information of the memory block.
And after receiving the application for changing the memory block state table, the dynamic memory allocation module reads the information of the changed memory block state table.
And writing the starting address of the memory block into a cache address field of the memory block state table.
The memory block state table includes a cache address field, a time-to-live field, an idle state field, and a write completion signal field.
The memory block lifetime field of the memory block status table is set to 1.
And setting the idle state field of the memory block state table to be 0.
The write complete signal field of the memory block status table is set to 0.
Step 9, responding to the read request.
The output port sends a request to the scheduler module to read the data.
The output port writes the memory block address to be read into the request buffer.
And step 10, collision detection.
The scheduler module reads the memory block start address of the request buffer, and sends the memory block start address to the dynamic memory allocation module.
The dynamic memory allocation module takes the initial address of the memory block as a read address, and reads the information of the memory block from the memory block state table.
If the write completion field of the memory block state table is 0, the dynamic memory allocation module sends the memory block start address to the data sending module.
Step 11, reading the data block.
And the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus.
And sending an application for updating the idle cache address to the dynamic memory allocation module.
And step 12, updating the idle cache address.
This step is described in further detail below with reference to fig. 4.
The dynamic memory allocation module changes the memory block state table.
The method for changing the memory block state table by the dynamic memory allocation module comprises the following steps:
And 2, judging whether the value of the survival time field of the memory block state table is 0, if so, executing the third step, and otherwise, executing the fourth step.
And 3, setting a memory block recycling field of the memory block state table to be 0 to indicate that the memory block is recycled.
And 4, setting a memory block recycling field of the memory block state table to be 1, wherein the memory block recycling field indicates that the memory block is not recycled.
And if the value of the memory block recovery field of the memory block state table is 1, writing the initial address of the memory block into the first-in first-out queue of the idle memory block.
Claims (7)
1. A low-delay data packet buffer device for switching equipment comprises a scheduler module, an idle memory block first-in first-out queue module, a memory block state table module, a data receiving module, a buffer module and a data sending module; the device is characterized by also comprising a data packet aggregation module and a dynamic memory allocation module; the scheduler module is respectively connected with the data packet aggregation module and the dynamic memory allocation module through a control bus, the dynamic memory allocation module is respectively connected with the memory block state table module and the idle memory block first-in first-out queue module through the control bus, and the data packet aggregation module is connected with the data receiving module through a data bus; the scheduler module is respectively connected with the data receiving module and the data sending module through a control bus; the data receiving module and the data sending module are connected with the cache region module interface through a data bus; wherein:
the data packet aggregation module is used for setting an aggregation counter to zero when initializing; receiving a write-in application of a data packet, and respectively extracting a destination port number and an effective length of the data packet from the write-in application; numbering the queue number sequence of the data packet by using a binary numerical value sequence of a destination port number, and writing the numbered queue number sequence into a queue number field of a first-in first-out queue of the aggregated block information; when the data packets are aggregated, taking the binary number value of the number of bytes occupied by the row storage space of the DRAM as the aggregation upper limit value; taking the binary value of the quotient of the system bandwidth of the data packet cache device and the number of bytes in the row storage space as the upper counting limit value of the aggregation counter; a merging module in the data packet aggregation module reads the data packet input by the input port and writes the data packet into an aggregation block memory; the merging module acquires the byte number in the aggregated block memory by using a byte number calculation method; judging whether the byte number in the aggregation block memory reaches an aggregation upper limit value, and if so, applying for a cache space; otherwise, continuing to write the data packet into the aggregation block memory; judging whether the count value of the aggregation counter is greater than the upper limit value of the count of the aggregation counter, and if so, applying for a cache space; otherwise, after the count value of the aggregation counter is added by 1, applying for a cache space until the count value reaches the upper limit value of the count of the aggregation counter; the merging module stops writing data packets into the aggregation block memory and sets an aggregation counter to be zero; adding 1 to the numerical value in the number field of the aggregation block information FIFO queue; writing the byte number in the aggregation block memory into an effective length field of an aggregation block information first-in first-out queue; sending a write request application to a scheduler module;
the scheduler module is used for reading the aggregation block information of the aggregation block information first-in first-out queue; taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the idle memory block first-in first-out queue; writing the initial address of the memory block into a cache address field of an aggregation block information first-in first-out queue; receiving a write request sent by a data packet aggregation module, acquiring a memory block address from an idle memory block first-in first-out queue module, and allocating a cache address for an aggregated data packet; reading the starting address of the memory block of the request buffer, and sending the starting address of the memory block to the dynamic memory allocation module;
the dynamic memory allocation module is configured to set a memory block state table entry address during initialization, where a high bit of the address indicates a queue number and a low bit of the address indicates a memory block label; taking the hexadecimal numerical sequence of the product value of the state table entry address of the memory block and the byte number of the row storage area as the initial address sequence of the memory block in the cache area; sequentially writing the initial address sequence of the memory block in each cache region into a first-in first-out queue module of the idle memory block; after receiving the application for changing the memory block state table, writing the effective length of the aggregated block into an aggregated block effective length field of the memory block state table; writing the initial address of the memory block into a cache address field of a memory block state table; adding 1 to a memory block survival time field of a memory block state table; setting a memory block recovery state field of a memory block state table to be 0; setting a write completion field of the memory block state table to 0; for changing the memory block state table; if the value of the memory block recovery field of the memory block state table is 1, writing the starting address of the memory block into a first-in first-out queue of the idle memory block, and using the starting address of the memory block as a read address to read the information of the memory block from the memory block state table; if the write completion field of the memory block state table is 0, sending the initial address of the memory block to the data sending module;
the memory block state table module is used for storing the occupation condition, the effective bytes, the idle state and the living space information of the DRAM memory block; subtracting 1 from the memory block survival time field of the memory block state table; setting a memory block recovery state field of a memory block state table to be 1;
the idle memory block first-in first-out queue module is used for storing the starting address of the unused memory block;
the data receiving module is used for reading the initial address of the memory block and the effective caching length from the aggregation block information first-in first-out queue; setting a write completion field of a memory block state table to 1; the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus; sending an application for changing a memory block state table to a dynamic memory allocation module;
the data sending module is used for reading the starting address of the memory block of the request buffer; the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus; sending an idle cache address updating application to a dynamic memory allocation module;
and the buffer area module is used for storing the data packet.
2. The packet low-latency buffering method for the switch device of claim 1, wherein the packet is aggregated and buffered in the entire line memory area of the memory, and the dynamic allocation is performed on the memory blocks, the method includes the following specific steps:
(1) initialization:
(1a) the buffer area module sets all address spaces of the storage area of the buffer area module to zero;
(1b) setting an aggregation counter in a data packet aggregation module to zero;
(2) dividing the memory blocks:
(2a) the dynamic memory allocation module sets a memory block state table entry address, wherein the high order of the address represents a queue number, and the low order of the address represents a memory block label;
(2b) the dynamic memory allocation module uses a binary numerical value sequence of a product value of the state table entry address of the memory block and the byte number of the row storage area as a memory block initial address sequence of a cache area;
(2c) sequentially writing the initial address sequence of the memory block in each cache region into a first-in first-out queue module of the idle memory block;
(3) reading data packet information:
(3a) the data packet aggregation module receives a writing application of a data packet, and respectively extracts a destination port number of the data packet and an effective length of the data packet from the writing application;
(3b) numbering the queue number sequence of the data packet by using a binary numerical value sequence of a destination port number, and writing the numbered queue number sequence into a queue number field of a first-in first-out queue of the aggregated block information;
(4) aggregating data packets:
(4a) taking a binary number value of the number of bytes occupied by a row memory space of a Dynamic Random Access Memory (DRAM) as an aggregation upper limit value;
(4b) taking the binary number value of the quotient of the bandwidth of the cache device and the number of bytes in the row storage space as the upper limit value of the counting of the aggregation counter;
(4c) a merging module in the data packet aggregation module reads the data packet input by the input port and writes the data packet into an aggregation block memory;
(4d) the merging module acquires the byte number in the aggregated block memory by using a byte number calculation method;
(4e) judging whether the number of bytes in the aggregation block memory reaches an aggregation upper limit value, if so, executing the step (5); otherwise, executing the step (4 f);
(4f) judging whether the count value of the aggregation counter is larger than the upper limit value of the count of the aggregation counter, if so, executing the step (5); otherwise, executing the step (4 g);
(4g) adding 1 to the count value of the aggregation counter and then executing the step (4 f);
(5) applying for a cache space:
(5a) the merging module stops writing data packets into the aggregation block memory and sets an aggregation counter to be zero;
(5b) adding 1 to the numerical value in the number field of the aggregation block information FIFO queue;
(5c) writing the byte number in the aggregation block memory into an effective length field of an aggregation block information first-in first-out queue;
(5d) the data packet aggregation module sends a write request application to the scheduler module;
(6) allocating a cache address:
(6a) the scheduler module reads the aggregation block information of the aggregation block information first-in first-out queue;
(6b) taking the aggregation block queue number and the serial number as read addresses, and reading the corresponding memory block starting address from the idle memory block first-in first-out queue;
(6c) writing the initial address of the memory block into a cache address field of an aggregation block information first-in first-out queue;
(7) moving the data packet:
(7a) the data receiving module reads the initial address of the memory block and the effective cache length from the aggregation block information first-in first-out queue;
(7b) the data receiving module sets a write completion field of the memory block state table to be 1;
(7c) the data receiving module outputs the aggregation block to a cache region corresponding to the starting address of the memory block through a data bus;
(7d) sending an application for changing a memory block state table to a dynamic memory allocation module;
(8) updating the state information of the memory blocks:
(8a) after receiving the application for changing the memory block state table, the dynamic memory allocation module writes the effective length of the aggregated block into an aggregated block effective length field of the memory block state table;
(8b) writing the initial address of the memory block into a cache address field of a memory block state table;
(8c) setting a memory block survival time field of a memory block state table to be 1;
(8d) setting a memory block idle state field of a memory block state table to be 0;
(8e) setting a write completion field in a memory block state table to 0;
(9) responding to the read request:
(9a) the output port sends a request for reading data to the scheduler module;
(9b) the output port writes the memory block address to be read into the request buffer;
(10) and (3) detecting a conflict:
(10a) the scheduler module reads the starting address of the memory block of the request buffer and sends the starting address of the memory block to the dynamic memory allocation module;
(10b) the dynamic memory allocation module takes the initial address of the memory block as a read address and reads the information of the memory block from the memory block state table;
(10c) if the write completion field of the memory block state table is 0, the dynamic memory allocation module sends the initial address of the memory block to the data sending module;
(11) reading the data block:
(11a) the data sending module outputs the aggregation block to the outside of the cache device from the cache region corresponding to the starting address of the memory block through a data bus;
(11b) sending an idle cache address updating application to a dynamic memory allocation module;
(12) and updating the idle cache address:
(12a) the dynamic memory allocation module changes a memory block state table;
(12b) and if the value of the memory block recovery field of the memory block state table is 1, writing the initial address of the memory block into the first-in first-out queue of the idle memory block.
3. The method as claimed in claim 2, wherein the write request for the packet in step (3a) includes an input port field, a destination port field, and a buffer valid length field.
4. The packet low-latency buffering method for the switching device according to claim 2, wherein the byte number calculating method in step (4d) comprises the following steps:
firstly, clearing a length register;
secondly, the length value of the currently received data packet is registered in a length register;
and thirdly, adding the length value in the extracted length register with the length value of the currently received data packet, registering the addition result in the length register, and taking the value in the length register as the byte number of the aggregated data packet.
5. The method according to claim 2, wherein the aggregation block information in step (6a) includes an aggregation block queue number, an aggregation block number, an effective length, and a memory block start address.
6. The packet low-latency buffering method for the switch device according to claim 2, wherein the memory block status table in step (8a) includes a buffer address field, an aggregation block valid length field, a time-to-live field, an idle status field, and a write completion field.
7. The method according to claim 2, wherein the step (12a) of the dynamic memory allocation module modifying the memory block status table comprises the following steps:
firstly, after receiving an application for updating an idle cache address, a dynamic memory allocation module subtracts 1 from a memory block lifetime field of a memory block state table;
secondly, judging whether the value of the survival time field of the memory block state table is 0, if so, executing a third step; otherwise, executing the fourth step;
thirdly, setting a memory block recovery field of the memory block state table to be 0 to indicate that the memory block is recovered;
and fourthly, setting a memory block recycling field of the memory block state table to be 1, wherein the memory block recycling field indicates that the memory block is not recycled.
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| CN111090601A (en) * | 2019-12-07 | 2020-05-01 | 苏州浪潮智能科技有限公司 | Multifunctional USB control method, system, terminal and storage medium based on BMC chip |
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