CN110815229A

CN110815229A - Stacking robot driving method and driving system

Info

Publication number: CN110815229A
Application number: CN201911140488.7A
Authority: CN
Inventors: 郭奔; 周小忠; 邵长岭; 李汉莹; 秦华; 朱辉平; 胡晓军
Original assignee: China Tobacco Zhejiang Industrial Co Ltd
Current assignee: China Tobacco Zhejiang Industrial Co Ltd
Priority date: 2019-11-20
Filing date: 2019-11-20
Publication date: 2020-02-21

Abstract

The invention discloses a palletizing robot driving method and a palletizing robot driving system, which comprise an ARM module and an FPGA module, wherein the ARM module is responsible for carrying out instruction or data interaction with an upper computer, the FPGA module is used for carrying out motor control signal transmission and grating signal processing, and the function of unpacking and palletizing smoke boxes is realized through modules such as motor signal control, grating closed loop feedback signal processing and a limit switch. In the palletizing robot based on the framework, the ARM compiles a program downloaded from a serial port, the upper computer sends a reconfiguration command and configuration data through the reconfigurable design of the upper computer, the ARM, a configuration chip and the FPGA, the configuration chip is rewritten through the ARM control to realize the control of 2 FPGAs, and finally an interface board of a drive card respectively controls X, Y, Z, A, B, C six-axis servo motors.

Description

Stacking robot driving method and driving system

Technical Field

The invention belongs to the technical field of robot driving, and particularly relates to a robot palletizer driving method and system.

Background art:

the stacking is to stack materials on a tray according to a certain rule and order so as to realize the logistics activities of transportation, loading, unloading, storage and the like of the materials. The cigarette box unpacking and stacking robot for the cigarette shred production line mainly is a robot which is used for separating the external packages of cut cigarette packets, transmitting and classifying and stacking paper boxes, plastic belts and other ribbons in a certain order and finishing the automatic unpacking and stacking functions of the cigarette boxes. At present, the widely applied robot palletizer driving cards are mainly divided into two types. The first type is a PC-based control system, a motion control card is inserted into a computer to take charge of the kinematic analysis and the trajectory planning algorithm of the robot and control the motor motion, and a software part is mainly realized based on a high-level programming language of the PC. But the defects of the method are that the method can not adapt to the modification requirement of the bottom layer drive, the transportability, the modification and modification are poor, the price is high, and a German KUKA palletizing robot is a product with the framework; the second type is based on a PLC control system, the hardware of the PLC control system is mainly composed of a PLC controller, the motor motion is controlled by means of a strong I/O control function, and a friendly HMI is designed by utilizing configuration software.

Disclosure of Invention

The invention aims to provide a robot palletizer driving method and a robot palletizer driving system, which aim to overcome the defect that the robot palletizer in the prior art is low in control precision.

The technical scheme of the invention is realized by the following steps:

in a first aspect, a robot palletizer driving method is provided, which comprises the following steps:

the microprocessor receives a control instruction of the upper computer, and control data are obtained after analysis;

the microprocessor sends the control data to the programmable device;

the motor driver reads the control data in the programmable device to control the motor to operate;

the motor motion controller monitors the motor running state and sends the running state information to the microprocessor;

the microprocessor uploads the running state information to the upper computer, and the upper computer sends out a control instruction according to the running state of the motor.

With reference to the first aspect, further, the method for sending the control data to the motor register by the microprocessor includes the following steps:

the microprocessor writes the control data to the programmable device;

the programmable device stores the control data in a motor register.

With reference to the first aspect, further, the operation control method of the motor includes the steps of:

the programmable device receives control data sent by the microprocessor and configures a relevant motor register according to the content of the control data;

the motor driver reads motor pulses and direction signals generated in the motor register to control the motor to operate;

the motor motion controller monitors the running state of the motor in real time and feeds the running state information of the motor back to the microprocessor;

the microprocessor judges whether the running state of the motor meets the regulations or not, and if yes, the running state is undetermined;

if not, the control data is sent out automatically according to the state type or uploaded to an upper computer for processing.

With reference to the first aspect, further, the control command includes one or more of an acceleration/deceleration movement command, a linear interpolation command, a fast stop command, and a Z-phase positioning and zeroing command.

With reference to the first aspect, further, the operation state information includes one or more of a position of each shaft motor, a real-time operation speed, and response information.

In a second aspect, there is provided a palletizing robot driving system comprising:

an upper computer;

the microprocessor module is bidirectionally connected with the upper computer, receives and analyzes a control instruction sent by the upper computer, and uploads control data to the upper computer;

the programmable device module is connected with the microprocessor module and used for storing control data sent by the microprocessor;

the motor driving module is connected with the programmable device module, reads control data and controls a motor connected with the programmable device module to operate;

and the motor motion controller module is connected with the microprocessor module and the motor, monitors the operation of the motor and sends operation information to the microprocessor module.

With reference to the second aspect, further, the microprocessor module and the programmable device module are connected through a communication module, where the communication module includes one or more of a data bus, an address bus, and a control bus.

With reference to the second aspect, further, the system further includes a power conversion module, where the power conversion module includes one or more of a 24V to 5V circuit module, a 5V to 3.3V circuit module, a 5V to 1.8V circuit module, and a 5V to 1.2V circuit module.

With reference to the second aspect, the microprocessor module further includes an ARM chip, and the programmable device module includes an FPGA module 1 and an FPGA module 2 that respectively control a plurality of sets of motors.

With reference to the second aspect, further, the motor includes at least six motors forming a servo motor for controlling X, Y, Z, A, B, C six directions.

The invention has the advantages that: the invention selects ARM + FPGA as the core and utilizes the reconfigurable design technology of FPGA to construct, thus having strong modifiability and portability; the LinuxNC real-time operating system can be implanted to ensure the real-time performance of the device operation, and a user-defined IP core can be written according to specific requirements, so that required specific functions can be freely added, and meanwhile, the bottom layer drive modification is facilitated, so that the system has better expandability and maintainability; the FPGA and ARM chips have superior product performance and reliability, and have higher performance-price ratio; due to the fact that good, standard and open software and hardware interfaces are selected, the control flexibility characteristic is good.

Drawings

Fig. 1 shows a control structure of a palletizing robot according to the present invention.

Fig. 2 is a schematic diagram of the drive control scheme of the ARM + FPGA of the present invention.

Fig. 3 is a schematic structural diagram of the present invention.

Fig. 4 is a schematic diagram of a 24V to 5V circuit module according to the invention.

Fig. 5 is a schematic diagram of a 5V to 3.3V circuit module according to the invention.

Fig. 6 is a schematic diagram of a 5V to 1.8V circuit module according to the invention.

Fig. 7 is a schematic diagram of a 5V to 1.2V circuit module according to the invention.

FIG. 8 is a schematic diagram of the JTAG interface circuit of the ARM chip of the present invention.

FIG. 9 is a schematic diagram of an oscillation circuit of the ARM chip of the present invention.

FIG. 10 is a schematic diagram of an ARM chip reset circuit according to the present invention.

FIG. 11 is a schematic diagram of an ISP interface and a power-on start-up circuit of an ARM chip according to the present invention.

Fig. 12 is a schematic diagram of a configuration circuit of the FPGA chip according to the present invention.

FIG. 13 is a schematic diagram of an oscillation circuit of the FPGA chip of the present invention.

FIG. 14 is a schematic diagram of an ARM and FPGA communication module of the present invention.

FIG. 15 is a schematic diagram of an external memory circuit according to the present invention.

FIG. 16 is a schematic diagram of a communication circuit with a host computer according to the present invention.

Fig. 17 is a schematic diagram of a motor drive interface circuit of the present invention.

Fig. 18 is a schematic diagram of a grating feedback signal circuit of the present invention.

Fig. 19 is a software system configuration of the present invention.

Figure 20 is a flowchart of the ARM main routine of the present invention.

Fig. 21 is a flowchart of a linear interpolation according to the present invention.

Fig. 22 is a flowchart of acceleration/deceleration control according to the present invention.

Fig. 23 is a flowchart of a point location movement routine of the present invention.

FIG. 24 is a flow chart of an implementation of a fast stop instruction of the present invention.

FIG. 25 is a flowchart of a process for a Z-phase fix-back instruction of the present invention.

FIG. 26 is a flow chart of ARM and FPGA communication according to the present invention.

Fig. 27 is a control flow diagram of reconstruction software according to the present invention.

Detailed Description

In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.

As shown in fig. 1, a palletizing robot structure suitable for the invention is as follows: a X, Y, Z, A, B, C six-axis robot palletizer driving card based on an Altera EP2C8 series FPGA chip and an ARM7TDMI-S series LPC2294 chip is applied to a cigarette box unpacking and palletizing robot in a cigarette making production line. The ARM is responsible for carrying out instruction or data interaction with the host computer, and FPGA carries out motor control signal transmission and grating signal's processing, realizes the function of unpacking the pile up neatly to the smoke box through modules such as motor signal control, grating closed loop feedback signal processing and limit switch. In the palletizing robot based on the framework, the ARM compiles a program downloaded from a serial port, the upper computer sends a reconfiguration command and configuration data through the reconfigurable design of the upper computer, the ARM, a configuration chip and the FPGA, the configuration chip is rewritten through the ARM control to realize the control of 2 FPGAs, and finally an interface board of a drive card respectively controls X, Y, Z, A, B, C six-axis servo motors.

As shown in fig. 2, the ARM is responsible for performing instruction or data interaction with the upper computer, and the FPGA transmits a motor control signal and processes a grating signal. And after receiving the instruction and the data, the ARM analyzes the instruction, sends the instruction to the FPGA, reads and writes the data in the FPGA according to a certain frequency, and uploads the data to the upper computer. In the system, the FPGA is used as a data memory extended by the ARM, and control data are written into the FPGA in a three-bus (data bus, address bus and control bus) mode. The FPGA mainly realizes motion control of 6 motors, processes feedback signals of a grating, an encoder, a limit switch and the like, realizes S-curve acceleration and deceleration in the process of controlling the operation of each shaft, stops the operation of the motors after the shafts run to a specified position, and simultaneously sends an interrupt signal to the ARM. The system adopts two pieces of FPGA, the FPGA1 module is responsible for controlling No. 1-3 motors, and the FPGA2 module is responsible for controlling No. 4-6 motors.

The design function of the ARM processor is as follows: (1) receiving an upper computer control instruction through an RS232 serial port; (2) analyzing the control instruction to generate control data of the FPGA; (3) configuring a motor register in the FPGA through a control bus, an address bus and a data bus; (4) reading and writing motor operation data information of the FPGA; (5) and running information feedback. In the running process of the system, the motion controller uploads real-time running information (the position, the real-time speed and response information of each shaft motor) to the upper computer; (6) and prompting the running state. Starting-up prompt, operation fault prompt, operation completion prompt and the like.

The FPGA function and the realization logic (1) realize the function of communicating with the ARM microprocessor; (2) receiving a motor control signal sent by an ARM processor, configuring a relevant motor register according to a control instruction, generating a pulse and a direction signal of a motor, and sending the pulse and the direction signal to a stepping motor driver to drive the motor to operate; (3) in the running process of the motor, the S-curve control of acceleration and deceleration is realized, so that the motor can run stably; (4) the motor is accurately positioned. Receiving a closed-loop signal generated by a grating, carrying out four-subdivision and direction discrimination on the signal, and calculating to obtain motor displacement information, thereby realizing closed-loop control on displacement and carrying out accurate positioning; (5) monitoring the running state of the motor, and quickly feeding back information such as the running state of the motor to the ARM processor, wherein the ARM processor takes different measures according to different motor states; (6) and (5) limiting and protecting.

As shown in fig. 3, the six-axis cigarette box unpacking and stacking robot driving card based on the ARM and the FPGA comprises a power supply conversion module, an ARM module, an FPGA module, an ARM and FPGA communication module, an external memory module, a communication module with an upper computer, a motor driving interface circuit module and a grating feedback signal circuit module; the power supply conversion module comprises a 24V-to-5V circuit, a 5V-to-3.3V circuit, a 5V-to-1.8V circuit and a 5V-to-1.2V circuit; the ARM module consists of a JTAG interface circuit, an oscillation circuit, a reset circuit, an ISP interface and a power-on starting circuit; the FPGA module comprises a configuration circuit and an oscillating circuit.

As shown in fig. 4, in the 24V to 5V circuit module, an LM2596 chip is used for voltage conversion, and a 4007 diode can prevent reverse voltage insertion, recover a fuse, and perform overcurrent protection, thereby enhancing the safety and reliability of the whole circuit. The inductance and capacitance of the peripheral circuit is used for filtering interference.

As shown in fig. 5, 6 and 7, the circuit module from 5V to 3.3V, the circuit module from 5V to 1.8V and the circuit module from 5V to 1.2V adopt the SPX1117 chip to perform voltage conversion, and the 0.1uF ceramic capacitor and the 10uF tantalum capacitor reduce the influence of power supply disturbance and high-frequency noise on the whole circuit.

As shown in FIG. 8, the ARM chip JTAG interface circuit module adopts a standard 20-pin JTAG emulation debugging interface of ARM company.

As shown in FIG. 9, the ARM chip oscillation circuit module adopts an 11.059M external crystal oscillator, and ARM chip clock signals are generated by an internal crystal oscillator and an externally connected crystal oscillator.

As shown in fig. 10, the ARM chip reset circuit uses CAT809R as a power supply monitoring chip, when the system is powered on, the state of the reset signal remains valid for at least 140ms after the reset signal rises to be greater than the threshold, and a low level signal is generated when the power supply voltage is lower than + 2.63V.

As shown in fig. 11, the ISP selection signal is controlled by pin P0.14 in the ISP interface of the ARM chip and the power-on start circuit module, and BOOT0\ BOOT1 is used as the power-on start selection.

As shown in fig. 12, the FPGA chip configuration circuit mainly includes seven signals, i.e., nCE, nCS, CONFIG-DONE, nSTATUS, ncofig, DATAO, and CLK, in the circuit configured in an active manner by using the EPCS4SI8 dedicated configuration chip. The nCE needs a pull-down resistor with the resistance value of 1K, and the nSTATUS, CONFIG-DONE and nCONFIG signal lines are pulled up to a power supply part with the resistance value of 10K by a resistor to 3.3V, so that the configuration pins are in a correct level state when JTAG configuration or normal use is carried out. In the JTAG configuration circuit, TCK is required to be pulled up to 3.3V, and TMS and TDI access resistors with 10K resistance are pulled down to the ground so as to ensure normal configuration and work of the chip. The JTAG interface may be configured for download using the download line of ALTERA via the Quartus II tool.

As shown in fig. 13, the FPGA chip oscillation circuit uses a 40MHZ active crystal oscillator as a clock input of the chip, the magnetic bead (FB305) and the two patch capacitors are used to reduce the influence of source disturbance on the crystal oscillator, and the 33 ohm resistor is anti-matching, so that the output of the crystal oscillator is optimal as much as possible.

As shown in fig. 14, in the ARM and FPGA communication module, the FPGA serves as a data storage of the ARM extension, and writes data to the FPGA in a three-bus (data bus, address bus, and control bus) manner. LPC2294 is allocated to FPGA1 and FPGA2 using BANK1 and BANK2 address spaces of the external memory interface. Chip selection signals CS0 and CS1 are distributed and connected with chip selection ends of the FPGA1 and the FPGA 2; the LPC2294 uses 16 as data buses D0-D15 to connect with corresponding 16-bit data line pins of the FPGA1 and the FPGA 2; OE and WE external control buses and write signals of the LPC2294 are respectively connected with read-write signal lines of the two FPGAs; LPC2294 uses a 16-bit data bus, with the other addresses removed A0, connected to the A0-A9 address buses of FPGA1 and FPGA2 using A1-A10.

As shown in fig. 15, the external memory module selects an AT24C64 chip to mainly store some parameter information, including pulse equivalent of six-axis servo motors, configuration confidence of the motion controller when leaving the factory, and the like, and accesses the information by using an I2C bus.

As shown in fig. 16, the communication module with the upper computer selects a MAX3232 chip to implement an RS-232 serial port communication mode.

As shown in fig. 17, the motor driving interface circuit module obtains a differential signal by using an AM26LS31 conversion chip to improve the anti-interference capability of the system, and supplies power by using a boost-to-5V circuit.

As shown in fig. 18, the grating feedback signal circuit module uses an MC3486 chip to perform differential-to-single-ended signal processing on the grating feedback signal, and the external I/O pin 3.3V voltage is converted by a 74LVT-H245 chip.

As shown in fig. 19, a software system of the six-axis cigarette box unpacking and palletizing robot driving card based on the ARM and the FPGA is composed of a linux xcnc core module, a self-developed bottom layer driver, an ARM and FPGA communication program, a reconfigurable software design module and an FPGA bus communication module.

The Linux NC is a set of computer software control system for machine control, and can be used for switching the motion mode of the numerical control component, loading and editing a G code, displaying the state of the numerical control component in real time and the like; the motion control module (EMCMOT) is the core of the Linux NC and is responsible for the core functions of the numerical control systems such as G code translation, interpolation operation, motion control and the like, and the module has high real-time requirement and needs to be operated in an ARM real-time kernel.

As shown in FIG. 20, ARM is a direct administrator of the motion controller as a virtual PLC. The PLC can complete the logic control function of the PLC on one hand, and can realize the motion control output function on the other hand. The former is mainly realized by PLC, and the latter sends motion control instructions to FPGA through an interface through PLC, and is completed by FPGA. After the ARM is implanted into the Linux NC system, the control of a main program is realized.

As shown in fig. 21, when the acceleration/deceleration motion command needs to be executed, the current coordinates and the coordinates of the end point are known, and a program for performing linear interpolation motion by dividing the execution time of the function related to the linux xcnc system call is executed.

As shown in fig. 22, when a linear interpolation command needs to be executed, in order to make the motor operate smoothly, particularly, the speed does not have too large sudden change in the starting and stopping stages, an acceleration and deceleration control program is often called.

As shown in fig. 23, linux xcnc outputs the jog motion control code to the self-developed underlying driver, and performs program compilation again, and the jog motion control flowchart is shown in the figure.

The self-development bottom layer drive mainly comprises a quick stop instruction, a Z-phase positioning return-to-zero instruction and other programs. As shown in fig. 24, after the fast stop command is triggered, the CPU sends the fast stop command to the FPGA, then waits for the response of the FPGA, and clears the flag bit currently in motion after receiving the signal that the motor has stopped. After receiving the command, the FPGA directly stops sending the PWM no matter what state the FPGA is in, marks the state identification as the stop state, and feeds back a stop signal to the CPU.

As shown in fig. 25, the Z-phase position return-to-zero command is used to determine that the current actual position of the motor cannot be determined when the system is just powered on, and the motor needs to be reset each time the control system is powered on. The Z-phase positioning return to zero is performed as follows: step 1: after the CPU receives the Z-phase positioning zero returning command, the PU controls and executes a point location movement instruction, the total number of movement steps is the total number of steps required by the motor to rotate for one circle, the direction is the forward direction, and the specific execution process is referred to the point location movement instruction; step 2: if the Z-phase signal is not received after the forward rotation is completed by half a turn, the CPU executes a point location motion instruction again, the number of the motion points is the total steps required by the motor to rotate by half a turn, the direction is reverse, and the specific execution process of the point location motion instruction is shown in the point location motion instruction; and step 3: if the CPU receives the Z-phase positioning signal when the motor moves in the forward direction, the CPU immediately sends a deceleration command to the FPGA until the FPGA stops sending pulses; and 4, step 4: after the step 3 is executed, if the CPU judges that the FPGA stops sending pulses, executing a point location motion instruction, wherein the total step number of the motion is the total step number required by 1/10 turns of the motor, the direction is reverse, and the specific execution process is shown in the point location motion instruction; and 5: in the process of executing the step 2 or the step 4, if the CPU receives the Z-phase positioning signal, the CPU immediately sends a deceleration command to the FPGA until the FPGA stops sending pulses; if the CPU does not receive the Z-phase positioning signal, repeating the step 2 or 4; step 6: after step 5 is executed, if the CPU determines that the FPGA stops sending pulses, the CPU executes the point location movement command, where the total number of steps of movement is the total number of steps required by 1/10 turns of the motor, and the direction is the forward direction. If the CPU receives the Z-phase positioning signal in the execution process, the CPU immediately sends a quick stop instruction to the FPGA, and Z-phase positioning is finished; if no Z-phase positioning signal is received, step 6 is repeated.

As shown in fig. 26, the communication module of the ARM and FPGA mainly sends the motion control command and related parameters to the dual-port RAM inside the FPGA responsible for motion control for the ARM to read the current related state of each axis motor.

As shown in fig. 27, in the reconfigurable software design block, the PC is the initiator of the reconfiguration command. When the system needs to upgrade (reconstruct) the hardware of the FPGA, the PC may send the new configuration data, rpd file (output file of the Quartus II project) and reconstruction command to the ARM through the serial port. ARM is the executor of reconstruction. Once the ARM receives the reconfiguration command and the configuration data sent by the upper computer, the ARM robs the FPGA of controlling the configuration chip, starts to control the configuration chip, and writes new data into the configuration chip. After the data writing of the EPCS configuration chip is finished, the ARM releases the control of the configuration chip, so that the FPGA regains the control right of the configuration chip to download the configuration data written at the last time.

It will be appreciated by those skilled in the art that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The embodiments disclosed above are therefore to be considered in all respects as illustrative and not restrictive. All changes which come within the scope of or equivalence to the invention are intended to be embraced therein.

Claims

1. A robot palletizer driving method, characterized in that the method comprises the following steps:

the microprocessor sends the control data to the programmable device;

2. The robot palletizer driving method according to claim 1, wherein: the method for the microprocessor to send the control data to the motor register comprises the following steps:

the microprocessor writes the control data to the programmable device;

the programmable device stores the control data in a motor register.

3. The robot palletizer driving method according to claim 1, wherein: the operation control method of the motor comprises the following steps:

the microprocessor judges whether the running state of the motor meets the specification or not, if so, the running state is undetermined,

4. The robot palletizer driving method according to claim 1, wherein: the control command comprises one or more of an acceleration and deceleration movement command, a linear interpolation command, a quick stop command and a Z-phase positioning zero returning command.

5. The robot palletizer driving method according to claim 1, wherein: the running state information comprises one or more of the position of each shaft motor, the real-time running speed and response information.

6. A palletizing robot driving system, comprising:

an upper computer;

7. Robot palletizer drive system according to claim 5, characterized in that: the microprocessor module is connected with the programmable device module through a communication module, and the communication module comprises one or more of a data bus, an address bus and a control bus.

8. Robot palletizer drive system according to claim 5, characterized in that: the system further comprises a power conversion module, wherein the power conversion module comprises one or more of a 24V-to-5V circuit module, a 5V-to-3.3V circuit module, a 5V-to-1.8V circuit module and a 5V-to-1.2V circuit module.

9. The robot palletizer drive system as in claim 4, wherein: the microprocessor module comprises an ARM chip, and the programmable device module comprises an FPGA module 1 and an FPGA module 2 which respectively control a plurality of groups of motors.

10. The robot palletizer drive system as in claim 4, wherein: the motors comprise servo motors composed of at least six motors and used for controlling X, Y, Z, A, B, C six directions.