CN104597802A - Super-high sampling rate of reproducible data collection system - Google Patents
Super-high sampling rate of reproducible data collection system Download PDFInfo
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- CN104597802A CN104597802A CN201410701064.4A CN201410701064A CN104597802A CN 104597802 A CN104597802 A CN 104597802A CN 201410701064 A CN201410701064 A CN 201410701064A CN 104597802 A CN104597802 A CN 104597802A
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Abstract
The invention provides a super-high sampling rate of reproducible data collection system. The super-high sampling rate of reproducible data collection system comprises an ADC (Analog To Digital Converter) chip, an embedded CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array) processing unit and a data storage, n clock signals are generated through a DCM (Digital Clock Management) unit of an FPGA, the different phases of clock signals are provided for an ADC during every time of data collection to implement different phases of data collection, different phases of data collection results are combined together in the FPGA finally to form a n times of ADC sampling rate of high sampling rate of data collection result together, the repeated collection is performed on every phase of data collection so as to perform the filter processing, and accordingly the noise can be eliminated and the performance of the data collection system can be further improved, wherein a value of the phase difference of the clock signals is the formula. According to the super-high sampling rate of reproducible data collection system, the high sampling rate of data collection on the low rate of ADC chip is implemented, the system control is simple, the requirements for the operational capability of the FPGA are low, the implementation is easy, and collected data are high in accuracy.
Description
Technical field
The present invention relates to a kind of data acquisition system (DAS), particularly a kind of superelevation sampling rate can playing data for broadcasting acquisition system.
Background technology
The develop rapidly of modern electronic technology, makes flush bonding processor performance constantly promote, such as current ARM series flush bonding processor, its performance not second to 1 year before PC processor.The flush bonding processor of these high speeds has derived increasing built-in type high speed data disposal system.But performance boost data being carried out to the modulus conversion chip of sample quantization but lags far behind the speed of processor performance lifting.Therefore how to realize at a high speed, accurately, the data collection data of big data quantity becomes key and the bottleneck place of modern embedded data disposal system.
Data acquisition unit usually adopt modulus conversion chip (ADC) to analog signal sampling quantize be converted to digital model after gather, and its sampling speed, namely sampling rate is just limited to the sampling rate parameter of modulus conversion chip.In order to realize superfast data acquisition, common way adopts polylith modulus conversion chip composition AD conversion array, every block conversion chip connects the sampling clock of out of phase, and then adopt FPGA the sampled result of different phase places to be combined, the sampled result of a synthesis high sampling rate, if the patent No. is method in the Chinese utility model patent of CN202033737U, be and utilize A/D converter time-interleaved that two sampling rates are 125MSPS to sample a road signal, achieve the sampling rate of 250MSPS.But this polylith AD conversion chip divides the way of phase acquisition to need polylith A/D chip and more FPGA pin, cost is higher and easily cause FPGA resource not enough.In addition performance, polylith A/D chip data acquisition system (DAS) also can cause between out of phase because of some parameter differences of each A/D chip certain amplitude and the difference of direct current biasing, thus causes the distorted signals of final synthesis larger.
Can playing data for broadcasting collection, refer to that data to be collected can repeat, namely can repeated acquisition, the data in a lot of embedded measurement application all have this characteristic, such as laser range finder.The present invention is directed to this data acquisition application scenario, propose a kind of low sampling rate modulus conversion chip that adopts and realize the method for high sampling rate data acquisition by repeatedly repeated acquisition.
Summary of the invention
The object of the present invention is to provide a kind of superelevation sampling rate can playing data for broadcasting acquisition system, comparatively large with the distorted signals that the modulus conversion chip solving the multiple low sampling rate of existing employing carries out existing for data sampling, be easy to the problem causing FPGA resource deficiency.
The second object of the present invention is, provides a kind of superelevation sampling rate can playing data for broadcasting acquisition system, to realize realizing the data acquisition of superelevation sampling rate by the modulus conversion chip of a low sampling rate by repeatedly repeated acquisition data.
For achieving the above object, the invention provides a kind of superelevation sampling rate can playing data for broadcasting acquisition system, comprise a modulus conversion chip, embedded type CPU, FPGA processing unit and data-carrier store, described FPGA processing unit comprises ADC interface module, multiphase clock generation module, data processing module, MIG memory interface module, cpu data module for reading and writing and CPU control register;
Described embedded type CPU is used in described CPU control register, writing acquisition phase signal and gathering commencing signal;
CPU control register is used for sending described acquisition phase signal and collection commencing signal to described multiphase clock generation module; Described multiphase clock generation module is used for producing according to the collection commencing signal received the clock signal that n phase is 2 π/n, and choose this n clock signal Zhong i-th road signal input described modulus conversion chip according to the acquisition phase signal received, i, n are positive integer, and 1≤i≤n;
Described modulus conversion chip is used for carrying out data acquisition according to the i-th tunnel clock signal received and the i-th circuit-switched data gathered being inputted described ADC interface module;
The i-th circuit-switched data that described ADC interface module is used for gathering carries out data buffer storage and clock synchronous process, and the i-th circuit-switched data after process is inputted described data processing module;
Described MIG memory interface module is used for carrying out read-write operation to the i-th circuit-switched data in described data-carrier store;
Described data-carrier store is for storing the i-th circuit-switched data of described MIG memory interface module write;
Described data processing module is used for the i-th circuit-switched data after to the process of input and carries out the i-th circuit-switched data that filtering noise reduction process obtains filtering noise reduction, the i-th circuit-switched data from data-carrier store that i-th circuit-switched data of filtering noise reduction and described MIG memory interface module read is weighted average calculating operation by described data processing module simultaneously, obtain the i-th circuit-switched data after weighted mean, and by described MIG memory interface module by the i-th circuit-switched data write data-carrier store after weighted mean;
Wherein, described modulus conversion chip is low rate ADC modulus conversion chip, during each data acquisition, described embedded type CPU controls described modulus conversion chip by described FPGA processing unit and completes the n circuit-switched data collection of n clock signal and the n circuit-switched data obtained is write data-carrier store respectively;
Described cpu data module for reading and writing is used for the n circuit-switched data in described data-carrier store to press phase combination, obtains final high resolving power sampled data, and by CPU control register by final high resolving power sampled data data input embedded type CPU.
Preferably, described multiphase clock generation module comprises a Selecting phasing register and a DCM Clock Managing Unit, described DCM Clock Managing Unit is used for producing according to the collection commencing signal received the clock signal that n phase is 2 π/n, and this n road clock signal is inputted described Selecting phasing register; This n clock signal Zhong i-th tunnel clock signal is inputted described modulus conversion chip according to the acquisition phase signal received by described Selecting phasing register root.
Preferably, data-carrier store comprises n data storage area, is respectively phase place 0 data storage area to phase place n data storage area; Wherein, the data of phase place i data storage area for writing under storing the i-th tunnel clock signal effect.
Preferably, the weighted mean operation that described data processing module carries out is specially: the data newly gathered by phase place i are multiplied with coefficient w0, the data of the phase place i stored by described data-carrier store are multiplied with w1, data after being multiplied by two-way are again added, and namely obtain the new data of the phase place i after weighted mean.
System design scheme principle of the present invention is the clock signal being produced n phase 2 π/n by the DCM unit of FPGA, each time during data acquisition to the clock signal of ADC out of phase, realize the data acquisition of out of phase, finally in FPGA, the data acquisition results of out of phase is combined, common composition ADC sampling rate n high sampling rate data acquisition results doubly.Wherein, repeated acquisition is carried out repeatedly to carry out filtering process to the data acquisition of each phase place, can stress release treatment, the further performance of raising data acquisition system (DAS).
This programme is primarily of the modulus conversion chip of a low rate, FPGA, data-carrier store and embedded type CPU form jointly, and wherein ADC completes the sample quantization of data, FPGA has been responsible for main control and data processing operation, and the data of storage of collected are responsible for by data-carrier store.The modulus conversion chip that this system achieves a low rate carries out the work of high sampling rate data acquisition, and Systematical control is simple, requires lower to the arithmetic capability of FPGA, be easy to realize, and the data precision gathered is higher.
Accompanying drawing explanation
Fig. 1 is basic principle schematic of the present invention;
Fig. 2 is that the superelevation sampling rate of the preferred embodiment of the present invention playing data for broadcasting acquisition system can form schematic diagram;
Fig. 3 A is the multiphase clock module composition structural representation of the preferred embodiment of the present invention;
Fig. 3 B forms clock signal graph of a relation corresponding to structure with the multiphase clock module in Fig. 3 A;
Fig. 4 is the weighted mean processing procedure schematic diagram of data processing module.
Embodiment
For better the present invention being described, hereby with a preferred embodiment, and accompanying drawing is coordinated to elaborate to the present invention, specific as follows:
Shown in Figure 1, carry out 4 samplings in each data acquisition.When adopting the modulus conversion chip ADC of low sampling rate to gather data, first time gathers sampled point corresponding to arrow that label in Fig. 1 is 1, i.e. A, E and I point; The sampled point of the corresponding arrow of second time sampled acquisition label 2, i.e. B, F, J point; The sampled point of the corresponding arrow of third time sampled acquisition label 3, i.e. C, G point, the sampled point of the 4th the corresponding arrow of sampled acquisition label 4, i.e. D, H point.By FPGA, the result that these four times are sampled is combined, just obtain the sampled signal of four sampling rates of A, B, C, D, E, F, G, H, I and J in upper figure.The present embodiment is sampled with 4 clock signals, is divided into 4 samplings by the clock of 4 groups of phase 90 degree, and collecting corresponding to label in Fig. 1 is respectively 1, the sampled point that the arrow of 2,3,4 is corresponding, combine in FPGA again, just can realize the high speed acquisition of 4 sampling rates.
The superelevation sampling rate that the present embodiment provides can playing data for broadcasting acquisition system as shown in Figure 2, this system comprises a modulus conversion chip 10, embedded type CPU 20, FPGA processing unit 30 and data-carrier store 40, FPGA processing unit 30 and comprises ADC interface module 31, multiphase clock generation module 32, data processing module 33, MIG memory interface module 34, cpu data module for reading and writing 35 and CPU control register 36; Wherein, multiphase clock generation module 32 comprises Selecting phasing register 321 and a DCM Clock Managing Unit 322.
During this system works, transmit acquisition phase signal by CPU control register 36 and gather commencing signal to multiphase clock generation module 32.As shown in Figure 3A, it is the clock signal of pi/2 that the DCM Clock Managing Unit 322 in multiphase clock generation module 32 produces 4 phase according to the collection commencing signal (clk_in) received, and by this 4 tunnel clock signal input phase mask register 321.This four roads signal as shown in Figure 3 B, is respectively phase place 0(clk 0), 90 degree, phase place (clk 90), 180 degree, phase place (clk 180) and 270 degree, phase place (clk 270) four tunnel clock signal.Selecting phasing register 321 inputs modulus conversion chip 10 and ADC interface module 31 according to these 4 the clock signal Zhong i-th tunnel clock signals (phase place is π i/2) of acquisition phase signal behavior received as ADC sampling clock.In the present embodiment, i is positive integer, and 1≤i≤4.
Modulus conversion chip 10 according to the i-th tunnel clock signal received with this clock signal for clock reference carries out data acquisition and the i-th circuit-switched data input ADC interface module 31 that will gather;
ADC interface module 31 carries out data buffer storage to the i-th circuit-switched data gathered, and combine according to received the i-th tunnel clock signal from multiphase clock generation module 32 and do clock synchronous process, and by the data input data processing module 33 after clock synchronous process.
The i-th circuit-switched data in MIG memory interface module 34 pairs of data-carrier stores 40 performs read-write operation.
The i-th circuit-switched data that data-carrier store 40 writes for store M IG memory interface module 34.
Data processing module 33 carries out to the i-th circuit-switched data after the clock synchronous process of input the i-th circuit-switched data that filtering noise reduction process obtains filtering noise reduction, i-th circuit-switched data of filtering noise reduction and the i-th circuit-switched data from data-carrier store 40 read by MIG memory interface module 34 are weighted average calculating operation by data processing module 33 simultaneously, obtain the i-th circuit-switched data after weighted mean, and the i-th circuit-switched data after weighted mean is write data-carrier store 40 by MIG memory interface module 34.
Wherein, modulus conversion chip 10 is the ADC modulus conversion chip of low rate, and the data sample rates of the ADC modulus conversion chip in the present embodiment is 125MSPS.Native system is adopted to carry out in the process of data acquisition, during each data acquisition, embedded type CPU 20 controls by FPGA processing unit 30 data acquisition that modulus conversion chip 10 completes 4 clock signals, and the data of obtain 4 kinds of outs of phase are write data-carrier store 40 respectively.
Embedded type CPU 20 sends and obtains data command to CPU control register 36, CPU control register 36 sending controling instruction is to cpu data module for reading and writing, by cpu data module for reading and writing 35 by the data that store in data-carrier store by phase combination, obtain final high resolving power sampled data, the sampling rate of this sampled data is 4 × 125MSPS=500 MSPS, and again by CPU control register 36, final high resolving power sampled data data are inputted embedded type CPU 20, namely complete data collection task once.
As shown in Figure 4, data-carrier store 40 comprises 4 data storage areas, is respectively phase place 0 data storage area, phase place 1 data storage area, phase place 3 data storage area and phase place 4 data storage area.Wherein, the data of phase place i data storage area for writing under storing the i-th tunnel clock signal effect.The weighted mean operation of data processing module 33 is specially the data newly gathered by phase place i and is multiplied with coefficient w0, the data of the phase place n stored by data-carrier store 40 are multiplied with w1, data after being multiplied by two-way are again added, and namely obtain phase place i(i-th tunnel processed) new data (the i-th circuit-switched data namely after weighted mean).Wherein, weighted value w0 and w1 can be arranged by embedded type CPU according to different demands, realizes noise reduction process flexibly.
Certainly, the present invention is not limited with above-described embodiment, and when specifically implementing, each data acquisition can carry out the data acquisition that n phase differential is the low sampling rate of the clock signal of 2 π/n, n be greater than 1 integer.Correspondingly, all the other device parameter performance also do not limit by above-described embodiment.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, any those skilled in the art is in the technical scope that the present invention discloses; the distortion do the present invention or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (4)
1. a superelevation sampling rate can playing data for broadcasting acquisition system, it is characterized in that, comprise a modulus conversion chip, embedded type CPU, FPGA processing unit and data-carrier store, described FPGA processing unit comprises ADC interface module, multiphase clock generation module, data processing module, MIG memory interface module, cpu data module for reading and writing and CPU control register;
Described embedded type CPU is used in described CPU control register, writing acquisition phase signal and gathering commencing signal;
CPU control register is used for sending described acquisition phase signal and collection commencing signal to described multiphase clock generation module; Described multiphase clock generation module is used for producing according to the collection commencing signal received the clock signal that n phase is 2 π/n, and choose this n clock signal Zhong i-th road signal input described modulus conversion chip according to the acquisition phase signal received, i, n are positive integer, and 1≤i≤n;
Described modulus conversion chip is used for carrying out data acquisition according to the i-th tunnel clock signal received and the i-th circuit-switched data gathered being inputted described ADC interface module;
The i-th circuit-switched data that described ADC interface module is used for gathering carries out data buffer storage and clock synchronous process, and the i-th circuit-switched data after process is inputted described data processing module;
Described MIG memory interface module is used for carrying out read-write operation to the i-th circuit-switched data in described data-carrier store;
Described data-carrier store is for storing the i-th circuit-switched data of described MIG memory interface module write;
Described data processing module is used for the i-th circuit-switched data after to the process of input and carries out the i-th circuit-switched data that filtering noise reduction process obtains filtering noise reduction, the i-th circuit-switched data from data-carrier store that i-th circuit-switched data of filtering noise reduction and described MIG memory interface module read is weighted average calculating operation by described data processing module simultaneously, obtain the i-th circuit-switched data after weighted mean, and by described MIG memory interface module by the i-th circuit-switched data write data-carrier store after weighted mean;
Wherein, described modulus conversion chip is low rate ADC modulus conversion chip, during each data acquisition, described embedded type CPU controls described modulus conversion chip by described FPGA processing unit and completes the n circuit-switched data collection of n clock signal and the n circuit-switched data obtained is write data-carrier store respectively;
Described cpu data module for reading and writing is used for the n circuit-switched data in described data-carrier store to press phase combination, obtains final high resolving power sampled data, and by CPU control register by final high resolving power sampled data data input embedded type CPU.
2. superelevation sampling rate according to claim 1 can playing data for broadcasting acquisition system, it is characterized in that, described multiphase clock generation module comprises a Selecting phasing register and a DCM Clock Managing Unit, described DCM Clock Managing Unit is used for producing according to the collection commencing signal received the clock signal that n phase is 2 π/n, and this n road clock signal is inputted described Selecting phasing register; This n clock signal Zhong i-th tunnel clock signal is inputted described modulus conversion chip according to the acquisition phase signal received by described Selecting phasing register root.
3. superelevation sampling rate according to claim 1 can playing data for broadcasting acquisition system, and it is characterized in that, data-carrier store comprises n data storage area, is respectively phase place 0 data storage area to phase place n data storage area; Wherein, the data of phase place i data storage area for writing under storing the i-th tunnel clock signal effect.
4. superelevation sampling rate according to claim 1 can playing data for broadcasting acquisition system, it is characterized in that, the weighted mean operation that described data processing module carries out is specially: the data newly gathered by phase place i are multiplied with coefficient w0, the data of the phase place i stored by described data-carrier store are multiplied with w1, data after being multiplied by two-way are again added, and namely obtain the new data of the phase place i after weighted mean.
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| CN105847714A (en) * | 2016-05-24 | 2016-08-10 | 中国科学院长春光学精密机械与物理研究所 | Delayed correction system for input image data of CMOS |
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| CN109738907A (en) * | 2019-03-13 | 2019-05-10 | 武汉海达数云技术有限公司 | Laser waveform data acquisition device and method |
| CN112462192A (en) * | 2020-11-04 | 2021-03-09 | 南京航空航天大学 | ADC frequency increasing system and method for aviation cable fault detection based on TDR technology |
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