CN106444352A - Method and system for measuring clock synchronization based on double buffer areas - Google Patents
Method and system for measuring clock synchronization based on double buffer areas Download PDFInfo
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- CN106444352A CN106444352A CN201610981281.2A CN201610981281A CN106444352A CN 106444352 A CN106444352 A CN 106444352A CN 201610981281 A CN201610981281 A CN 201610981281A CN 106444352 A CN106444352 A CN 106444352A
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- G—PHYSICS
- G04—HOROLOGY
- G04R—RADIO-CONTROLLED TIME-PIECES
- G04R20/00—Setting the time according to the time information carried or implied by the radio signal
- G04R20/02—Setting the time according to the time information carried or implied by the radio signal the radio signal being sent by a satellite, e.g. GPS
- G04R20/04—Tuning or receiving; Circuits therefor
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
- G05B19/0425—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2604—Test of external equipment
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- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
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- Automation & Control Theory (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention provides a method and a system for measuring clock synchronization based on double buffer areas. The system comprises a DSP (digital signal processor) and an FPGA (field programmable gate array), wherein the DSP and the FPGA are arranged in a measuring device; the DSP comprises a data receiving unit, a data calculating unit, a first buffer area and a second buffer area; the data receiving unit is used for receiving sampling data from the FPGA in the measuring device; one of the first buffer area and the second buffer area is used for storing the current sampling data at any time; when the sampling data received by the DSP is the last packet in an absolute time tag TPa, the currently received sampling data is switched to be stored into the other buffer area; when the data length in the other buffer area reaches the measuring and calculating data length TPm, the data calculating unit starts to read the data in the buffer area and calculate parameters, and the original buffer area continues to store the sampling data and calculate the parameters, until the length of the stored sampling data reaches TPm; the original buffer area does not work, and the buffer areas are switched to work, so as to realize the synchronization measuring and calculation.
Description
Technical field
The present invention relates to measuring instrument simultaneous techniquess field, particularly to a kind of clock synchro measure based on double buffering
Method and system.
Background technology
Power analyzer, power quality analyzer, electric power online monitoring device etc. possess the instrument instrument of electric measurement function
Table, in order to ensure to produce identical result when two apparatus measures same signal, or the difference in same measuring system
It is necessary to possess the function of clock synchro measure when position is measured using multiple stage instrument.
Accurate clock synchro measure function is to measuring instrument in synchronized sampling, electric energy event detection, power fault analysis
Etc. aspect there is material impact.Current method for synchronously measuring adopts the larger intervalometer timing of error mostly；Some GPS timings
Method for synchronously measuring does not then account for the sampling gap problem between synchronizing cycle, or using mechanism when frequent pair, reduces
The precision of measurement and efficiency.These method for synchronously measuring all can not meet clock synchro measure will to certainty of measurement and efficiency
Ask.
Content of the invention
It is an object of the invention to provide a kind of clock method for synchronously measuring based on double buffering and system, existing to solve
Technical problem during inadequate, frequent pair of some measurement apparatus certainty of measurement when entering row clock synchro measure, under efficiency.
For achieving the above object, the invention provides a kind of clock method for synchronously measuring based on double buffering, including with
Lower step：
S1：DSP creates first buffering area and second buffering area；
S2：In any one time receiving the enabling signal starting clock synchro measure, start DSP reception and be derived from
The sampled data of FPGA；
S3：Currently received sampled data is preserved to first buffering area, when the data length in first buffering area reaches
After survey calculation data length TPm, the data that DSP reads in first buffering area is entered line parameter and is calculated, and now second buffering area is not
Work；
S4：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampling
Data preserves to second buffering area, and after the data length in second buffering area reaches survey calculation data length TPm, DSP reads
Take the data in second buffering area to enter line parameter to calculate, now first buffering area continues to preserve sampled data and enters line parameter meter
Calculate, until after the sampled data length preserving reaches TPm, first buffering area does not work；
S5：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampling
Data preserves to first buffering area, and after the data length in first buffering area reaches survey calculation data length TPm, DSP reads
Take the data in first buffering area to enter line parameter to calculate, now second buffering area continues to preserve sampled data and enters line parameter meter
Calculate, until after the sampled data length preserving reaches TPm, second buffering area does not work；
S6：Repeated execution of steps S4 to S6, until FPGA stops data sampling.
It is preferred that when described first buffering area or second buffering area start to preserve sampled data every time, it starts storage
First data point is the integral point data of absolute time tag TPa.
It is preferred that the sampled data length that described DSP reads every time is TPs.
It is preferred that described survey calculation data length TPm is set to TPm=n*T, wherein, T is the cycle of measurement signal, n
For positive integer.
It is preferred that in described step S4 and S5, it is last in absolute time tag TPa for judging that DSP receives sampled data
One bag condition be：
Whether the absolute time tag TPa of first data point of the packet belonging to present sample data reaches the next one
In the range of TPa, meanwhile, whether the absolute time tag TPa of last data point of the packet belonging to present sample data
Exceed or reached in the range of next TPa.
Present invention also offers a kind of clock synchronized measurement system based on double buffering, including dsp system and FPGA system
System, described dsp system includes the DSP that several are arranged in different measurement apparatus, and described DSP includes：Data receipt unit,
Data Computation Unit, first buffering area and second buffering area；
Described FPGA system includes the FPGA that several are arranged in different measurement apparatus, and described FPGA is used for into line number
Obtain sampled data according to sampling；
Described data receipt unit is used for receiving the sampled data of the FPGA in same measurement apparatus；
Described first buffering area and second buffering area are used for preserving described sampled data；Wherein, first described in any time
Relief area and second buffering area one of both preserve current sampled data, are absolute time mark whenever DSP receives sampled data
When signing last bag in TPa, the switching of currently received sampled data is preserved to another relief area, and whenever another relief area
After interior data length reaches survey calculation data length TPm, the data that Data Computation Unit starts to read in this relief area is entered
Line parameter calculates, and now former relief area continues to preserve sampled data and enter line parameter to calculate, until the sampled data length preserving
After reaching TPm, former relief area does not work, and switching successively is carried out.
It is preferred that described DSP is connected with RTC clock, described RTC clock is used for providing reference to clock synchronized measurement system
Clock signal.
It is preferred that the data communication mode between described DSP and FPGA is upp, and DSP is connected with host computer by network.
It is preferred that described FPGA is provided with satellite signal reception module, for receiving satellite time transfer signal with according to described
Satellite time transfer signal carries out the synchronization of the FPGA between different measuring device.
It is preferred that the sampled data of FPGA includes voltage and current, the parameter that the Data Computation Unit of DSP calculates includes work(
Rate parameter, power quality parameter.
Due to employing technique scheme, the invention has the beneficial effects as follows：
1) calculating cycle of Data Computation Unit is continuous, does not have any gap and omission；
2) the synchronous RTC clock by measuring instrument of clock controls, it is to avoid frequently enter the synchronous operation of row clock, and raising sets
Received shipment line efficiency；
3) adopt the mechanism of double buffering, improve clock synchronous efficiency and easily perform；
4) realize the clock to the measuring instrument such as any power parameter, the quality of power supply, electric power monitoring field synchronous, to event
Detection, fault location have very great help；
5) clock method for synchronously measuring is applied to the configuration of any calculating cycle, synchronizing cycle；
6) adopt the data communication mode of upp between DSP and FPGA, data transfer is quickly stablized；
7) provide a kind of synchronized measurement system, realize the synchro measure to diverse location multiple stage instrument；
8) achieve two kinds of different instruments and draw identical measurement result, accurate detection when measuring same signal
To power events.
Brief description
Fig. 1 is the clock synchronized measurement system composition schematic diagram based on double buffering of preferred embodiment；
Fig. 2 is the DSP composition schematic diagram of preferred embodiment；
Fig. 3 is the clock synchro measure sequence chart of preferred embodiment；
Fig. 4 is the DSP double buffering working machine drawing of preferred embodiment.
Specific embodiment
For the present invention is better described, hereby with a preferred embodiment, and coordinate accompanying drawing that the present invention is elaborated, specifically
As follows：
As shown in figure 1, present embodiments providing a kind of clock synchronized measurement system based on double buffering, including DSP system
System and FPGA system, FPGA system includes the FPGA that several are arranged in different measurement apparatus, and dsp system includes several
It is arranged at the DSP in different measurement apparatus.Wherein, FPGA is used for carrying out data sampling obtaining sampled data；DSP is used for receiving
From the sampled data of FPGA and carry out data calculating.
As shown in Fig. 2 each DSP in the present embodiment includes：Data receipt unit 201, Data Computation Unit 202,
One relief area 203 and second buffering area 204.
Data receipt unit 201 is used for receiving the sampled data of the FPGA in same measurement apparatus；
First buffering area 203 and second buffering area 204 are used for preserving sampled data；Wherein, any time first buffering area
And second buffering area one of both preserves current sampled data, and reach survey calculation data length in the data length preserving
After TPm, the data that Data Computation Unit 202 starts to read in this relief area is entered line parameter and is calculated.Whenever DSP receives sampled data
When wrapping for last in absolute time tag TPa, the switching of currently received sampled data is preserved to another relief area, and often
After the data length in another relief area reaches survey calculation data length TPm, Data Computation Unit 202 starts to read this and delays
Rush the data in area and enter line parameter calculating, now former relief area continues to preserve sampled data and enter line parameter to calculate, until preservation
Sampled data length reach TPm after, former relief area does not work, successively switching carry out.
DSP in the present embodiment is connected with RTC clock, and this RTC clock is used for providing reference to clock synchronized measurement system
Clock signal.
For data transfer between DSP and FPGA in same measurement apparatus by the way of dual port RAM, and DSP and FPGA
Between data communication mode be DSP in upp, and each measurement apparatus all pass through network (in the present embodiment for Ethernet) with upper
Position machine is connected, and host computer can obtain sampled data and the calculating parameter of each measurement apparatus by ethernet communication mode.
FPGA in each measurement apparatus is provided with GPS receiver module, for receiving the GPS time service letter from gps satellite
Number to carry out the synchronization of the FPGA between different measuring device according to GPS time signal.
Wherein, the FPGA sampled data in the present embodiment includes but is not limited to voltage and current, and the parameter that DSP calculates includes
It is not limited to power parameter, power quality parameter.
Shown in Figure 3, a kind of clock method for synchronously measuring based on double buffering that the present embodiment provides, including following
Step：
S1：DSP creates first buffering area and second buffering area；
S2：In any one time receiving the enabling signal starting clock synchro measure, start DSP reception and be derived from
The sampled data of FPGA；
S3：Currently received sampled data is preserved to first buffering area, when the data length in first buffering area reaches
After survey calculation data length TPm, the data that DSP reads in first buffering area is entered line parameter and is calculated, and now second buffering area is not
Work；
S4：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampling
Data preserves to second buffering area, and after the data length in second buffering area reaches survey calculation data length TPm, DSP reads
Take the data in second buffering area to enter line parameter to calculate, now first buffering area continues to preserve sampled data and enters line parameter meter
Calculate, until after the sampled data length preserving reaches TPm, first buffering area does not work；
S5：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampling
Data preserves to first buffering area, and after the data length in first buffering area reaches survey calculation data length TPm, DSP reads
Take the data in first buffering area to enter line parameter to calculate, now second buffering area continues to preserve sampled data and enters line parameter meter
Calculate, until after the sampled data length preserving reaches TPm, second buffering area does not work；
S6：Repeated execution of steps S4 to S6, until FPGA stops data sampling.
Wherein, when described first buffering area or second buffering area start to preserve sampled data every time, its start to store the
One data point is the integral point data of absolute time tag TPa.
The sampled data length that in the present embodiment, DSP reads every time is TPs=20ms；When DSP measures calculating every time
Data length TPm be set to TPm=n*T, wherein, T be measurement signal cycle, n be positive integer, n value in the present embodiment
For 10；The absolute time tag TPa=10min (such as 01 that dsp system synchronizes every time:10,01:20), that is, each is absolute
The 10min moment restarts synchronous calculating.Here TPs, TPm and TPa is before the formal data of execution preserves and pre-sets
Complete, execution control to subsequent processes of different sizes according to this three parameters pre-setting.
In step S4 and S5, judge that DSP receives the condition for last bag in absolute time tag TPa for the sampled data
For：
Whether the absolute time tag TPa of first data point of the packet belonging to present sample data reaches the next one
In the range of TPa, meanwhile, whether the absolute time tag TPa of last data point of the packet belonging to present sample data
Exceed or reached in the range of next TPa.
Shown in Figure 3, this clock synchro measure sequence chart is specific as follows：
Step 1：Dsp system creates two an equal amount of sync buffering area BufA and BufB.Sync buffering area receives
The sampled data of FPGA, and carry out based on electric parameter by dsp system computing unit when data storage length reaches TPm
Calculate
Step 2：Dsp system random time is started working, and BufA is normal operating conditions, and BufB is holding state, now
Sampled data is saved in BufA, and when BufA data length is TPm, dsp system computing unit reading BufA data carries out all kinds of electricity
The computing of gas parameter；BufB does not preserve data and is not used for calculating yet
Step 3：Step 2 be continued until data that dsp system receives for absolute time tag is 10min last
Bag；
Now BufB jumps to normal operating conditions from holding state, and that is, BufB starts to preserve sampled data, and it starts to deposit
First data point of storage is 10min integral point data, and BufB dsp system computing unit when data length reaches TPm is read
BufB data is taken to carry out the computing of all kinds of electric parameters；
Now BufA keeps working condition.
Step 4：BufA continues sampling in the moment of step 3, until the sampled data length of BufA storage is TPm, and
After the completion of dsp system carries out the calculating of all kinds of electric parameters to this TPm length samples data, BufA jumps to from working condition and treats
Machine state；I.e. BufA stops preserving sampled data and being used for calculating.
Now BufB keeps normal operating conditions.
Step 5：Step 4 be continued until data that dsp system receives for absolute time tag is 10min last
Bag；
Now BufA jumps to normal operating conditions from holding state, and that is, BufA starts to preserve sampled data, and it starts to deposit
First data point of storage is 10min integral point data, and BufA dsp system computing unit when data length reaches TPm is read
BufB data is taken to carry out the computing of all kinds of electric parameters；
Now BufB keeps working condition.
Step 6：BufB continues sampling in the moment of step 5, until the sampled data length of BufB storage is TPm, and
After the completion of dsp system carries out the calculating of all kinds of electric parameters to this TPm length samples data, BufB jumps to from working condition and treats
Machine state；I.e. BufB stops preserving sampled data and being used for calculating.
Now BufA keeps normal operating conditions.
Step 7：Repeat step 2～step 5, until FPGA system stops data sampling.
Specifically, shown in Figure 4, it is named as BufA in the first buffering area the present embodiment in double buffering, second delays
Rush area and be named as BufB, each relief area can store the data of n data calculating cycle length.When step S4, S5 executes,
When carrying out the switching between double buffering BufA and double buffering BufB, there is a lap in the data that both preserve, this is heavy
The folded part i.e. time point with absolute time tag TPa as 10min is judged, when reaching this time point, that is, starts another
Relief area carries out data preservation, simultaneously as in the relief area of former work packet resolve not yet complete, need to continue executing with to work as
The front preservation of data of data calculating cycle length (TPm) and the calculating of measurement parameter, to ensure the complete of data.And
The data that another relief area of switching preserves at it reaches TPm and proceeds by parameter calculating.This mode ensure that two bufferings
Integrity and the synchronicity of parameter calculating that interval censored data preserves.
Below in conjunction with the accompanying drawings with one practical application example is described in further detail to the present invention program
In this example, whether calibrating is clock synchro measure state, and verification step is as follows taking quality of power supply instrument as a example：
1st, power quality analyzer is in clock synchronous working state；
2nd, the voltage dip event of a setting persistent period is exported to electric energy by a synchronous signal generator
Mass-synchrometer, the time started of this rapid drawdown event is T1；
3rd, check that power quality analyzer detects this rapid drawdown event, and record initial time rapid drawdown event is detected
Tm1；
4th, compare Tm and T1, | Tm T1 |<1 cycle (signal period detecting)；
5th, close the synchronous time adjustment function of power quality analyzer, work at least 48 hours；
6 and then exported the voltage dip of a given persistent period by synchronous signal generator, the opening of this rapid drawdown event
Time beginning is T2；
7th, check that power quality analyzer detects this rapid drawdown event, and record initial time rapid drawdown event is detected
Tm2；
8th, carry out following checking：
|T2–Tm2|<|T2–T1|/(3600*24).
Can be illustrated by above-mentioned steps：
1st, step 4 illustrates that, when instrument opens synchronous, signal time difference is less than a signal period；
2nd, the checking explanation of step 8, after instrument cuts out synchronization, after 48 hours, not synchronous lower signal time difference is less than
1S.
A kind of this clock method for synchronously measuring based on double buffering that can prove the present invention and system have following
Feature：
1st, accurate clock synchro measure mechanism；
2nd, convenient and simple, can continue automatically to keep synchro measure function.
The above, the only specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, and any
Those skilled in the art the invention discloses technical scope in, the deformation that the present invention is done or replacement, all should cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by described scope of the claims.
Claims (10)
1. a kind of clock method for synchronously measuring based on double buffering is it is characterised in that comprise the following steps：
S1：DSP creates first buffering area and second buffering area；
S2：In any one time receiving the enabling signal starting clock synchro measure, start DSP and receive from FPGA's
Sampled data；
S3：Currently received sampled data is preserved to first buffering area, when the data length in first buffering area reaches measurement
After calculating data length TPm, the data that DSP reads in first buffering area is entered line parameter and is calculated, and now second buffering area does not work；
S4：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampled data
Preserve to second buffering area, after the data length in second buffering area reaches survey calculation data length TPm, DSP reads the
Data in two relief areas is entered line parameter and is calculated, and now first buffering area continues to preserve sampled data and enter line parameter to calculate, directly
After reaching TPm to the sampled data length preserving, first buffering area does not work；
S5：When DSP receives last bag that sampled data is in absolute time tag TPa, by currently received sampled data
Preserve to first buffering area, after the data length in first buffering area reaches survey calculation data length TPm, DSP reads the
Data in one relief area is entered line parameter and is calculated, and now second buffering area continues to preserve sampled data and enter line parameter to calculate, directly
After reaching TPm to the sampled data length preserving, second buffering area does not work；
S6：Repeated execution of steps S4 to S6, until FPGA stops data sampling.
2. the clock method for synchronously measuring based on double buffering according to claim 1 is it is characterised in that every time described
When one relief area or second buffering area start to preserve sampled data, first data point that it starts to store is absolute time tag
The integral point data of TPa.
3. the clock method for synchronously measuring based on double buffering according to claim 1 is it is characterised in that described DSP is every
The sampled data length of secondary reading is TPs.
4. the clock method for synchronously measuring based on double buffering according to claim 1 is it is characterised in that described meter
Calculate data length TPm and be set to TPm=n*T, wherein, T is the cycle of measurement signal, and n is positive integer.
5. the clock method for synchronously measuring based on double buffering according to claim 1 is it is characterised in that described step S4
And in S5, judge that DSP receives sampled data and for the condition of last bag in absolute time tag TPa is：
Whether the absolute time tag TPa of first data point of the packet belonging to present sample data reaches next TPa
In the range of, meanwhile, whether the absolute time tag TPa of last data point of the packet belonging to present sample data is super
Cross or reach in the range of next TPa.
6. a kind of clock synchronized measurement system based on double buffering is it is characterised in that include dsp system and FPGA system, institute
State the DSP that dsp system includes several and is arranged in different measurement apparatus, described DSP includes：Data receipt unit, data
Computing unit, first buffering area and second buffering area；
Described FPGA system includes the FPGA that several are arranged in different measurement apparatus, and described FPGA is used for carrying out data adopting
Sample obtains sampled data；
Described data receipt unit is used for receiving the sampled data of the FPGA in same measurement apparatus；
Described first buffering area and second buffering area are used for preserving described sampled data；Wherein, the first buffering described in any time
Area and second buffering area one of both preserve current sampled data, are absolute time tag TPa whenever DSP receives sampled data
During last bag interior, the switching of currently received sampled data is preserved to another relief area, and in another relief area
After data length reaches survey calculation data length TPm, the data that Data Computation Unit starts to read in this relief area is joined
Number calculates, and now former relief area continues to preserve sampled data and enter line parameter to calculate, until the sampled data length preserving reaches
After TPm, former relief area does not work, and switching successively is carried out.
7. the clock synchronized measurement system based on double buffering according to claim 6 it is characterised in that described DSP with
RTC clock is connected, and described RTC clock is used for providing reference clock signal to clock synchronized measurement system.
8. the clock synchronized measurement system based on double buffering according to claim 6 it is characterised in that described DSP and
Data communication mode between FPGA is upp, and DSP is connected with host computer by network.
9. the clock synchronized measurement system based on double buffering according to claim 6 is it is characterised in that described FPGA sets
It is equipped with satellite signal reception module, for receiving satellite time transfer signal so that different measuring dress is carried out according to described satellite time transfer signal
The synchronization of the FPGA between putting.
10. the clock synchronized measurement system based on double buffering according to claim 6 is it is characterised in that FPGA's adopts
Sample data includes voltage and current, and the parameter that the Data Computation Unit of DSP calculates includes power parameter, power quality parameter.
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