CN202617149U

CN202617149U - High-precision IP (Internet Protocol) network one-way time delay measuring device

Info

Publication number: CN202617149U
Application number: CN 201220279919
Authority: CN
Inventors: 唐旭; 王飞; 丛自龙; 孙宇; 孙滨; 张鹏; 章敬崇; 辜博雅; 贾静文
Original assignee: 63655 TROOPS OF PEOPLE'S LIBERATION ARMY
Current assignee: 63655 TROOPS OF PEOPLE'S LIBERATION ARMY
Priority date: 2012-06-14
Filing date: 2012-06-14
Publication date: 2012-12-19
Anticipated expiration: 2022-06-14

Abstract

The utility model relates to a high-precision IP (Internet Protocol) network one-way time delay measuring device, which belongs to the field of network communication and consists of measuring equipment and a network to be measured, wherein the measuring equipment consists of a set of sending equipment and a set of receiving equipment, each set of equipment respectively consists of a field-programmable gate array chip, a digital signal processor, an Ethernet controller, a memory, a constant-temperature oscillator and a counter, the field-programmable gate array chip is respectively and electrically connected with the digital signal processor, the Ethernet controller and the counter, the constant-temperature oscillator is electrically connected with the counter, and the memory is electrically connected with the digital signal processor. The high-precision IP network one-way time delay measuring device has the advantages that the technical problems of clock precision and clock synchronization during time delay measurement are solved, the time delay measurement precision can reach the 10ns level, the measuring results are reliable, the cost is greatly reduced, and the network one-way time delay and the network service quality can be accurately reflected.

Description

High accuracy IP network one-way delay measurement device

Technical field

The high accuracy IP network one-way delay measurement device of the utility model belongs to network communication field.

Background technology

Time delay is one of build-in attribute of network, also is the basic index of evaluating network performance.Time delay refers to a packet and sends to the required time of another main frame from a main frame.At present; The methods such as latency measurement that both at home and abroad mainly adopt GPS to carry out latency measurement end to end, order realizes based on Ping latency measurement, realize based on software about the measurement of time delay; There is following defective in it: 1, use GPS to carry out latency measurement, acquisition expenses height and use cost are big; 2, under the asymmetrical paths situation, the source end maybe be different to the path of source end with destination to the path of destination, causes measurement result unreliable; 3, certainty of measurement is not high, is Millisecond; 4, Measurement Resolution is relatively poor, is 10 Milliseconds.

Summary of the invention

The purpose of the utility model is to provide a kind of high accuracy IP network one-way delay measurement device.

The purpose of the utility model is achieved in that high accuracy IP network one-way delay measurement device is made up of measuring equipment MD (Measurement Device) and tested network; Measuring equipment is made up of a cover transmitting apparatus and a cover receiving equipment, and every complete equipment is formed by field programmable gate array chip, digital signal processor, ethernet controller, memory, constant temperature oscillator, counter.Field programmable gate array chip is electrically connected with above-mentioned digital signal processor, ethernet controller, counter respectively, and constant temperature oscillator is electrically connected with counter, and memory is electrically connected with digital signal processor.

Owing to carry out technique scheme; This device solves clock accuracy and the technical problem of clock synchronization of latency measurement, its time delay certainty of measurement can reach the 10ns level, measurement result is reliable; Cost reduces greatly, can reflect the One Way Delay and reflection network service quality of network more exactly.

Description of drawings: the technical scheme of the utility model is provided by following accompanying drawing and embodiment:

Fig. 1 is the system module composition diagram of high accuracy IP network one-way delay measurement device;

Fig. 2 is the measuring equipment structural representation;

Fig. 3 is that the measuring equipment clock synchronization realizes design drawing;

Fig. 4 is field programmable gate array chip and ethernet controller interface sketch map.

Embodiment:

Legend: 1, field programmable gate array chip, 2, counter, 3, constant temperature oscillator, 4, digital signal processor, 5, memory, 6, ethernet controller, 7, synchronous port.

Embodiment: shown in Fig. 1～3.The high accuracy IP network one-way delay measurement device of the utility model is made up of measuring equipment MD (Measurement Device) and tested network; Measuring equipment is made up of a cover transmitting apparatus (MD-S) and a cover receiving equipment (MD-R), measures operation and accomplishes through two device cooperations.Every complete equipment is that the make the science and technology prosperous JFVNY OC14 40MHz constant temperature oscillator 3 of Co., Ltd, the EPM7128STC counter 2 of U.S. ALTERA company of the brilliant space in SD card, Beijing formed by the DM9000 ethernet controller 6 of the TMS320VC5509A digital signal processor DSP 4 (Digital Signal Processor) of the EP1C12Q240C8 field programmable gate array chip FPGA (Field-Programmable Gate Array) 1 of U.S. ALTERA company, American TI Company, Taiwan Lian Jie international corporation, capacity less than the memory 5 of 4G; Wherein constant temperature oscillator 3 provides the counting operating frequency for counter 2; The counter 2 main clock synchronizations of accomplishing between transmitting apparatus and the receiving equipment are for field programmable gate array chip 1 provides relative time.Field programmable gate array chip 1 is responsible for the control chip of Ethernet is carried out initialization in the transmitting apparatus, stamps markers to detection packet, is packaged into the IP packet, sends to ethernet controller 6 by digital signal processor 4 control field programmable gate array chips 1; Field programmable gate array chip 1 is responsible for analyzing the IP packet that ethernet controller 6 transmits in the receiving equipment, and relatively frame head judges whether to be detection packet, gives digital signal processor 4 if detection packet is then stamped markers for detection packet after unpacking.The transmission of digital signal processor 4 main responsible control detection packet, reception, extraction One Way Delay parameter, temporal information etc. are stored in measurement result in the memory 5 at last.

A, clock synchronization: owing to dispose and the restriction that realizes, current performance measurement mainly is the edge that each measurement point is distributed in tested network, carries out performance measurement end to end, so clock synchronization is mainly realizing between the measurement point end to end.

As shown in Figure 3; Give the power supply of transmitting apparatus and receiving equipment respectively with battery; (SYNC (Synchronous interface) links to each other, and with synchronous triggering counter 2, resets when realizing it, counts synchronously with the synchronous port 7 on this two unit counts device to use a holding wire then.Pin one is a synchronous port 7 among the figure, is the button that two equipment are realized synchronous triggering, and when button when 1～7 and 8 pin short circuits, corresponding generation low level produces and interrupts, thereby in synchronous port 7 output synchronizing signals, two equipment is moved on same clock basis.Two equipment are record Counter Value separately in transmission, acceptance test bag, just can obtain time delay through calculating.Because of the crystal oscillator frequency precision of constant temperature oscillator 3 is ± 0.5PPM that the clock cycle is 20ns, thereby the time precision of one-way delay measurement system is the 10ns level.The time that obtains by this method is relative time, realizes that cost is very little.

B, detection packet transmission control:

This device adopts field programmable gate array chip 1; All adopt VHSIC hardware description language VHDL (Very-High-Speed Integrated Circuit Hardware Description Language), and on the design platform of Quatus7.2, accomplish whole Module Design, comprehensive, emulation, mapping and placement-and-routing.

As shown in Figure 4, use field programmable gate array chip 1 control ethernet controller 6, realize the transmission of IP packet, field programmable gate array chip 1 directly is connected with the external bus of ethernet controller 6.

Digital signal processor 4 writes the transmission detection packet through field programmable gate array chip 1 in the transmission buffer area of ethernet controller 6, and sends the transmission data command to ethernet controller 6.After digital signal processor 4 was handled detection packet and finished, ethernet controller 6 began to send a Frame.When sending these frame data, the data of second frame write the transmission buffer area.

After ethernet controller 6 sent and finishes, it will produce an indication and send the interrupt signal of accomplishing.In process of transmitting, digital signal processor 4 can be inquired about register flag bit through field programmable gate array chip 1, obtains the transmit status of detection packet.

Digital signal processor 4 is checked accepting state through field programmable gate array chip 1; If receive new data; Digital signal processor 4 begins to read reception buffer area data through field programmable gate array chip 1, when reading, adds the temporal information that receives data.

According to the length information that obtains, judge whether to run through a frame.If run through, then read next frame, read up to data and finish.

Claims

1. high accuracy IP network one-way delay measurement device; Constitute by measuring equipment MD (Measurement Device) and tested network; Measuring equipment is made up of a cover transmitting apparatus and a cover receiving equipment; It is characterized in that: every complete equipment is formed by field programmable gate array chip, digital signal processor, ethernet controller, memory, constant temperature oscillator, counter; Field programmable gate array chip is electrically connected with above-mentioned digital signal processor, ethernet controller, counter respectively, and constant temperature oscillator is electrically connected with counter, and memory is electrically connected with digital signal processor.

2. high accuracy IP network one-way delay measurement device as claimed in claim 1 is characterized in that: be connected with holding wire between the synchronous port on transmitting apparatus and the receiving equipment counter.

3. high accuracy IP network one-way delay measurement device as claimed in claim 1 is characterized in that: field programmable gate array chip directly is electrically connected with the external bus of ethernet controller.