CN109542040B - IO signal processing method and programmable logic controller - Google Patents
IO signal processing method and programmable logic controller Download PDFInfo
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Abstract
The IO signal processing method is applied to a programmable logic controller under an industrial environment, the number of I/O points of the programmable logic controller is less than 256, and the programmable logic controller is connected with a field programmable gate array for signal acquisition.
Description
Technical Field
The application relates to the technical field of P L C, in particular to an IO signal processing method and a programmable logic controller.
Background
A Programmable logic Controller (P L C, Programmable L g-C Controller) is widely used by virtue of Programmable flexibility, wherein, a small P L C is an electronic device operated by digital operation, the I/O point number of the electronic device is below 256, and the electronic device is specially designed for application in industrial environment, a small P L C uses a programming memory, stores the electronic device in the programming memory and performs operations such as logic operation, sequence operation, timing counting and the like, and can operate various machines or production processes through data input and output, and the small P L C has the advantages of small volume and compact structure.
However, the small P L C having only a single CPU cannot meet the needs of the industrial control site in some cases because of limited IO resources included in the CPU of the small P L C and the limitation of the operation speed of the CPU.
Therefore, it is a technical solution to solve the problems of insufficient IO resources and low operating efficiency while providing a programmable logic controller with the advantages of small size and compact structure.
Disclosure of Invention
In view of this, an object of the present invention is to provide an IO signal processing method and a programmable logic controller, so that the programmable logic controller can solve the problems of insufficient IO resources and low operation efficiency on the basis of having the advantages of small size and compact structure.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
an IO signal processing method is applied to a programmable logic controller under an industrial environment, the number of I/O points of the programmable logic controller is less than 256, and a field programmable gate array for collecting signals is connected with the programmable logic controller, and the method comprises the following steps:
judging whether a digital signal and/or a high-speed pulse signal acquired by the field programmable gate array need to be acquired or not;
and if the digital signal and/or the high-speed pulse signal are required to be acquired, reading the register of the field programmable gate array to acquire the digital signal and/or the high-speed pulse signal.
In a preferred option of the embodiment of the present application, in the IO signal processing method, the method further includes:
judging whether a digital signal and/or a PWM signal needs to be output or not;
and if the digital signal and/or the PWM signal needs to be output, generating a corresponding output instruction, and sending the output instruction to a register of the field programmable gate array so that the field programmable gate array outputs the digital signal and/or the PWM signal.
In a preferred option of the embodiment of the present application, in the IO signal processing method, the step of generating a corresponding output instruction and sending the output instruction to the register of the field programmable gate array includes:
if the signal needing to be output is a PWM signal, calculating according to the frequency value and the duty ratio of the PWM signal and a preset formula to obtain a high level count value and a low level count value of the PWM signal;
and sending the high-level counting value and the low-level counting value to a register of the field programmable gate array.
In a preferred option of the embodiment of the present application, in the IO signal processing method, the preset formula includes:
cnth＝109*(Dc/104)/Freq/Ts；
cntl＝109*(1-Dc/104)/Freq/Ts；
wherein, cnthIs a high level count value, cntlThe low level count value, Dc the duty cycle, Freq the frequency value, Ts the clock period of the FPGA.
In a preferred option of an embodiment of the present application, in the IO signal processing method, the programmable logic controller is further connected to an ADC chip for acquiring an analog signal through an SPI interface, and the method further includes:
judging whether analog signals acquired by the ADC chip need to be acquired or not;
if the analog signal needs to be acquired, acquiring an original code value corresponding to the analog signal from a register of the ADC chip, and converting the original code value into a mapping code value which can be identified by an upper computer connected with the programmable logic controller according to a first preset relation.
In a preferable selection of the embodiment of the application, in the IO signal processing method, the first preset relationship includes:
MAPCODE＝(a1*CODE+b1)*103/1.221；
wherein MAPCODE is a mapping CODE value, CODE is an original CODE value, a1And b1The parameters are calibrated for a predetermined acquisition.
In a preferred option of an embodiment of the present application, in the IO signal processing method, the programmable logic controller is further connected to a DAC chip for outputting an analog signal through an SPI interface, and the method further includes:
judging whether an analog signal needs to be output through the DAC chip or not;
if the analog signal needs to be output, converting a mapping code value sent by an upper computer connected with the programmable logic controller into an original code value which can be identified by the DAC chip according to a second preset relation, and sending the original code value to the DAC chip so as to control the DAC chip to output the analog signal.
In a preferable selection of the embodiment of the application, in the IO signal processing method, the second preset relationship includes:
wherein CODE is the original CODE value, MAPCODE is the mapping CODE value, a2And b2The parameters are calibrated for a predetermined output.
On the basis, an embodiment of the present application further provides a programmable logic controller, including:
a storage unit;
a processing unit;
a computer program stored in the storage unit and capable of running on the processing unit, wherein the computer program realizes the IO signal processing method when running;
the I/O point number of the programmable logic controller is less than 256, and the programmable logic controller is connected with a field programmable gate array for collecting signals.
In a preferred option of the embodiment of the present application, in the above programmable logic controller, the programmable logic controller has 24 digital signal acquisition channels, 45 digital signal output channels, 14 analog signal acquisition channels, 2 analog signal output channels, 8 high-speed pulse signal acquisition channels, and 24 PWM signal output channels.
According to the IO signal processing method and the programmable logic controller, the programmable logic controller is connected with the field programmable gate array to acquire and acquire data based on the field programmable gate array, so that the problems of insufficient IO resources and low operation efficiency of the programmable logic controller can be solved on the basis of the advantages of small size and compact structure, and the method and the programmable logic controller have high practical value.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is an application block diagram of a programmable logic controller according to an embodiment of the present application.
Fig. 2 is a schematic flowchart of an IO signal processing method according to an embodiment of the present application.
Fig. 3 is a schematic flowchart of other steps included in an IO signal processing method according to an embodiment of the present application.
Fig. 4 is a schematic flowchart of step S140 in fig. 3.
Fig. 5 is a schematic flowchart of other steps included in an IO signal processing method according to an embodiment of the present application.
Fig. 6 is a schematic flowchart of other steps included in an IO signal processing method according to an embodiment of the present application.
Icon: 100-a programmable logic controller; 120-a storage unit; 140-a processing unit; 200-field programmable gate array.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. In the description of the present application, the terms "first," "second," "third," "fourth," and the like are used merely to distinguish one description from another, and are not to be construed as merely or implying relative importance.
As shown in fig. 1, the embodiment of the present application provides a programmable logic controller 100 that can be applied in an industrial environment. The number of I/O points of the Programmable logic controller 100 is less than 256, and a Field-Programmable Gate Array (FPGA) 200 for acquiring signals is connected thereto.
In detail, the programmable logic controller 100 may include a storage unit 120 and a processing unit 140. The storage unit 120 and the processing unit 140 are electrically connected directly or indirectly to realize data transmission or interaction. For example, they may be electrically connected to each other via one or more communication buses or signal lines. The processing unit 140 is configured to execute the executable computer program stored in the storage unit 120 to implement the IO signal processing method.
The Memory unit 120 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The storage unit 120 is configured to store a program, and the processing unit 140 executes the program after receiving the execution instruction.
It will be appreciated that the configuration shown in fig. 1 is merely illustrative and that the programmable logic controller 100 may include more or fewer components than shown in fig. 1 or may have a different configuration than shown in fig. 1.
For example, in an alternative example, the programmable logic controller 100 may have 24 digital signal acquisition channels, 45 digital signal output channels, 14 analog signal acquisition channels, 2 analog signal output channels, 8 high-speed pulse signal acquisition channels, and 24 PWM signal output channels.
That is to say, in order to collect and output an analog signal, in this embodiment, the programmable logic controller 100 may further be connected with an ADC chip and a DAC chip through the SPI interface, so as to collect and output an analog signal based on the ADC chip and the DAC chip.
With reference to fig. 2, an embodiment of the present application further provides an IO signal processing method applicable to the above programmable logic controller 100. The method steps defined by the flow related to the IO signal processing method may be implemented by the programmable logic controller 100. The specific process shown in fig. 2 will be described in detail below.
Step S110, determining whether the digital signal and/or the high-speed pulse signal acquired by the field programmable gate array 200 needs to be acquired.
Step S120, reading the register of the field programmable gate array 200 to obtain the digital signal and/or the high-speed pulse signal.
In this embodiment, the programmable logic controller 100 is connected to a field programmable gate array 200, and the field programmable gate array 200 may be configured to collect a digital signal and a high-speed pulse signal and store the digital signal and the high-speed pulse signal in a corresponding register.
Therefore, when the step S110 is executed to determine that the digital signal and/or the high-speed pulse signal collected by the field programmable gate array 200 needs to be acquired, the step S120 may be executed. That is, the digital signal or the high-speed pulse signal stored in the register of the field programmable gate array 200 can be obtained by performing a read operation on the register.
It should be noted that, when the field programmable gate array 200 performs high-speed pulse signal acquisition, double-edge detection may be performed on an input pulse. The specific detection method is that the input pulse is delayed by one clock, and the phase-reversal result of the input pulse and the delayed pulse is 1 after the phase-reversal result, which is expressed as a rising edge; the phase of the inverted result of the input pulse and the delayed pulse is summed to be 1, and the result is represented as a falling edge.
When the high-speed pulse signal is acquired, a count value or a frequency measurement value of the high-speed pulse signal is acquired. For example, after detecting a rising edge and a falling edge, the count register may be incremented by 1 to form the count value, respectively. Wherein, the frequency measurement value is to count by taking 1s as a time window. Specifically, a 1s counter may be provided in the field programmable gate array 200, and when the counter counts to 1s, the pulse count value of the pulse count value register is stored in the frequency measurement value register, and the pulse count value register is cleared.
With reference to fig. 3, in order to further expand the IO resources of the programmable logic controller 100, in this embodiment, the IO signal processing method may further include step S130 and step S140, which is described in detail below.
Step S130, determining whether the digital signal and/or the PWM signal needs to be output.
Step S140, generating a corresponding output instruction, and sending the output instruction to the register of the field programmable gate array 200, so that the field programmable gate array 200 outputs the digital signal and/or the PWM signal.
In this embodiment, considering that the IO resources and the operation rate of the programmable logic controller 100 are limited, the field programmable gate array 200 may be controlled to output a corresponding digital signal or PWM signal.
Therefore, when it is determined that the digital signal and/or the PWM signal needs to be output through step S130, a corresponding output command may be generated by performing step S140. And, the output instruction may be sent to a register of the field programmable gate array 200 to cause the field programmable gate array 200 to output the digital signal and/or the PWM signal.
Optionally, a mode of generating the output instruction is not limited, and may be selected according to an actual application requirement. For example, in a possible example, if the PWM signal needs to be output, in conjunction with fig. 4, step S140 may include step S141 and step S143, which is described in detail below.
And step S141, calculating according to the frequency value and the duty ratio of the PWM signal and a preset formula to obtain a high level count value and a low level count value of the PWM signal.
Step S143, sending the high level count value and the low level count value to the register of the field programmable gate array 200.
In this embodiment, the high-level count value and the low-level count value may be calculated in the programmable logic controller 100 in consideration of the operation resources of the field programmable gate array 200 and other factors. Therefore, when it is determined that the PWM signal needs to be output, the corresponding high-level count value and low-level count value can be calculated based on the frequency value and duty ratio of the PWM signal. Then, the high-level count value and the low-level count value are sent to the field programmable gate array 200 as the output instruction, so that the field programmable gate array 200 can output the corresponding PWM signal based on the high-level count value and the low-level count value.
The specific content of the preset formula for calculating the high-level count value and the low-level count value is not limited, and can be selected according to the actual application requirements. For example, in one possible example, the preset formula may include:
cnth＝109*(Dc/104)/Freq/Ts；
cntl＝109*(1-Dc/104)/Freq/Ts；
wherein, cnthIs a high level count value, cntlIs a low level count value, Dc is the duty cycle, Freq is the frequency value, Ts is the clock period of the field programmable gate array 200.
Note that the quantization unit of the duty ratio Dc may be 0.01%, the unit of the frequency value Freq may be Hz, and the unit of the clock period Ts may be ns.
In addition, the mode of outputting the corresponding PWM signal based on the high-level count value and the low-level count value is not limited, and can be selected according to the actual application requirements. For example, in a possible example, when receiving the high-level count value and the low-level count value, the field programmable gate array 200 may first perform countdown with the high-level count value as an initial value under the driving of a clock until the count value is 0, and then perform corresponding countdown with the low-level count value as the initial value until the count value is 0. By repeatedly performing the above described down-count operation, the output of the PWM signal can be realized.
Further, in order to realize the acquisition of the analog signal, in this embodiment, with reference to fig. 5, the programmable logic controller 100 may further connect to an ADC chip through an SPI interface, and the IO signal processing method may further include step S150 and step S160, which are described in detail below.
And step S150, judging whether the analog signal acquired by the ADC chip needs to be acquired.
Step S160, obtaining an original code value corresponding to the analog signal from the register of the ADC chip, and converting the original code value into a mapping code value that can be identified by an upper computer connected to the programmable logic controller 100 according to a first preset relationship.
In this embodiment, the ADC chip is used to collect and store analog signals. Therefore, when the programmable logic controller 100 determines that the analog signal needs to be obtained, the original code value corresponding to the analog signal may be obtained from the register of the ADC chip.
In addition, in order to control a connected upper computer through the analog signal, the original code value can be converted into a mapping code value which can be identified by the upper computer, and the mapping code value is sent to the upper computer.
Optionally, specific contents of the first preset relationship for converting the original code value into the mapped code value are not limited, and may be selected according to actual application requirements. For example, in an alternative example, the first preset relationship may include:
MAPCODE＝(a1*CODE+b1)*103/1.221；
wherein MAPCODE is a mapping CODE value, CODE is an original CODE value, a1And b1The parameters are calibrated for a predetermined acquisition.
It should be noted that, the manner of determining the acquisition calibration parameters may be performed by an acquisition calibration module. For example, CODE values corresponding to 2mA, 10mA and 20mA can be collected to obtain CODE2mA、CODE10mAAnd CODE20mAThen, the acquisition calibration parameter a is calculated by the following formula1And b1：
Further, in order to realize output of the analog signal, in this embodiment, with reference to fig. 6, the programmable logic controller 100 may further connect to a DAC chip through an SPI interface, and the IO signal processing method may further include step S170 and step S180, which is described in detail below.
And step S170, judging whether an analog signal needs to be output through the DAC chip.
Step S180, converting a mapping code value issued by an upper computer connected to the programmable logic controller 100 into an original code value identifiable by the DAC chip according to a second preset relationship, and sending the original code value to the DAC chip to control the DAC chip to output the analog signal.
In this embodiment, after receiving the mapping code value issued by the upper computer, it may be determined that a corresponding analog signal needs to be output through the DAC chip. Therefore, the mapped code value can be firstly converted into an original code value which can be identified by the DAC chip, and the original code value is sent to the DAC chip so as to control the DAC chip to output the analog signal.
Optionally, specific contents of the second preset relationship for converting the mapping code value into the original code value are not limited, and may be selected according to actual application requirements. For example, in an alternative example, the second preset relationship may include:
wherein MAPCODE is a mapping CODE value, CODE is an original CODE value, a2And b2The parameters are calibrated for a predetermined output.
It should be noted that, the manner of determining the output calibration parameter may be performed by a set output calibration module. For example, the DAC chip may be set with the original code values of 200, 2000, and 4000, respectively, and the corresponding output currents may be collected to obtain current1, current2, and current3, respectively, and then the collection calibration parameter a may be calculated by the following formula2And b2：
To sum up, the IO signal processing method and the programmable logic controller 100 provided by the present application establish a connection between the programmable logic controller 100 and the field programmable gate array 200 to acquire and acquire data based on the field programmable gate array 200, so that the programmable logic controller 100 can also solve the problems of insufficient IO resources and low operation efficiency on the basis of the advantages of small size and compact structure, and has a very high practical value.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus and method embodiments described above are illustrative only, as the flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, an electronic device, or a network device) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (8)
1. An IO signal processing method is characterized in that the method is applied to a programmable logic controller under an industrial environment, the number of I/O points of the programmable logic controller is less than 256, and a field programmable gate array for collecting signals is connected with the programmable logic controller, and the method comprises the following steps:
judging whether a digital signal and/or a high-speed pulse signal acquired by the field programmable gate array need to be acquired or not;
if the digital signal and/or the high-speed pulse signal need to be acquired, reading a register of the field programmable gate array to acquire the digital signal and/or the high-speed pulse signal;
judging whether a digital signal and/or a PWM signal needs to be output or not;
if the digital signal and/or the PWM signal needs to be output, generating a corresponding output instruction, and sending the output instruction to a register of the field programmable gate array so that the field programmable gate array outputs the digital signal and/or the PWM signal;
if the signal needing to be output is a PWM signal, calculating a high level count value and a low level count value of the PWM signal according to a preset formula according to the frequency value and the duty ratio of the PWM signal;
and sending the high-level counting value and the low-level counting value to a register of the field programmable gate array.
2. The IO signal processing method according to claim 1, wherein the preset formula includes:
wherein, cnthIs a high level count value, cntlThe low level count value, Dc the duty cycle, Freq the frequency value, Ts the clock period of the FPGA.
3. An IO signal processing method according to claim 1 or 2, wherein the programmable logic controller is further connected to an ADC chip for acquiring an analog signal through an SPI interface, and the method further includes:
judging whether analog signals acquired by the ADC chip need to be acquired or not;
if the analog signal needs to be acquired, acquiring an original code value corresponding to the analog signal from a register of the ADC chip, and converting the original code value into a mapping code value which can be identified by an upper computer connected with the programmable logic controller according to a first preset relation.
4. The IO signal processing method according to claim 3, wherein the first preset relationship includes:
wherein MAPCODE is a mapping CODE value, CODE is an original CODE value, a1And b1The parameters are calibrated for a predetermined acquisition.
5. An IO signal processing method according to claim 1 or 2, wherein the programmable logic controller is further connected to a DAC chip for outputting an analog signal through an SPI interface, the method further comprising:
judging whether an analog signal needs to be output through the DAC chip or not;
if the analog signal needs to be output, converting a mapping code value sent by an upper computer connected with the programmable logic controller into an original code value which can be identified by the DAC chip according to a second preset relation, and sending the original code value to the DAC chip so as to control the DAC chip to output the analog signal.
6. The IO signal processing method according to claim 5, wherein the second preset relationship includes:
wherein CODE is the original CODE value, MAPCODE is the mapping CODE value, a2And b2The parameters are calibrated for a predetermined output.
7. A programmable logic controller, comprising:
a storage unit;
a processing unit;
a computer program stored in the storage unit and capable of running on the processing unit, the computer program implementing the IO signal processing method according to any one of claims 1 to 6 when running;
the I/O point number of the programmable logic controller is less than 256, and the programmable logic controller is connected with a field programmable gate array for collecting signals.
8. The programmable logic controller of claim 7, wherein the programmable logic controller has 24 digital signal acquisition channels, 45 digital signal output channels, 14 analog signal acquisition channels, 2 analog signal output channels, 8 high speed pulse signal acquisition channels, and 24 PWM signal output channels.
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| CN102760111A (en) * | 2012-06-27 | 2012-10-31 | 浙江大学 | FPGA-based (Field Programmable Gate Array) extended multi-serial port device and data receiving-transmitting method thereof |
| CN203588252U (en) * | 2013-11-30 | 2014-05-07 | 成都天奥信息科技有限公司 | Upgrading circuit for FPGA (Field Programmable Gate Array) configuration program |
| CN107024911A (en) * | 2017-05-03 | 2017-08-08 | 中国核动力研究设计院 | A kind of nuclear power plant's numerical control system Logical processing unit |
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