CN202818339U - AFDX time delay measuring device - Google Patents
AFDX time delay measuring device Download PDFInfo
- Publication number
- CN202818339U CN202818339U CN201220457293.2U CN201220457293U CN202818339U CN 202818339 U CN202818339 U CN 202818339U CN 201220457293 U CN201220457293 U CN 201220457293U CN 202818339 U CN202818339 U CN 202818339U
- Authority
- CN
- China
- Prior art keywords
- circuit
- time
- data processing
- pulse
- transmitting terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The utility model discloses an AFDX (Avionics Full Duplex Switched Ethernet) time delay measuring device, and relates to the technology of aviation bus ARINC 664 test. The AFDX time delay measuring device disclosed by the utility model comprises: a transmitting end data processing circuit for transmitting a data package used for measuring time delay and triggering a transmitting end pulse-generating circuit to work while transmitting the data package; the transmitting end pulse-generating circuit for generating a pulse signal and transmitting the pulse signal to a calculating circuit when receiving the trigger; a receiving end data processing circuit for receiving the data package used for measuring time delay and triggering a receiving end pulse-generating circuit to work while receiving the data package; the receiving end pulse-generating circuit for generating a pulse signal and transmitting the pulse signal to the calculating circuit when receiving the trigger; and the calculating circuit for calculating data transmission time delay between a transmitting end and a receiving end according to the received two pulse signals. By adopting the technical scheme of the AFDX time delay measuring device of the utility model, measurement for network time delay can be more accurate, thereby raising reliability of measurement of the time delay.
Description
Technical field
The utility model relates to aviation bus ARINC 664 technical field of measurement and test, is specifically related to a kind of avionics full duplex real-time ethernet latency measurement device.
Background technology
AFDX (Avionics Full Duplex Switched Ethernet, avionics full duplex real-time ethernet) be Airbus SAS according to the ARINC664 standard, the technology that realizes for the aircraft data network (Aircraft Data Networks) of determining.Be widely used at present interconnecting electronic system in the aviation aircraft is such as engine, flight-control component, cruise system etc.Up to now, AFDX has used at A380, in A400M and the Boeing B787 project.And based on the equipment of this agreement also increasing, so be sought after very perfect testing scheme this kind equipment is tested.And the Time delay measurement of Network Environment is an important indicator of this network, but do not have at present good testing scheme to measure.
The utility model content
Technical problem to be solved in the utility model is, a kind of avionics full duplex real-time ethernet latency measurement device is provided, and makes the measurement of network delay more accurate.
In order to solve the problems of the technologies described above, the utility model discloses a kind of avionics full duplex real-time ethernet latency measurement device, comprise transmitting terminal data processing circuit, transmitting terminal pulse-generating circuit, receiving terminal data processing circuit, receiving terminal pulse-generating circuit and counting circuit, wherein:
Described transmitting terminal data processing circuit sends the packet that is used for measuring time-delay to described receiving terminal data processing circuit, and triggers the work of described transmitting terminal pulse-generating circuit when sending packet;
Described transmitting terminal pulse-generating circuit when receiving the triggering of described transmitting terminal data processing circuit, produces a pulse signal and issues described counting circuit;
Described receiving terminal data processing circuit receives described transmitting terminal data processing circuit and sends the packet that is used for measuring time-delay, and trigger the work of described receiving terminal pulse-generating circuit in the receive data bag;
Described receiving terminal pulse-generating circuit when receiving the triggering of described receiving terminal data processing circuit, produces a pulse signal and issues described counting circuit;
Described counting circuit receives the pulse signal of described transmitting terminal pulse-generating circuit transmission and the pulse signal that described receiving terminal pulse-generating circuit produces, and delays time according to the transfer of data that two pulse signals that receive calculate between transmitting terminal and the receiving terminal.
Preferably, in the above-mentioned avionics full duplex real-time ethernet latency measurement device, described counting circuit respectively with described receiving terminal data processing circuit be connected the receiving terminal pulse-generating circuit and be connected, described transmitting terminal pulse-generating circuit by described receiving terminal data processing circuit with pulse signal and issue described counting circuit.
Preferably, in the above-mentioned avionics full duplex real-time ethernet latency measurement device, described counting circuit respectively with described transmitting terminal data processing circuit be connected the transmitting terminal pulse-generating circuit and be connected, described receiving terminal pulse-generating circuit by described transmitting terminal data processing circuit with pulse signal and issue described counting circuit.
Preferably, in the above-mentioned avionics full duplex real-time ethernet latency measurement device, the pulse signal that the pulse signal that described transmitting terminal data processing circuit produces and described receiving terminal pulse-generating circuit produce is identical or different.
The invention also discloses a kind of avionics full duplex real-time ethernet latency measurement device, comprise markers injection circuit, transmitting terminal data processing circuit, receiving terminal data processing circuit, markers writing circuit and counting circuit, wherein:
Described markers injection circuit injects the time scale information of delivery time and sends to described transmitting terminal data processing circuit in measurement is delayed time with packet;
Described transmitting terminal data processing circuit arrives described receiving terminal data processing circuit with the measurement time-delay that described markers injection circuit sends with Packet Generation;
Described receiving terminal data processing circuit receives described test time-delay and use packet, therefrom extracts described test time-delay with Packet Generation time scale information constantly, and the time scale information that described test was delayed time with packet time of reception sends to described counting circuit;
Described markers writing circuit records described test time-delay with the packet time scale information of the time of reception, and described test time-delay is sent to described counting circuit with the time scale information of packet time of reception;
Described counting circuit with the time scale information in the Packet Generation moment and the time scale information of the time of reception, calculates the transfer of data time-delay between transmitting terminal and the receiving terminal according to described test time-delay.
Preferably, above-mentioned avionics full duplex real-time ethernet latency measurement device also comprises:
Markers is unified the initial time of described markers injection circuit and described markers writing circuit to circuit.
Adopt the present techniques scheme to make the measurement of network delay more accurate, thereby improve the reliability of latency measurement.
Description of drawings
Fig. 1 is the fundamental diagram of AFDX latency measurement device among the embodiment 1;
Fig. 2 is AFDX latency measurement apparatus structure schematic diagram among the embodiment 1;
Fig. 3 is AFDX latency measurement apparatus structure schematic diagram in concrete the application;
Fig. 4 is AFDX latency measurement apparatus structure schematic diagram among the embodiment 2.
Embodiment
For making the purpose of this utility model, technical scheme and advantage clearer, hereinafter in connection with accompanying drawing technical solutions of the utility model are described in further detail.Need to prove that in the situation of not conflicting, the application's embodiment and the feature among the embodiment can make up arbitrarily mutually.
Embodiment 1
Present embodiment provides a kind of AFDX latency measurement device, can accurately measure test packet transmission delay in the AFDX network environment.
The utility model is based on the hardware environment of AFDX test card-AFDX test card, and wherein hardware environment provides the triggering signal of standard Transistor-Transistor Logic level output for test.Data processing module on the hardware provides and receives the corresponding one by one of Time delay measurement packet and a triggering signal for test provides the corresponding one by one of the packet of Time delay measurement and trigger output signal.Like this, when the transmitting terminal of test sends a message, produce an internal trigger output signal, and output to the external trigger interface.Then the receiving terminal of test produces an internal trigger output signal when receiving this message, and is linked to the external trigger interface, thereby calculates the transmission delay between transmitting terminal and the receiving terminal.This principle as shown in Figure 1.
Based on above-mentioned principle, the AFDX latency measurement device that present embodiment provides comprises transmitting terminal data processing circuit, transmitting terminal pulse-generating circuit, receiving terminal data processing circuit, receiving terminal pulse-generating circuit and counting circuit as shown in Figure 2.
The transmitting terminal data processing circuit sends the packet that is used for measuring time-delay to the receiving terminal data processing circuit, and triggers the work of transmitting terminal pulse-generating circuit when sending packet;
The transmitting terminal pulse-generating circuit when receiving the triggering of transmitting terminal data processing circuit, produces a pulse signal and issues counting circuit;
The receiving terminal data processing circuit, the receiving end/sending end data processing circuit sends the packet that is used for measuring time-delay, and triggers the work of receiving terminal pulse-generating circuit in the receive data bag;
The receiving terminal pulse-generating circuit when receiving the triggering of receiving terminal data processing circuit, produces a pulse signal and issues counting circuit;
The pulse signal that the pulse signal that counting circuit, receiving end/sending end pulse-generating circuit send and receiving terminal pulse-generating circuit produce, and calculate transfer of data time-delay between transmitting terminal and the receiving terminal according to two pulse signals that receive.
Need to prove that the pulse signal that above-mentioned transmitting terminal pulse-generating circuit and receiving terminal pulse-generating circuit produce can be identical or different.
In addition, above-mentioned counting circuit can place transmitting terminal, also can place receiving terminal.When counting circuit places transmitting terminal, counting circuit is connected respectively the transmitting terminal pulse-generating circuit and is connected with the transmitting terminal data processing circuit, the receiving terminal pulse-generating circuit (is after the receiving terminal pulse-generating circuit produces pulse signal by the transmitting terminal data processing circuit to counting circuit transmitted signal then, pulse signal is sent to the transmitting terminal treatment circuit, and the transmitting terminal treatment circuit is transmitted to local counting circuit again).
When counting circuit placed receiving terminal, counting circuit was connected respectively the receiving terminal pulse-generating circuit and is connected with the receiving terminal data processing circuit, the transmitting terminal pulse-generating circuit then by the receiving terminal data processing circuit to counting circuit transmitted signal.
The below introduces above-mentioned AFDX latency measurement device in detail in conjunction with application scenarios again, suppose and above-mentioned transmitting terminal data processing circuit and transmitting terminal impulse circuit can be placed a test card, referred to as the transmitting terminal test card, receiving terminal data processing circuit, transmitting terminal impulse circuit and counting circuit are placed a test card, referred to as the receiving terminal test card, at this moment, whole measurement mechanism as shown in Figure 3.
The transmitting terminal test card sends the receiving terminal test card that arrives the opposite end for the packet of measurement time-delay, and passes through pulse signal of triggering signal output port transmission to the receiving terminal test card when sending packet.Need to prove that above-mentioned triggering signal output port is the pre-configured port that is used for the transmitted signal, but this port is not limited in the transmitted signal.
The receiving terminal test card, packet and pulse signal that the receiving end/sending end test card sends, and when receiving packet, produce an internal pulse signal identical with the pulse signal length of transmitting terminal test card transmission, according to the transfer of data time-delay between the pulse signal that receives and internal pulse signal calculating transmitting terminal test card and the test of this receiving terminal.
Wherein, data processing circuit can adopt programmable logic chip FPGA to realize the data processing in the transmitting terminal test card, be used for measuring the packet of delaying time to send to the receiving terminal test card, and when sending packet, trigger pulse-generating circuit work in the transmitting terminal test card.
Data processing circuit also can adopt programmable logic chip FPGA to realize the data processing in the receiving terminal test card.And counting circuit can be realized by programmable logic chip FPGA.
In addition, also may need to prepare oscilloscope to the test of network environment, namely when the transmission delay of certain two end node in the test network environment, the trigger output signal of above-mentioned transmitting terminal test card and receiving terminal test card can also be received on the oscilloscope.By host computer the relation between triggering signal and the corresponding packet is shone upon one by one.Like this, the internal pulse signal that the pulse signal that the transmitting terminal test card sends and receiving terminal test card produce all can be connected to oscilloscope, so that the user sees transfer of data time-delay between transmitting terminal and the receiving terminal intuitively by oscilloscope.
Also will illustrate, also can include counting circuit in the above-mentioned transmitting terminal test card, like this, in different test processs, it namely can be used as data receiver and also can be used as the data receiver.Same, above-mentioned receiving terminal test card also may be as data receiver in other test processs.
Embodiment 2
Present embodiment provides a kind of AFDX latency measurement device, as shown in Figure 4, comprises markers injection circuit, transmitting terminal data processing circuit, receiving terminal data processing circuit, markers writing circuit and counting circuit.
The markers injection circuit injects the time scale information of delivery time and sends to the transmitting terminal data processing circuit in measurement is delayed time with packet;
The transmitting terminal data processing circuit arrives the receiving terminal data processing circuit with the measurement time-delay that the markers injection circuit sends with Packet Generation;
The receiving terminal data processing circuit receives the test time-delay and use packet, therefrom extracts described test time-delay with Packet Generation time scale information constantly, and will test the time scale information of delaying time with packet time of reception and send to counting circuit;
Markers writing circuit, record test time-delay be with the packet time scale information of the time of reception, and the test time-delay is sent to counting circuit with the time scale information of packet time of reception;
Counting circuit with the time scale information in the Packet Generation moment and the time scale information of the time of reception, calculates the transfer of data time-delay between transmitting terminal and the receiving terminal according to the test time-delay.
In concrete the application, markers injection circuit and transmitting terminal data processing circuit can be placed same test card, referred to as the transmitting terminal test card.In like manner, also receiving terminal data processing circuit, markers writing circuit and counting circuit can be placed same test card, referred to as the receiving terminal test card.
Transmitting terminal test card, transmission are measured time-delay with the receiving terminal test card of packet to the opposite end, wherein measure and delay time with the time scale information that carries delivery time in the packet.
The receiving terminal test card, the test time-delay packet that the receiving end/sending end test card sends, and the time scale information of record when receiving packet, according to test time-delay with the time scale information of delivery time in the packet and record receive packet the time time scale information, the transfer of data of calculating between the test of transmitting terminal test card and this receiving terminal is delayed time.
Need to prove that for the reliability that guarantees to calculate, can also increase by a markers to circuit, this circuit is unified the initial time of markers injection circuit and markers writing circuit, guarantees that namely transmitting terminal and receiving terminal have unified timing system.
The above is preferred embodiments of the present utility model only, is not be used to limiting protection range of the present utility model.All within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., all should be included within the protection range of the present utility model.
Claims (6)
1. an avionics full duplex real-time ethernet latency measurement device is characterized in that this device comprises transmitting terminal data processing circuit, transmitting terminal pulse-generating circuit, receiving terminal data processing circuit, receiving terminal pulse-generating circuit and counting circuit, wherein:
Described transmitting terminal data processing circuit sends the packet that is used for measuring time-delay to described receiving terminal data processing circuit, and triggers the work of described transmitting terminal pulse-generating circuit when sending packet;
Described transmitting terminal pulse-generating circuit when receiving the triggering of described transmitting terminal data processing circuit, produces a pulse signal and issues described counting circuit;
Described receiving terminal data processing circuit receives described transmitting terminal data processing circuit and sends the packet that is used for measuring time-delay, and trigger the work of described receiving terminal pulse-generating circuit in the receive data bag;
Described receiving terminal pulse-generating circuit when receiving the triggering of described receiving terminal data processing circuit, produces a pulse signal and issues described counting circuit;
Described counting circuit receives the pulse signal of described transmitting terminal pulse-generating circuit transmission and the pulse signal that described receiving terminal pulse-generating circuit produces, and delays time according to the transfer of data that two pulse signals that receive calculate between transmitting terminal and the receiving terminal.
2. avionics full duplex real-time ethernet latency measurement device as claimed in claim 1 is characterized in that,
Described counting circuit respectively with described receiving terminal data processing circuit be connected the receiving terminal pulse-generating circuit and be connected, described transmitting terminal pulse-generating circuit by described receiving terminal data processing circuit with pulse signal and issue described counting circuit.
3. avionics full duplex real-time ethernet latency measurement device as claimed in claim 1 is characterized in that,
Described counting circuit respectively with described transmitting terminal data processing circuit be connected the transmitting terminal pulse-generating circuit and be connected, described receiving terminal pulse-generating circuit by described transmitting terminal data processing circuit with pulse signal and issue described counting circuit.
4. such as each described avionics full duplex real-time ethernet latency measurement device of claims 1 to 3, it is characterized in that,
The pulse signal that the pulse signal that described transmitting terminal data processing circuit produces and described receiving terminal pulse-generating circuit produce is identical or different.
5. an avionics full duplex real-time ethernet latency measurement device is characterized in that this device comprises markers injection circuit, transmitting terminal data processing circuit, receiving terminal data processing circuit, markers writing circuit and counting circuit, wherein:
Described markers injection circuit injects the time scale information of delivery time and sends to described transmitting terminal data processing circuit in measurement is delayed time with packet;
Described transmitting terminal data processing circuit arrives described receiving terminal data processing circuit with the measurement time-delay that described markers injection circuit sends with Packet Generation;
Described receiving terminal data processing circuit receives described test time-delay and use packet, therefrom extracts described test time-delay with Packet Generation time scale information constantly, and the time scale information that described test was delayed time with packet time of reception sends to described counting circuit;
Described markers writing circuit records described test time-delay with the packet time scale information of the time of reception, and described test time-delay is sent to described counting circuit with the time scale information of packet time of reception;
Described counting circuit with the time scale information in the Packet Generation moment and the time scale information of the time of reception, calculates the transfer of data time-delay between transmitting terminal and the receiving terminal according to described test time-delay.
6. avionics full duplex real-time ethernet latency measurement device as claimed in claim 5 is characterized in that, also comprises:
Markers is unified the initial time of described markers injection circuit and described markers writing circuit to circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220457293.2U CN202818339U (en) | 2012-09-07 | 2012-09-07 | AFDX time delay measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201220457293.2U CN202818339U (en) | 2012-09-07 | 2012-09-07 | AFDX time delay measuring device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202818339U true CN202818339U (en) | 2013-03-20 |
Family
ID=47877142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201220457293.2U Expired - Lifetime CN202818339U (en) | 2012-09-07 | 2012-09-07 | AFDX time delay measuring device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202818339U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516508A (en) * | 2013-09-17 | 2014-01-15 | 中国科学院计算技术研究所 | Method and system for correcting clock drift in one-way and two-way delay variation measurement |
| CN105515908A (en) * | 2015-12-10 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | AFDX photoelectric conversion time delay test method |
| CN105510853A (en) * | 2015-11-24 | 2016-04-20 | 深圳怡化电脑股份有限公司 | Method and system for measuring time delay of magnetic sensor |
| CN109104312A (en) * | 2018-08-13 | 2018-12-28 | 北京航测精仪科技有限公司 | A kind of configurable AFDX bus data frame latency device and AFDX data frame time-delay method |
| CN109194551A (en) * | 2018-11-09 | 2019-01-11 | 上海仁童电子科技有限公司 | A kind of real-time ethernet equipment performance test method, apparatus and system |
| CN109327700A (en) * | 2018-11-23 | 2019-02-12 | 中国电子科技集团公司第五十四研究所 | A kind of image coding and decoding time delay measuring method based on SEI transmission |
| CN111585836A (en) * | 2020-04-26 | 2020-08-25 | 工业互联网创新中心（上海）有限公司 | Network testing method and device |
-
2012
- 2012-09-07 CN CN201220457293.2U patent/CN202818339U/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103516508A (en) * | 2013-09-17 | 2014-01-15 | 中国科学院计算技术研究所 | Method and system for correcting clock drift in one-way and two-way delay variation measurement |
| CN103516508B (en) * | 2013-09-17 | 2016-07-06 | 中国科学院计算技术研究所 | A kind of unidirectional and two-way delay variation revises the method and system of clock drift in measuring |
| CN105510853A (en) * | 2015-11-24 | 2016-04-20 | 深圳怡化电脑股份有限公司 | Method and system for measuring time delay of magnetic sensor |
| CN105515908A (en) * | 2015-12-10 | 2016-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | AFDX photoelectric conversion time delay test method |
| CN109104312A (en) * | 2018-08-13 | 2018-12-28 | 北京航测精仪科技有限公司 | A kind of configurable AFDX bus data frame latency device and AFDX data frame time-delay method |
| CN109194551A (en) * | 2018-11-09 | 2019-01-11 | 上海仁童电子科技有限公司 | A kind of real-time ethernet equipment performance test method, apparatus and system |
| CN109327700A (en) * | 2018-11-23 | 2019-02-12 | 中国电子科技集团公司第五十四研究所 | A kind of image coding and decoding time delay measuring method based on SEI transmission |
| CN111585836A (en) * | 2020-04-26 | 2020-08-25 | 工业互联网创新中心（上海）有限公司 | Network testing method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN202818339U (en) | AFDX time delay measuring device | |
| CN101098219A (en) | Correcting time synchronisation inaccuracy caused by asymmetric delay on a communication link | |
| US20200124709A1 (en) | Circuit, method and related chip for time measurement, system, and device | |
| AU2013204757A1 (en) | Synchronisation of a system of distributed computers | |
| CN104022828A (en) | Fiber data transmission method based on asynchronous communication mode | |
| CN110928176B (en) | Multifunctional time service equipment supporting multiple time service technologies | |
| US20100293243A1 (en) | method and apparatus for measuring directionally differentiated (one-way) network latency | |
| CN101304344B (en) | Apparatus and method for calibrating time delay of network performance tester | |
| CN101373205B (en) | Returning ring test structure of IC chip interface module | |
| WO2022019984A1 (en) | System and method for synchronizing nodes in a network device | |
| CN102508804A (en) | Secure digital (SD)/secure digital input and output (SDIO) master controller | |
| CN106301657B (en) | High time precision large space channel synchronization acquisition system | |
| CN113726592A (en) | Transmission delay testing method and system of edge server and related components | |
| CN216526795U (en) | Interface circuit of network time precision monitoring method of time-service equipment | |
| CN114268563B (en) | Method for precisely measuring time-triggered Ethernet transparent clock | |
| CN202940827U (en) | Avionic full duplex real-time Ethernet data pre-processing device | |
| Champion et al. | TiCkS: A flexible White-Rabbit based time-stamping board | |
| US11146273B2 (en) | Electronic device and electronic product | |
| CN103684730A (en) | Time synchronization method | |
| Vinogradov et al. | Device for measuring one-way network delay with microsecond accuracy | |
| CN202617149U (en) | High-precision IP (Internet Protocol) network one-way time delay measuring device | |
| CN101949681B (en) | System and method for measuring length of twisted pair based on RS485 bus signal transmission delay | |
| CN114509722A (en) | Angle measuring method, system and related device | |
| CN109361567A (en) | A kind of method and device of test lot product UART communication compatibility | |
| CN110071851B (en) | System and method for measuring flight test data delay |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130320 |