CN101304344B - Apparatus and method for calibrating time delay of network performance tester - Google Patents
Apparatus and method for calibrating time delay of network performance tester Download PDFInfo
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- CN101304344B CN101304344B CN 200810114264 CN200810114264A CN101304344B CN 101304344 B CN101304344 B CN 101304344B CN 200810114264 CN200810114264 CN 200810114264 CN 200810114264 A CN200810114264 A CN 200810114264A CN 101304344 B CN101304344 B CN 101304344B
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Abstract
The invention discloses a time delay calibration device for network performance testing instruments and also discloses a method for time delay parameter calibration by the time delay calibration device. The time delay calibration device comprises a serial interface, a control unit, a time delay control unit, a memory and an Ethernet interface circuit; wherein, the time delay control unit is connected with the control unit, the memory and the Ethernet interface circuit respectively, and the control unit is connected with the serial interface which is used for connecting a console. The Ethernet interface circuit is used for connecting the network performance testing instruments. The time delay calibration device controls the corresponding memory by FPGA to realize the addition of the time delay, and the accuracy of the time delay addition has no relation with the line rate. Meanwhile, the accuracy of the time delay addition is high, which can meet the time delay parameter measurement and calibration requirement of the most accurate network performance testing instruments at present.
Description
Technical field
The present invention relates to a kind of time delay of network performance tester calibrating installation and method thereof, relate in particular to and a kind ofly realize the method that time delay of network performance tester calibrating installation that time delay adds and this time delay calibrating installation are realized the delay parameter calibration by the relevant memory of FPGA control, belong to the communication field of measuring techniques.
Background technology
At present, the data communication network of China has obtained greatly developing, and has formed the nationwide network system.Data service shared proportion in whole communication service significantly rises.Particularly along with the development of next generation network technology, communication industry is to making the transition take data communication network as basic direction fully.Therefore, data communication network will play an increasingly important role as the basis of whole communication network.
In data communication network, network performance testing system is for detection of the specific performance index of tested network or the network equipment, such as throughput, delay, packet loss etc., it is a kind of important means of estimating exactly the performance of under the heterogeneous networks load tested network or the network equipment.Complete network performance testing system is comprised of network test equipment and control desk two parts.Wherein, network test equipment is used for realizing test port, finish the basic function of test, comprise the generation of measurement, route message of the generation of test traffic and reception, test statistics and message intercepting etc., in whole test process, bringing into play indispensable important function.Control desk is generally realized by PC, is used for providing User Interface, comprises setting, analysis of test results and the demonstration etc. of test parameter.
Network test equipment is divided according to function, can be divided into two large classes.The first kind is protocol analyzer, is used for realization to the analysis of Code And Decode, traffic statistics and the carrying content of ICP/IP protocol, IP routing protocol, ATM agreement.The protocol analyzer of part also possesses the function of emulation ICP/IP protocol, IP routing protocol and ATM agreement.Equations of The Second Kind is network performance tester, is used for realizing data forwarded performance test.Main test event is four parameters of network performance, i.e. the throughput of data network (Throughput), time delay (Latency), frame loss rate (FrameLoss Rate) and back-to-back performance (Back to Back).
In four parameters of above-mentioned network performance, time delay comprises packet queuing delay, propagation delay time, Forwarding Delay, is the important indicator that affects user awareness.Therefore, delay parameter is an important parameter that needs carry out measuring fixed amount, calibration.But the accuracy of measuring for delay parameter at present lacks unified standard.From the performance index that each network performance tester producer provides, the diverse network ability meter differs larger for the accuracy of measurement of delay parameter.The resolution of some network performance testers can reach Microsecond grade, and some network performance testers can only reach Millisecond.Some network performance testers are higher to the accuracy of latency measurement when speed is low on the line, but in the situation that the higher measurement to delay parameter of line speed is not very accurate just.This has just made obstacle for service quality objective, that estimate relevant telecommunication service operator exactly.
Summary of the invention
For the existing deficiency of prior art, primary and foremost purpose of the present invention provides a kind of time delay of network performance tester calibrating installation (being called for short the time delay calibrating installation).This time delay calibrating installation can be in the situation that the accuracy of different rates, different test frame length calibration network ability meters measurement delay parameters.
Another object of the present invention provides the concrete grammar that utilizes above-mentioned time delay of network performance tester calibrating installation calibration delay parameter.
For realizing above-mentioned goal of the invention, the present invention adopts following technical scheme:
A kind of time delay of network performance tester calibrating installation, the delay parameter for the calibration network ability meter is characterized in that:
Described time delay of network performance tester calibrating installation is comprised of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit;
Described time delay control unit connects respectively described control unit, memory and ethernet interface circuit, and described control unit connects described serial port circuit;
Described serial port circuit is used for connecting control desk, and described ethernet interface circuit is used for connecting described network performance tester.
Wherein, described time delay control unit is comprised of cache module, time delay control module, package forward module and speed adjusting module, described time delay control module is connected between described ethernet interface circuit and the described cache module, and the data that are used for described ethernet interface circuit place is received write described cache module.
Described time delay control module, package forward module and speed adjusting module are realized by coding on the programmable gate array chip at the scene.
Described control unit is any one in CPU, single-chip microcomputer or the digital signal processor.
Described memory is any one among SDRAM or the FLASH.
In the situation that be operated in the 10/100Base-T Ethernet, two time delay control unit that correspond respectively to up direction and down direction share same memory.
In the situation that be operated in the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet, two time delay control unit that correspond respectively to up direction and down direction are used respectively independent memory.
When needs join delay, the time delay settings of link direction, interface type and each direction that need to join delay at first are set, then by control unit the time delay settings of receiving are converted to the count pulse of timer; Time delay control module in the time delay control unit will write cache module from the Frame data that ethernet interface circuit is received, and start the time delay timer; After the timing of time delay timer had arrived, the time delay control module read the corresponding data frame data from cache module, and sent to the ethernet interface circuit place.
When needs were adjusted interface rate, ethernet interface circuit was synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again; Timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module; The speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
Compared with prior art, time delay calibrating installation provided by the present invention adopts hardware mode to join delay, and namely controls the adding that corresponding memory is realized time delay by FPGA.This mode has advantages of as follows:
1. the accuracy of time delay adding and line speed are irrelevant, and the data that namely no matter enter the time delay calibrating installation are that very low speed or wire rate (maximum rate that can reach in theory) can both accurately be realized the Frame that enters is added stable setting time delay;
2. the accuracy of time delay adding is very high.Relevant test proof, the expanded uncertainty that uses this time delay calibrating installation to join delay is (0.2+ time delay settings * 10
-6) microsecond, therefore spreading factor k=2 can satisfy at present the delay parameter measurement and calibration requirement of accurate network performance tester.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing:
Fig. 1 is the working state schematic representation of time delay of network performance tester calibrating installation provided by the present invention;
Fig. 2 is the overall structure block diagram of time delay calibrating installation shown in Figure 1;
Fig. 3 is the embodiment schematic diagram that is applicable to the time delay calibrating installation of 10/100Base-T Ethernet;
Fig. 4 is the embodiment schematic diagram that is applicable to the time delay calibrating installation of 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet;
Fig. 5 is that this time delay calibrating installation is realized the schematic flow sheet that time delay adds;
Fig. 6 is that this time delay calibrating installation is realized the schematic flow sheet that interface rate is adjusted.
Embodiment
Referring to shown in Figure 1, time delay calibrating installation provided by the present invention is connected with control desk with network performance tester respectively when carrying out the time delay calibration operation.The ethernet data frame (including but not limited to the Frame of Ethernet II, IEEE802.3 form) that network performance tester will be tested usefulness sends to the time delay calibrating installation from a port, and the test that the time delay calibrating installation will be received is carried out passing through the loopback of another one port to network performance tester after the time delay processing with ethernet data frame.Then compare the time delay of time delay calibrating installation adding and the time delay that network performance tester measures.The result who utilizes the value calibration network performance tester of time delay calibrating installation to measure.Control desk is realized by PC.This control desk is connected with the time delay calibrating installation with network performance tester respectively, sends various control signals by control link to them.Implementation step about the time delay calibration operation hereinafter also has detailed explanation.
The concrete composition structure of this time delay calibrating installation as shown in Figure 2.This device is comprised of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit.Wherein, time delay control unit is connection control unit, memory and ethernet interface circuit respectively, and control unit connects serial port circuit.In this time delay calibrating installation, serial port circuit as with the interface of control desk, be used for receiving the user who is installed in control desk and control the instruction that software sends; Ethernet interface circuit as with the interface of network performance tester, be used for receiving the Frame that network performance tester sends.In addition, the user controls the control signal that software sends and also arrives ethernet interface circuit through serial port circuit and control unit, so that the Control ethernet interface circuit is to the processing procedure of Frame.
Time delay control unit is one of core component of this time delay calibrating installation.This time delay control unit is comprised of cache module, time delay control module, package forward module and speed adjusting module.Wherein the time delay control module is connected between ethernet interface circuit and the cache module, is used for writing cache module from the Frame data that ethernet interface circuit receives, and starts the time delay timer.The package forward module is used for realizing the forwarding operation of relevant data frame, and the speed adjusting module is by reducing or the adaptive input in interval of increasing and next frame and the speed difference between the output.Above-mentioned time delay control module, package forward module and speed adjusting module can adopt existing application-specific integrated circuit (ASIC) to realize, also can realize by coding on FPGA (field programmable gate array) chip (content that specific implementation is introduced in can be with reference to Chinese invention patent ZL 200510011710.5 and ZL200510011711.X).Consider from aspects such as cost and upgrading conveniences, utilize fpga chip to realize that each above-mentioned functional module is more satisfactory selection.
Control unit also is one of core component of this time delay calibrating installation.This control unit can adopt universal cpu to realize, also can adopt single-chip microcomputer or DSP (digital signal processor) to realize.Serial port circuit can adopt based on the interface medium of RS485 serial bus standard and interface adapter spare and realize.Ethernet interface circuit is supported MDI, MDI-X auto negotiation, can utilize the multiple existing Ethernet chip such as RTL8029C, DM9000AE to realize.Memory can adopt SDRAM or FLASH to realize.These all are all very familiar routine techniquess of persons skilled in the art, just do not describe in detail at this.
In the prior art, the time delay that usually adopts software to realize can only reach the accuracy of Millisecond, and the stability that time delay adds under the condition of two-forty is also poor.For these technological deficiencies, this time delay calibrating installation has adopted hardware mode to join delay specially, namely controls the accurate adding that corresponding memory is realized time delay by FPGA.Below, describe the operation principle of this time delay calibrating installation in detail by Fig. 3 and two specific embodiments shown in Figure 4.
Embodiment shown in Figure 3 is a kind of time delay calibrating installation of the 10/100Base-T of being applicable to Ethernet.As shown in Figure 3, the control unit in this time delay calibrating installation adopts the universal cpu of SST company to realize.Ethernet interface circuit has two groups, respectively corresponding up, down direction.Corresponding time delay control unit also has two.These two time delay control unit realize by fpga chip, and they connect respectively two groups of ethernet interface circuits.Two time delay control unit are connected same memory by address bus with data/address bus.Herein cache module and memory integrate.CPU is connected with ethernet interface circuit with fpga chip by control bus, in order to finish the control to fpga chip, ethernet interface circuit.
In the embodiment shown in fig. 3, fpga chip adopts the product of ALTRA company.This fpga chip is connected with SDRAM as memory by 32 bit data bus and 12 bit address buses.In addition, this fpga chip also is connected with ethernet interface circuit by 8 bit data bus, and wherein 4 is Ethernet data receive data bus, and other 4 are Ethernet data transmission bus.
Embodiment shown in Figure 4 is a kind of time delay calibrating installation that is applicable to the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet.Control unit in this time delay calibrating installation also adopts the universal cpu of SST company to realize.Time delay control unit realizes by fpga chip, and they connect respectively two groups of ethernet interface circuits.Respectively corresponding up, the down direction of these two groups of ethernet interface circuits.CPU is connected with ethernet interface circuit with fpga chip by control bus, in order to finish the control to fpga chip, ethernet interface circuit.FPGA adopts the product of ALTRA company.This fpga chip is connected with SDRAM as memory by 30 bit data bus and 21 bit address buses.Cache module and memory in the time delay control unit integrate.In addition, this fpga chip is connected with ethernet interface circuit by 20 bit data bus, and wherein 10 is Ethernet data receive data bus, and other 10 are Ethernet data transmission bus.
In the embodiment shown in fig. 4, consider that the operating rate of interlock circuit in the gigabit Ethernet is very high.In order to ensure the speed of processing, each direction all adopts independent FPGA and memory when design.This is to distinguish with the time delay calibrating installation maximum in design of the above-mentioned 10/100Base-T of being applicable to Ethernet.
Time delay calibrating installation provided by the present invention is realized metering and calibration operation to the time delay of network performance tester parameter by add a stable time delay between two network interfaces.Below in conjunction with Fig. 5 and Fig. 6 the operation principle of this time delay calibrating installation is described in detail.
Fig. 5 has shown the basic procedure that time delay calibrating installation realization time delay adds.
At first, this time delay calibrating installation is after powering up, and control unit automatically performs initialize routine, and relevant register is set.And be ready to control with the user the mutual control of software.
Control the time delay settings that link direction (up, descending or two-way), interface type (10/100Base-T, 1000Base-T or 1000Base-SX/LX) and each direction that need to join delay are set in the software the user.
Control unit is converted to the time delay settings of receiving the count pulse of corresponding timer.
Time delay control module in the time delay control unit will write cache module from the Frame data that ethernet interface circuit is received, and start the time delay timer.
After the timing of time delay timer had arrived, the time delay control module read the corresponding data frame data from cache module, and sent to the ethernet interface circuit place.
Utilize time delay shown in Figure 5 to add flow process, can different time delay settings be set respectively independently at the both direction of link.When receiving or send Frame, export corresponding trigger impulse, can be used for packet counted with the time interval and test.
For the Frame data of reality, according to the requirement of Its Relevant Technology Standards, the scope of its clock frequency change is 100 * 10
-6In order to adapt to the excursion of clock frequency, be necessary that the speed of docking port is carried out adaptive.Ginseng is shown in Table 1, and carries out the adaptive concrete grammar of interface rate and mainly contains following three kinds:
| The implementation step | Advantage | Shortcoming | |
| Method 1 | The clock of delay process adopts the recovered clock that receives.Delay precision depends on recovered clock like this | The homology clock is simple | Delay precision is uncertain |
| Method 2 | The clock of delay process adopts the recovered clock that receives, but with local clock time-delay is calibrated, counted | Frame data stream structural change in the method 3 can not appear in the homology clock delay | Precision depends on recovered clock drift and shake |
| Method 3 | The divided clock territory, the clock of delay process adopts local clock | Delay precision is guaranteed by local clock | Design is complicated, and can change the structure of ethernet data stream |
Table 1
Through research, the present invention guarantees the accuracy that joins delay with above-mentioned method 3.Based on the method, this time delay calibrating installation has adopted interface rate as shown in Figure 6 to adjust flow process.This interface rate is adjusted flow process and is finished by the speed adjusting module in the time delay control unit, is used for the speed between adaptive ethernet interface circuit input and the output.
Interface rate shown in Figure 6 is adjusted being described in detail as follows of flow process:
At first, ethernet interface circuit is synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again;
The time delay timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module;
The speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
Add flow process and interface rate adjustment flow process based on above-mentioned time delay, just can carry out to network performance tester the measurement and calibration of delay parameter.The below introduces the implementation step of this time delay calibration operation:
(1) this time delay calibrating installation, the network performance tester that is calibrated are connected by mode shown in Figure 1.Wherein, according to the interface type of the network performance tester that is calibrated and the difference of configuration, can adopt different ethernet interface circuits to be connected to the time delay calibrating installation, make and set up man-to-man transmitting-receiving relation between each port of network performance tester that is calibrated;
(2) ethernet interface circuit speed (such as 10/100/1000Mbps) and the mode of operation (such as full-duplex/half-duplex) of the network performance tester be calibrated are set.The time delay calibrating installation adopts the interface of same configuration, to guarantee proper communication between the two.Start the delay testing function of the network performance tester that is calibrated;
(3) the time delay settings of time delay calibrating installation are set;
(4) the delay testing item parameter of the network performance tester that is calibrated of configuration, the frame length of test Ethernet data is made as respectively 64,128,256,512,1024,1280,1518 bytes;
(5) test rate of the network performance tester be calibrated is set;
(6) start the delay parameter test, test the Forwarding Delay between two interfaces.
(7) time delay value that the network performance tester test is obtained and the time delay settings of time delay calibrating installation setting compare, can see the accuracy of the time delay value that the network performance tester test obtains, realize the calibration to the time delay of network performance tester measured value of parameters.
The above has been described in detail time delay of network performance tester calibrating installation of the present invention, but obvious specific implementation form of the present invention is not limited to this.For the those skilled in the art of the art, in the situation that do not deviate from various apparent change that claim scope of the present invention carries out it all within protection scope of the present invention.
Claims (6)
1. time delay of network performance tester calibrating installation is used for the delay parameter of calibration network ability meter, it is characterized in that:
Described time delay of network performance tester calibrating installation is comprised of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit;
Described time delay control unit connects respectively described control unit, memory and ethernet interface circuit, described control unit connects described serial port circuit, described serial port circuit is used for connecting control desk, and described ethernet interface circuit is used for connecting described network performance tester;
Described time delay control unit is comprised of cache module, time delay control module, package forward module and speed adjusting module, described time delay control module is connected between described ethernet interface circuit and the described cache module, and described time delay control module, described package forward module and described speed adjusting module are realized by coding on the programmable gate array chip at the scene;
When joining delay, the time delay settings of link direction, interface type and each direction that need to join delay at first are set, then by described control unit the time delay settings of receiving are converted to the count pulse of time delay timer; Described time delay control module will write from the data that described ethernet interface circuit is received described cache module, and start described time delay timer; After the timing of described time delay timer arrived, described time delay control module read corresponding data from described cache module, and sends to described ethernet interface circuit place.
2. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described control unit is any one in CPU, single-chip microcomputer or the digital signal processor.
3. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described memory is any one among SDRAM or the FLASH.
4. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
In the situation that be operated in the 10/100Base-T Ethernet, two time delay control unit that correspond respectively to up direction and down direction share same memory.
5. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
In the situation that be operated in the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet, two time delay control unit that correspond respectively to up direction and down direction are used respectively independent memory.
6. a method of adjusting interface rate realizes based on time delay of network performance tester calibrating installation as claimed in claim 1, it is characterized in that:
(1) ethernet interface circuit is synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again;
(2) the time delay timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module;
(3) the speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
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| CN102957576A (en) * | 2011-08-30 | 2013-03-06 | 沈阳埃森诺通信设备有限公司 | Multifunctional network quality monitoring method and device |
| CN102307109B (en) * | 2011-08-31 | 2017-02-22 | 重庆中天重邮通信技术有限公司 | Signaling data acquisition single link time delay correction method |
| CN102647313B (en) * | 2012-05-14 | 2015-08-05 | 瑞斯康达科技发展股份有限公司 | A kind of network test system |
| CN107872365A (en) * | 2017-10-23 | 2018-04-03 | 上海斐讯数据通信技术有限公司 | A kind of Ethernet fourdrinier wire beats stream performance test methods and system |
| CN108833213B (en) * | 2018-08-08 | 2022-02-22 | 迈普通信技术股份有限公司 | Ethernet link detection method and device |
| CN109728978B (en) * | 2019-01-29 | 2023-04-07 | 中国航空无线电电子研究所 | AFDX (avionics full Duplex switched Ethernet) switch line speed control capability test method considering clock drift |
| CN115015976B (en) * | 2022-05-30 | 2022-12-20 | 中国计量科学研究院 | Bi-directional time delay calibration method for Beidou RDSS closed-loop test system |
| CN116455799A (en) * | 2023-04-28 | 2023-07-18 | 广东高云半导体科技股份有限公司 | Test equipment |
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| CN1595836A (en) * | 2004-06-30 | 2005-03-16 | 中兴通讯股份有限公司 | Method for implementing synchronization of outdoor unit and indoor unit of TD-SCDMA system |
| CN1753329A (en) * | 2005-10-28 | 2006-03-29 | 芯通科技（成都）有限公司 | Method of timing and timing calibration of base station radio frequency remoter and its use |
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| CN1595836A (en) * | 2004-06-30 | 2005-03-16 | 中兴通讯股份有限公司 | Method for implementing synchronization of outdoor unit and indoor unit of TD-SCDMA system |
| CN1753329A (en) * | 2005-10-28 | 2006-03-29 | 芯通科技（成都）有限公司 | Method of timing and timing calibration of base station radio frequency remoter and its use |
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