CN101304344A - Apparatus and method for calibrating time delay of network performance tester - Google Patents
Apparatus and method for calibrating time delay of network performance tester Download PDFInfo
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- CN101304344A CN101304344A CN 200810114264 CN200810114264A CN101304344A CN 101304344 A CN101304344 A CN 101304344A CN 200810114264 CN200810114264 CN 200810114264 CN 200810114264 A CN200810114264 A CN 200810114264A CN 101304344 A CN101304344 A CN 101304344A
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Abstract
The invention discloses a time delay calibration device for network performance testing instruments and also discloses a method for time delay parameter calibration by the time delay calibration device. The time delay calibration device comprises a serial interface, a control unit, a time delay control unit, a memory and an Ethernet interface circuit; wherein, the time delay control unit is connected with the control unit, the memory and the Ethernet interface circuit respectively, and the control unit is connected with the serial interface which is used for connecting a console. The Ethernet interface circuit is used for connecting the network performance testing instruments. The time delay calibration device controls the corresponding memory by FPGA to realize the addition of the time delay, and the accuracy of the time delay addition has no relation with the line rate. Meanwhile, the accuracy of the time delay addition is high, which can meet the time delay parameter measurement and calibration requirement of the most accurate network performance testing instruments at present.
Description
Technical field
The present invention relates to a kind of time delay of network performance tester calibrating installation and method thereof, relate in particular to and a kind ofly realize that by the relevant memory of FPGA control time delay of network performance tester calibrating installation and this time delay calibrating installation that time delay adds realize the delay parameter Calibration Method, belong to the communication field of measuring techniques.
Background technology
At present, the data communication network of China has obtained greatly developing, and has formed the nationwide network system.Data service shared proportion in whole communication service rises significantly.Particularly along with the development of next generation network technology, communication industry is to complete direction transition based on data communication network.Therefore, data communication network will play an increasingly important role as the basis of whole communication network.
In data communication network, network performance testing system is used to detect the specific performance index of the tested network or the network equipment, as throughput, delay, packet loss etc., be a kind of important means of estimating the performance of under the heterogeneous networks load tested network or the network equipment exactly.The whole network Performance Test System is made up of network test equipment and control desk two parts.Wherein, network test equipment is used to realize test port, finish the basic function of test, comprise the generation of measurement, route message of the generation of test traffic and reception, test statistics and message intercepting etc., in whole test process, bringing into play indispensable important function.Control desk is generally realized by PC, is used to provide User Interface, comprises the analysis of setting, test result of test parameter and demonstration etc.
Network test equipment is divided according to function, can be divided into two big classes.The first kind is a protocol analyzer, is used to realize the analysis to Code And Decode, traffic statistics and the carrying content of ICP/IP protocol, IP routing protocol, ATM agreement.The protocol analyzer of part also possesses the function of emulation ICP/IP protocol, IP routing protocol and ATM agreement.Second class is a network performance tester, is used to realize the test to data forwarded performance.Main test event is four parameters of network performance, i.e. the throughput of data network (Throughput), time delay (Latency), frame loss rate (FrameLoss Rate) and back-to-back performance (Back to Back).
In four parameters of above-mentioned network performance, time delay comprises packet queuing delay, propagation delay time, forwarding time delay, is the important indicator that influences user's perception.Therefore, delay parameter is an important parameter that needs carry out measuring fixed amount, calibration.But the accuracy of measuring at delay parameter lacks unified standard at present.From the performance index that each network performance tester producer provides, the diverse network ability meter differs bigger for the accuracy of measurement of delay parameter.The resolution of the network performance tester that has can reach the microsecond level, and the network performance tester that has can only reach Millisecond.The network performance tester that has is higher to the accuracy of latency measurement when speed is low on the line, but the measurement to delay parameter is not very accurate just under the line speed condition with higher.This has just made obstacle for service quality objective, that estimate relevant telecommunication service operator exactly.
Summary of the invention
At the existing in prior technology deficiency, primary and foremost purpose of the present invention provides a kind of time delay of network performance tester calibrating installation (being called for short the time delay calibrating installation).This time delay calibrating installation can be under the situation of different rates, different test frame lengths the calibration network ability meter measure the accuracy of delay parameter.
Another object of the present invention provides the concrete grammar that utilizes above-mentioned time delay of network performance tester calibrating installation calibration delay parameter.
For realizing above-mentioned goal of the invention, the present invention adopts following technical scheme:
A kind of time delay of network performance tester calibrating installation is used for the delay parameter of calibration network ability meter, it is characterized in that:
Described time delay of network performance tester calibrating installation is made up of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit;
Described time delay control unit connects described control unit, memory and ethernet interface circuit respectively, and described control unit connects described serial port circuit;
Described serial port circuit is used to connect control desk, and described ethernet interface circuit is used to connect described network performance tester.
Wherein, described time delay control unit is made up of cache module, time delay control module, packet forwarding module and speed adjusting module, described time delay control module is connected between described ethernet interface circuit and the described cache module, is used for the data that described ethernet interface circuit place receives are write described cache module.
Described time delay control module, packet forwarding module and speed adjusting module are realized by coding on the programmable gate array chip at the scene.
Described control unit is any one in CPU, single-chip microcomputer or the digital signal processor.
Described memory is any one among SDRAM or the FLASH.
Under the situation that is operated in the 10/100Base-T Ethernet, correspond respectively to the shared same memory of two time delay control unit of up direction and down direction.
Under the situation that is operated in the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet, two time delay control unit that correspond respectively to up direction and down direction are used independent memory respectively.
When needs join delay, time delay value of setting of link direction, interface type and each direction that need join delay at first is set, by control unit time delay value of setting of receiving is converted to the count pulse of timer then; Time delay control module in the time delay control unit will write cache module from the Frame data that ethernet interface circuit is received, and start the time delay timer; After the timing of time delay timer had arrived, the time delay control module read the corresponding data frame data from cache module, and sent to the ethernet interface circuit place.
When needs were adjusted interface rate, ethernet interface circuit was synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again; Timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module; The speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
Compared with prior art, time delay calibrating installation provided by the present invention adopts hardware mode to join delay, and promptly realizes the adding of time delay by FPGA control corresponding memory.This mode has following advantage:
1. the accuracy of time delay adding and line speed are irrelevant, and the data that promptly no matter enter the time delay calibrating installation are that very low speed or wire rate (maximum rate that can reach in theory) can both accurately be realized the Frame that enters is added stable setting time delay;
2. the accuracy of time delay adding is very high.Relevant test proof, the expanded uncertainty that uses this time delay calibrating installation to join delay is (the 0.2+ time delay value of setting * 10
-6) microsecond, therefore spreading factor k=2 can satisfy at present the delay parameter measurement and calibration requirement of accurate network performance tester.
Description of drawings
The invention will be further described below in conjunction with accompanying drawing:
Fig. 1 is the working state schematic representation of time delay of network performance tester calibrating installation provided by the present invention;
Fig. 2 is the overall structure block diagram of time delay calibrating installation shown in Figure 1;
Fig. 3 is the embodiment schematic diagram that is applicable to the time delay calibrating installation of 10/100Base-T Ethernet;
Fig. 4 is the embodiment schematic diagram that is applicable to the time delay calibrating installation of 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet;
Fig. 5 is that this time delay calibrating installation is realized the schematic flow sheet that time delay adds;
Fig. 6 is that this time delay calibrating installation is realized the schematic flow sheet that interface rate is adjusted.
Embodiment
Referring to shown in Figure 1, time delay calibrating installation provided by the present invention is connected with control desk with network performance tester respectively when carrying out the time delay calibration operation.The ethernet data frame (including but not limited to the Frame of Ethernet II, IEEE802.3 form) that network performance tester will be tested usefulness sends to the time delay calibrating installation from a port, and the test that the time delay calibrating installation will be received is carried out giving network performance tester by the loopback of another one port after the time delay processing with ethernet data frame.Compare the time delay of time delay calibrating installation adding and the time delay that network performance tester measures then.The result who utilizes the value calibration network performance tester of time delay calibrating installation to measure.Control desk is realized by PC.This control desk is connected with the time delay calibrating installation with network performance tester respectively, and they send various control signalings by the Quality Initiative road direction.Concrete implementation step about the time delay calibration operation hereinafter also has detailed explanation.
The concrete composition structure of this time delay calibrating installation as shown in Figure 2.This device is made up of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit.Wherein, time delay control unit connects control unit, memory and ethernet interface circuit respectively, and control unit connects serial port circuit.In this time delay calibrating installation, serial port circuit as with the interface of control desk, be used for receiving the instruction that user's Control Software of being installed in control desk is sent; Ethernet interface circuit as with the interface of network performance tester, be used to receive the Frame that network performance tester sends.In addition, the control signaling that user's Control Software is sent also arrives ethernet interface circuit through serial port circuit and control unit, so that the control ethernet interface circuit is to the processing procedure of Frame.
Time delay control unit is one of core component of this time delay calibrating installation.This time delay control unit is made up of cache module, time delay control module, packet forwarding module and speed adjusting module.Wherein the time delay control module is connected between ethernet interface circuit and the cache module, and the Frame data that are used for receiving from ethernet interface circuit write cache module, and starts the time delay timer.The packet forwarding module is used to realize the forwarding operation of relevant data frame, and the speed adjusting module is by reducing or the adaptive input in interval of increasing and next frame and the speed difference between the output.Above-mentioned time delay control module, packet forwarding module and speed adjusting module can adopt existing application-specific integrated circuit (ASIC) to realize, also can realize that (specific implementation can be with reference to Chinese invention patent ZL 200510011710.5 and ZL by coding on FPGA (field programmable gate array) chip
200510011711.X the content of middle introduction).Consider from aspects such as cost and upgrading conveniences, utilize fpga chip to realize that each above-mentioned functional module is more satisfactory selection.
Control unit also is one of core component of this time delay calibrating installation.This control unit can adopt universal cpu to realize, also can adopt single-chip microcomputer or DSP (digital signal processor) to realize.Serial port circuit can adopt based on the interface medium of RS485 serial bus standard and interface adapter spare and realize.Ethernet interface circuit supports that MDI, MDI-X consult automatically, can utilize multiple existing Ethernet interface chip such as RTL8029C, DM9000AE to realize.Memory can adopt SDRAM or FLASH to realize.These all are all very familiar routine techniquess of persons skilled in the art, just do not describe in detail at this.
In the prior art, the time delay that adopts software to realize usually can only reach the accuracy of Millisecond, and the stability that time delay adds under the condition of two-forty is also poor.At these technological deficiencies, this time delay calibrating installation has adopted hardware mode to join delay specially, promptly realizes the accurate adding of time delay by FPGA control corresponding memory.Below, describe the operation principle of this time delay calibrating installation in detail by Fig. 3 and two specific embodiments shown in Figure 4.
Embodiment shown in Figure 3 is a kind of time delay calibrating installation of the 10/100Base-T of being applicable to Ethernet.As shown in Figure 3, the control unit in this time delay calibrating installation adopts the universal cpu of SST company to realize.Ethernet interface circuit has two groups, respectively corresponding up, down direction.Corresponding time delay control unit also has two.These two time delay control unit realize that by fpga chip they connect two groups of ethernet interface circuits respectively.Two time delay control unit are connected same memory by address bus with data/address bus.Herein cache module and memory integrate.CPU is connected with ethernet interface circuit with fpga chip by control bus, so that finish the control to fpga chip, ethernet interface circuit.
In the embodiment shown in fig. 3, fpga chip adopts the product of ALTRA company.This fpga chip is connected with SDRAM as memory by 32 bit data bus and 12 bit address buses.In addition, this fpga chip also is connected with ethernet interface circuit by 8 bit data bus, and wherein 4 are Ethernet data reception data/address bus, and other 4 is that Ethernet data sends bus.
Embodiment shown in Figure 4 is a kind of time delay calibrating installation that is applicable to the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet.Control unit in this time delay calibrating installation also adopts the universal cpu of SST company to realize.Time delay control unit realizes that by fpga chip they connect two groups of ethernet interface circuits respectively.Respectively corresponding up, the down direction of these two groups of ethernet interface circuits.CPU is connected with ethernet interface circuit with fpga chip by control bus, so that finish the control to fpga chip, ethernet interface circuit.FPGA adopts the product of ALTRA company.This fpga chip is connected with SDRAM as memory by 30 bit data bus and 21 bit address buses.Cache module and memory in the time delay control unit integrate.In addition, this fpga chip is connected with ethernet interface circuit by 20 bit data bus, and wherein 10 are Ethernet data reception data/address bus, and other 10 is that Ethernet data sends bus.
In the embodiment shown in fig. 4, consider that the operating rate of interlock circuit in the gigabit Ethernet is very high.In order to ensure the speed of handling, each direction all adopts independent FPGA and memory when design.This is to distinguish with the time delay calibrating installation maximum in design of the above-mentioned 10/100Base-T of being applicable to Ethernet.
Time delay calibrating installation provided by the present invention is realized metering and calibration operation to the time delay of network performance tester parameter by add a stable time delay between two network interfaces.Below in conjunction with Fig. 5 and Fig. 6 the operation principle of this time delay calibrating installation is described in detail.
Fig. 5 has shown the basic procedure that time delay calibrating installation realization time delay adds.
At first, this time delay calibrating installation is after powering up, and control unit automatically performs initialize routine, and relevant register is set.And be ready to mutual control with user's Control Software.
Time delay value of setting of link direction (up, descending or two-way), interface type (10/100Base-T, 1000Base-T or 1000Base-SX/LX) and each direction that need join delay is set in user's Control Software.
Control unit is converted to time delay value of setting of receiving the count pulse of corresponding timer.
Time delay control module in the time delay control unit will write cache module from the Frame data that ethernet interface circuit is received, and start the time delay timer.
After the timing of time delay timer had arrived, the time delay control module read the corresponding data frame data from cache module, and sent to the ethernet interface circuit place.
Utilize time delay shown in Figure 5 to add flow process, can different time delay values of setting be set independently respectively at the both direction of link.When receiving or send Frame, output relative trigger pulse can be used for packet counted with the time interval and tests.
For the Frame data of reality, according to the requirement of correlation technique standard, the scope of its clock frequency change is 100 * 10
-6In order to adapt to the excursion of clock frequency, be necessary that the speed of docking port is carried out adaptive.Ginseng is shown in Table 1, and carries out the adaptive concrete grammar of interface rate and mainly contains following three kinds:
| Concrete implementation step | Advantage | Shortcoming | |
| Method 1 | The clock of delay process adopts the recovered clock that receives.Delay precision depends on recovered clock like this | The homology clock is simple | Delay precision is uncertain |
| Method 2 | The clock of delay process adopts the recovered clock that receives, but with local clock time-delay is calibrated, counted | Frame data stream structural change in the method 3 can not appear in the homology clock delay | Precision depends on recovered clock drift and shake |
| Method 3 | The divided clock territory, the clock of delay process adopts local clock | Delay precision is guaranteed by local clock | Design is complicated, and can change the structure of ethernet data stream |
Table 1
Through research, the present invention uses above-mentioned method 3 to guarantee the accuracy that joins delay.Based on this method, this time delay calibrating installation has adopted interface rate as shown in Figure 6 to adjust flow process.This interface rate is adjusted flow process and is finished by the speed adjusting module in the time delay control unit, is used for the speed between adaptive ethernet interface circuit input and the output.
Interface rate shown in Figure 6 is adjusted being described in detail as follows of flow process:
At first, ethernet interface circuit is synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again;
The time delay timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module;
The speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
Add flow process and interface rate adjustment flow process based on above-mentioned time delay, just can carry out the measurement and calibration of delay parameter network performance tester.Introduce the concrete implementation step of this time delay calibration operation below:
(1) this time delay calibrating installation, the network performance tester that is calibrated are connected by mode shown in Figure 1.Wherein,, can adopt different ethernet interface circuits to be connected to the time delay calibrating installation, make and set up man-to-man transmitting-receiving relation between each port of network performance tester that is calibrated according to the interface type of the network performance tester that is calibrated and the difference of configuration;
(2) the ethernet interface circuit speed (as 10/100/1000Mbps) and the mode of operation (as full-duplex/half-duplex) of the network performance tester be calibrated are set.The time delay calibrating installation adopts the interface of same configuration, to guarantee proper communication between the two.Start the delay testing function of the network performance tester that is calibrated;
(3) time delay value of setting of time delay calibrating installation is set;
(4) the delay testing item parameter of the network performance tester that is calibrated of configuration, the frame length of test Ethernet data is made as 64,128,256,512,1024,1280,1518 bytes respectively;
(5) test rate of the network performance tester be calibrated is set;
(6) start the delay parameter test, test the forwarding time delay between two interfaces.
(7) time delay value that the network performance tester test is obtained and time delay value of setting of time delay calibrating installation setting compare, can see the accuracy of the time delay value that the network performance tester test obtains, realize calibration the time delay of network performance tester measured value of parameters.
Above time delay of network performance tester calibrating installation of the present invention is had been described in detail, but obvious specific implementation form of the present invention is not limited thereto.For the those skilled in the art in present technique field, the various conspicuous change of under the situation that does not deviate from claim scope of the present invention it being carried out is all within protection scope of the present invention.
Claims (9)
1. time delay of network performance tester calibrating installation is used for the delay parameter of calibration network ability meter, it is characterized in that:
Described time delay of network performance tester calibrating installation is made up of serial port circuit, control unit, time delay control unit, memory and ethernet interface circuit;
Described time delay control unit connects described control unit, memory and ethernet interface circuit respectively, and described control unit connects described serial port circuit;
Described serial port circuit is used to connect control desk, and described ethernet interface circuit is used to connect described network performance tester.
2. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described time delay control unit is made up of cache module, time delay control module, packet forwarding module and speed adjusting module, described time delay control module is connected between described ethernet interface circuit and the described cache module, is used for the data that described ethernet interface circuit place receives are write described cache module.
3. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described time delay control module, packet forwarding module and speed adjusting module are realized by coding on the programmable gate array chip at the scene.
4. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described control unit is any one in CPU, single-chip microcomputer or the digital signal processor.
5. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Described memory is any one among SDRAM or the FLASH.
6. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Under the situation that is operated in the 10/100Base-T Ethernet, correspond respectively to the shared same memory of two time delay control unit of up direction and down direction.
7. time delay of network performance tester calibrating installation as claimed in claim 1 is characterized in that:
Under the situation that is operated in the 1000Base-T/1000Base-LX/1000Base-SX gigabit Ethernet, two time delay control unit that correspond respectively to up direction and down direction are used independent memory respectively.
8. a method that realizes that time delay adds realizes based on time delay of network performance tester calibrating installation as claimed in claim 1, it is characterized in that:
(1) time delay value of setting of link direction, interface type and each direction that need join delay is set, by control unit time delay value of setting of receiving is converted to the count pulse of timer then;
(2) the time delay control module in the time delay control unit will write cache module from the Frame data that ethernet interface circuit is received, and start the time delay timer;
(3) after the timing of time delay timer has arrived, the time delay control module reads the corresponding data frame data from cache module, and sends to the ethernet interface circuit place.
9. a method of adjusting interface rate realizes based on time delay of network performance tester calibrating installation as claimed in claim 1, it is characterized in that:
(1) ethernet interface circuit is synchronized with the clock that receives ethernet data frame, and the ethernet data frame that receives is sent in the time delay control module, and the time delay control module writes data in the cache module again;
(2) timer then after, the time delay control module reads data in the cache module with the local clock frequency, and judges the storage condition of cache module;
(3) the speed adjusting module is by reducing or the adaptive input interface in interval of increasing and next frame and the speed difference between the output interface.
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| CN115015976A (en) * | 2022-05-30 | 2022-09-06 | 中国计量科学研究院 | Bi-directional time delay calibration method for Beidou RDSS closed-loop test system |
| CN115015976B (en) * | 2022-05-30 | 2022-12-20 | 中国计量科学研究院 | Bi-directional time delay calibration method for Beidou RDSS closed-loop test system |
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