CN116455799A - Test equipment - Google Patents
Test equipment Download PDFInfo
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- CN116455799A CN116455799A CN202310496554.4A CN202310496554A CN116455799A CN 116455799 A CN116455799 A CN 116455799A CN 202310496554 A CN202310496554 A CN 202310496554A CN 116455799 A CN116455799 A CN 116455799A
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- 238000012360 testing method Methods 0.000 title claims abstract description 51
- 239000000872 buffer Substances 0.000 claims description 58
- 101100283411 Arabidopsis thaliana GMII gene Proteins 0.000 claims description 3
- 238000010276 construction Methods 0.000 abstract description 5
- 230000005540 biological transmission Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
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- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The application discloses test equipment, the test equipment is connected in series to an Ethernet network through a first Ethernet interface and a second Ethernet interface, so that Ethernet data from the Ethernet equipment enter the test equipment through the first Ethernet interface/the second Ethernet interface and are output from the second Ethernet interface/the first Ethernet interface after network delay is increased, dynamic adjustment of delay parameters is realized, and construction of corresponding test environments is simplified.
Description
Technical Field
The present application relates to, but is not limited to, ethernet testing technology, and more particularly to a testing device.
Background
In ethernet networks, some application scenarios require clock synchronization, i.e. the time of each device in the network must be synchronized to a master clock, like protocols such as IEEE1588, network time protocol (NTP, network Time Protocol). The NTP protocol compensates for network latency to synchronize clocks of various devices in the network to the master clock.
In testing the above protocols, different network delays need to be tested in order to simulate the actual network environment. How to simulate network delay in a laboratory for testing is the basis for ensuring the success of the test. How to simulate ethernet line delay in a laboratory is a problem that needs to be solved.
Disclosure of Invention
The application provides test equipment, which can dynamically adjust delay parameters and simplify the construction of corresponding test environments.
The embodiment of the invention provides test equipment, which comprises the following components: the system comprises a processing chip, a first Ethernet physical layer PHY chip and a second Ethernet PHY chip; wherein,,
the processing chip is connected with the first Ethernet PHY chip and the second Ethernet PHY chip and is used for forwarding the Ethernet data from the first Ethernet port and/or the second Ethernet port, and configuration information is acquired through a configuration interface of external electronic equipment so as to control the delay of the Ethernet data;
and connecting test equipment in series to an Ethernet network through the first Ethernet interface and the second Ethernet interface, wherein Ethernet data from the Ethernet network enters the processing chip from the first Ethernet interface through the first Ethernet PHY chip and is output from the second Ethernet interface through the second Ethernet PHY chip, or enters the processing chip from the second Ethernet interface through the second Ethernet PHY chip and is output from the first Ethernet interface through the first Ethernet PHY chip.
In one illustrative example, the processing chip is implemented with a field programmable gate array FPGA.
In one illustrative example, the processing chip includes: the device comprises a first receiving module, a first sending module, a second receiving module, a second sending module, a first buffer, a second buffer and a configuration module; wherein,,
the first receiving module is configured to receive ethernet data from the first ethernet PHY chip, splice the received ethernet data into parallel data, and write the parallel data into the first buffer;
the second receiving module is configured to receive ethernet data from the second ethernet PHY chip, splice the received ethernet data into parallel data, and write the parallel data into the second buffer;
the first sending module is configured to detect that the data amount stored in the first buffer is greater than or equal to a preset buffer reading threshold, read the data in the first buffer, convert the read data into an interface form of the first ethernet PHY chip, and send the data to the first ethernet PHY chip;
the second sending module is configured to detect that the data amount stored in the second buffer is greater than or equal to a preset buffer reading threshold, read the data in the second buffer, convert the read data into an interface form of the second ethernet PHY chip, and send the data to the second ethernet PHY chip;
the configuration module is configured to receive configuration information from the external electronic device via the configuration interface, and set a buffer reading threshold of the first buffer/the second buffer according to the obtained configuration information.
In one illustrative example, the interface of the first ethernet PHY chip/the second ethernet PHY chip includes: media independent interface MII, or gigabit MII interface GMII, or reduced MII interface RGMII.
In an exemplary embodiment, the first buffer is a first-in first-out memory; the second buffer is a second first-in first-out memory.
In one illustrative example, the configuration interface is a universal asynchronous receiver transmitter UART interface.
In an exemplary embodiment, the configuration module is a UART module, and is connected to the UART interface.
In an exemplary embodiment, the step delay duration of the buffer read threshold is a clock cycle of reading the first buffer/the second buffer;
the time delay time length is the time length for delaying the Ethernet data.
In an exemplary embodiment, the relationship between the buffer reading threshold and the delay time length is: delay time = buffer read threshold x step delay time.
In one illustrative example, the step delay time is 8 nanoseconds ns.
According to the test equipment provided by the embodiment of the application, the test equipment is connected in series to the Ethernet through the first Ethernet interface and the second Ethernet interface, so that Ethernet data from the Ethernet equipment enters the test equipment through the first Ethernet interface/the second Ethernet interface and is output from the second Ethernet interface/the first Ethernet interface after network delay is increased, dynamic adjustment of delay parameters is realized, and construction of a corresponding test environment is simplified.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a schematic diagram of a test apparatus according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the composition and structure of a processing chip in a test apparatus according to an embodiment of the present application;
fig. 3 is a schematic view of a scenario in which a test device according to an embodiment of the present application is applied to an ethernet network.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.
In the laboratory, the delay of the line can be increased, typically by forwarding the device (e.g. switch) through a serial network. However, each network forwarding device may have a limited delay that may be added, and if more delay is desired, more network forwarding devices may need to be connected in series. That is, the method of increasing the delay of the line by the tandem network forwarding device in the related art cannot simulate the network environment of long-distance transmission with high delay. Furthermore, if a tester wants to change the network delay, the connection mode of the network forwarding device needs to be changed, which causes complexity in building a corresponding test environment.
In order to realize the simulation of the delay of an Ethernet line in a laboratory, a tester can simply build a network environment for long-distance transmission and conveniently and rapidly modify delay parameters, the application provides test equipment which is based on a Field programmable gate array (FPGA, field-Programmable Gate Array), can dynamically adjust the delay parameters, can simulate the network environment for long-distance transmission with high delay, realizes the configurable delay of the Ethernet, and can simplify the building of corresponding test environments when the network delay is required to be changed.
Fig. 1 is a schematic diagram of a composition structure of a test device in an embodiment of the present application, where, as shown in fig. 1, the test device is provided with a first ethernet interface, a second ethernet interface, and a configuration interface; the test apparatus includes: a processing chip, a first ethernet physical layer (PHY) chip, a second ethernet PHY chip, wherein,
the processing chip is connected with the first Ethernet PHY chip and the second Ethernet PHY chip and is used for forwarding the Ethernet data from the first Ethernet port and/or the second Ethernet port, and acquiring configuration information through a configuration interface of external electronic equipment so as to control the delay of the Ethernet data;
the test device is connected in series to the ethernet network through the first ethernet interface and the second ethernet interface, and ethernet data from the ethernet network may enter the processing chip from the first ethernet interface via the first ethernet PHY chip and be output from the second ethernet interface via the second ethernet PHY chip, or may enter the processing chip from the second ethernet interface via the second ethernet PHY chip and be output from the first ethernet interface via the first ethernet PHY chip.
According to the test equipment provided by the embodiment of the application, the test equipment is connected in series to the Ethernet through the first Ethernet interface and the second Ethernet interface, so that Ethernet data from the Ethernet equipment enters the test equipment through the first Ethernet interface/the second Ethernet interface and is output from the second Ethernet interface/the first Ethernet interface after network delay is increased, dynamic adjustment of delay parameters is realized, and construction of a corresponding test environment is simplified.
In one illustrative example, the configuration interface may be a universal asynchronous receiver Transmitter (UART, universal Asynchronous Receiver/Transmitter) interface. The UART interface can be connected with electronic equipment, such as a mobile phone, a computer and the like, configuration information is input through a preset page on the electronic equipment, the configuration information is sent to the processing chip through a URAT interface sending instruction, and the processing chip can adjust delay parameters of the test equipment according to the configuration information so as to control data delay, thereby realizing the function of configurable line delay.
In one illustrative example, the processing chip may be implemented using an FPGA. In one embodiment, as shown in FIG. 2, a processing chip implemented based on an FPGA may include: the device comprises a first receiving module, a first sending module, a second receiving module, a second sending module, a first buffer, a second buffer and a configuration module; wherein,,
the first receiving module is used for receiving the Ethernet data from the first Ethernet PHY chip, splicing the received Ethernet data into parallel data and writing the parallel data into the first buffer;
the second receiving module is used for receiving the Ethernet data from the second Ethernet PHY chip, splicing the received Ethernet data into parallel data and writing the parallel data into the second buffer;
the first sending module is used for detecting that the data quantity stored in the first buffer is greater than or equal to a preset buffer reading threshold value, reading the data in the first buffer, converting the read data into an interface form of the first Ethernet PHY chip and sending the read data to the first Ethernet PHY chip;
the second sending module is used for detecting that the data quantity stored in the second buffer is greater than or equal to a preset buffer reading threshold value, reading the data in the second buffer, converting the read data into an interface form of a second Ethernet PHY chip and sending the read data to the second Ethernet PHY chip;
the configuration module is used for receiving configuration information from the external electronic equipment through the configuration interface and setting a buffer reading threshold of the first buffer/the second buffer according to the obtained configuration information.
In one illustrative example, the interface of the first ethernet PHY chip/the second ethernet PHY chip may be, but is not limited to, as: media independent interfaces (MII, media Independent interface), gigabit MII interfaces (GMII, gigabit Media Independant Interface), reduced MII interfaces (RGMII, reduced Media Independant Interface).
In one illustrative example, the first buffer may be a first-in first-out memory (FIFO 1). The second buffer may be a second first-in first-out memory (FIFO 2).
In an exemplary embodiment, the configuration module may be a UART module, connected to a UART interface, and configured to receive serial data sent from an electronic device connected to the UART interface, such as a mobile phone, a computer, etc., and parse the serial data to obtain configuration information, and set a buffer reading threshold of the first buffer/the second buffer according to the configuration information. The circuit delay configurable function is realized through the configuration module.
In one embodiment, the step delay time of the buffer read threshold is the clock period of the read first buffer/second buffer, e.g., 8ns. The delay time is the time for delaying the Ethernet data, and the stepping delay time is the adjustment quantity of the primary delay time. In one embodiment, the relationship between the cache read threshold and the delay time is: delay time = cache read threshold x step delay time, in one embodiment the step delay time may be 8 nanoseconds (ns).
Fig. 3 is a schematic view of a scenario in which a test device in the embodiment of the present application is applied in an ethernet network, as shown in fig. 3, where the test device is connected in series between ethernet device 1 and ethernet device 2 through a first ethernet interface and a second ethernet interface, and meanwhile, the test device is connected to an electronic device through a configuration interface, so as to obtain configuration information from the electronic device, and perform delay control on ethernet data passing through the test device. By the test equipment provided by the embodiment of the application, the construction of the corresponding test environment is simplified, and the delay parameter is dynamically adjusted.
Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims appended hereto.
Claims (10)
1. A test apparatus, comprising: the system comprises a processing chip, a first Ethernet physical layer PHY chip and a second Ethernet PHY chip; wherein,,
the processing chip is connected with the first Ethernet PHY chip and the second Ethernet PHY chip and is used for forwarding the Ethernet data from the first Ethernet port and/or the second Ethernet port, and configuration information is acquired through a configuration interface of external electronic equipment so as to control the delay of the Ethernet data;
and connecting test equipment in series to an Ethernet network through the first Ethernet interface and the second Ethernet interface, wherein Ethernet data from the Ethernet network enters the processing chip from the first Ethernet interface through the first Ethernet PHY chip and is output from the second Ethernet interface through the second Ethernet PHY chip, or enters the processing chip from the second Ethernet interface through the second Ethernet PHY chip and is output from the first Ethernet interface through the first Ethernet PHY chip.
2. The test device of claim 1, wherein the processing chip is implemented with a field programmable gate array FPGA.
3. The test apparatus of claim 2, wherein the processing chip comprises: the device comprises a first receiving module, a first sending module, a second receiving module, a second sending module, a first buffer, a second buffer and a configuration module; wherein,,
the first receiving module is configured to receive ethernet data from the first ethernet PHY chip, splice the received ethernet data into parallel data, and write the parallel data into the first buffer;
the second receiving module is configured to receive ethernet data from the second ethernet PHY chip, splice the received ethernet data into parallel data, and write the parallel data into the second buffer;
the first sending module is configured to detect that the data amount stored in the first buffer is greater than or equal to a preset buffer reading threshold, read the data in the first buffer, convert the read data into an interface form of the first ethernet PHY chip, and send the data to the first ethernet PHY chip;
the second sending module is configured to detect that the data amount stored in the second buffer is greater than or equal to a preset buffer reading threshold, read the data in the second buffer, convert the read data into an interface form of the second ethernet PHY chip, and send the data to the second ethernet PHY chip;
the configuration module is configured to receive configuration information from the external electronic device via the configuration interface, and set a buffer reading threshold of the first buffer/the second buffer according to the obtained configuration information.
4. The test device of claim 2, wherein the first ethernet PHY chip/second ethernet PHY chip interface comprises: media independent interface MII, or gigabit MII interface GMII, or reduced MII interface RGMII.
5. The test apparatus of claim 2, wherein the first buffer is a first-in first-out memory; the second buffer is a second first-in first-out memory.
6. The test device of claim 2, wherein the configuration interface is a universal asynchronous receiver transmitter UART interface.
7. The test device of claim 6, wherein the configuration module is a UART module coupled to the UART interface.
8. The test device of claim 3, wherein the step delay duration of the cache read threshold is a clock cycle of reading the first/second buffers;
the time delay time length is the time length for delaying the Ethernet data.
9. The test device of claim 8, wherein the cache read threshold is related to the delay time length by: delay time = buffer read threshold x step delay time.
10. The test apparatus of claim 9, wherein the step delay time duration is 8 nanoseconds ns.
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| CN202310496554.4A CN116455799B (en) | 2023-04-28 | 2023-04-28 | Test equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118138506A (en) * | 2024-04-30 | 2024-06-04 | 广州赛宝计量检测中心服务有限公司 | Calibration device and method for data network tester |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304344A (en) * | 2008-06-02 | 2008-11-12 | 信息产业部通信计量中心 | Apparatus and method for calibrating time delay of network performance tester |
| CN102811110A (en) * | 2011-06-01 | 2012-12-05 | 中兴通讯股份有限公司 | Transmission delay control method and transmission delay control system |
| US20200169489A1 (en) * | 2015-05-06 | 2020-05-28 | Marvell Asia Pte., Ltd. | Securing and controlling remote access of a memory-mapped device utilizing an ethernet interface and test port of a network device |
| US20220374371A1 (en) * | 2019-12-06 | 2022-11-24 | Suzhou Centec Communications Co., Ltd. | Verification System and Verification Method for Ethernet Interface Chip |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101304344A (en) * | 2008-06-02 | 2008-11-12 | 信息产业部通信计量中心 | Apparatus and method for calibrating time delay of network performance tester |
| CN102811110A (en) * | 2011-06-01 | 2012-12-05 | 中兴通讯股份有限公司 | Transmission delay control method and transmission delay control system |
| US20200169489A1 (en) * | 2015-05-06 | 2020-05-28 | Marvell Asia Pte., Ltd. | Securing and controlling remote access of a memory-mapped device utilizing an ethernet interface and test port of a network device |
| US20220374371A1 (en) * | 2019-12-06 | 2022-11-24 | Suzhou Centec Communications Co., Ltd. | Verification System and Verification Method for Ethernet Interface Chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118138506A (en) * | 2024-04-30 | 2024-06-04 | 广州赛宝计量检测中心服务有限公司 | Calibration device and method for data network tester |
| CN118138506B (en) * | 2024-04-30 | 2024-07-02 | 广州赛宝计量检测中心服务有限公司 | Calibration device and method for data network tester |
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