CN104597802B - A kind of reproducible data collecting system of superelevation sample rate - Google Patents

Abstract

The invention provides a reproducible data acquisition system with an ultra-high sampling rate. The system includes an ADC analog-to-digital conversion chip, an embedded CPU, an FPGA processing unit, and a data memory. The DCM unit of the FPGA generates n phases with a difference of 2π/n The clock signal of different phases is given to the ADC for each data acquisition to realize data acquisition of different phases. Finally, the data acquisition results of different phases are combined in the FPGA to form a high sampling rate data of n times the ADC sampling rate. Collect results. Among them, the data acquisition of each phase is collected repeatedly for filtering processing, which can eliminate noise and further improve the performance of the data acquisition system. The system implements a low-rate analog-to-digital conversion chip for high-sampling-rate data acquisition. The control of the system is simple, and the computing power of the FPGA is low. It is easy to implement, and the accuracy of the collected data is high.

Description

A Reproducible Data Acquisition System with Ultra High Sampling Rate

technical field

The invention relates to a data acquisition system, in particular to an ultra-high sampling rate reproducible data acquisition system.

Background technique

The rapid development of modern electronic technology has continuously improved the performance of embedded processors. For example, the performance of the current ARM series embedded processors is no less than that of PC processors two or three years ago. These high-speed embedded processors have derived more and more embedded high-speed data processing systems. However, the performance improvement of analog-to-digital conversion chips that sample and quantize data lags far behind the speed of processor performance improvement. Therefore, how to achieve high-speed, accurate, and large-scale data acquisition has become the key and bottleneck of modern embedded data processing systems.

The data acquisition unit usually uses an analog-to-digital conversion chip (ADC) to sample and quantify the analog signal and convert it into a digital model for collection, and its sampling speed, that is, the sampling rate, is limited by the sampling rate parameter of the analog-to-digital conversion chip. In order to achieve ultra-high-speed data acquisition, the usual practice is to use multiple analog-to-digital conversion chips to form an AD conversion array, each conversion chip is connected to a sampling clock of different phases, and then FPGA is used to combine the sampling results of different phases to synthesize A high sampling rate sampling result, such as the method in the Chinese utility model patent with the patent number CN202033737U, is to use two A/D converters with a sampling rate of 125MSPS to alternately sample one signal in parallel to achieve a sampling rate of 250MSPS. However, this method of phase-separated acquisition with multiple AD conversion chips requires multiple AD chips and more FPGA pins, which is costly and likely to cause insufficient FPGA resources. In addition, from the performance point of view, the multi-block AD chip data acquisition system will also cause certain amplitude and DC bias differences between different phases due to some parameter differences of each AD chip, resulting in large distortion of the final synthesized signal.

Reproducible data collection means that the data to be collected can appear repeatedly, that is, it can be collected repeatedly. Many data in embedded measurement applications have this characteristic, such as laser range finders. Aiming at such data acquisition application occasions, the present invention proposes a method for realizing high sampling rate data acquisition by using a low sampling rate analog-to-digital conversion chip through multiple repeated acquisitions.

Contents of the invention

The purpose of the present invention is to provide a reproducible data acquisition system with an ultra-high sampling rate, so as to solve the problem that existing signal distortions caused by multiple low-sampling-rate analog-to-digital conversion chips for data sampling are relatively large, which easily causes FPGA resources to Insufficient problem.

The second object of the present invention is to provide a reproducible data acquisition system with an ultra-high sampling rate, so as to realize data acquisition at an ultra-high sampling rate by repeatedly collecting data through an analog-to-digital conversion chip with a low sampling rate.

To achieve the above object, the invention provides a reproducible data acquisition system with an ultra-high sampling rate, comprising an analog-to-digital conversion chip, an embedded CPU, an FPGA processing unit and a data memory, and the FPGA processing unit includes an ADC interface module, Multi-phase clock generation module, data processing module, MIG memory interface module, CPU data reading and writing module and CPU control register;

The embedded CPU is used to write the acquisition phase signal and the acquisition start signal into the CPU control register;

The CPU control register is used to transmit the acquisition phase signal and the acquisition start signal to the multi-phase clock generation module; the multi-phase clock generation module is used to generate n phase differences according to the received acquisition start signal and be 2π/n clock signal, and select the i-th road signal in the n clock signals according to the received acquisition phase signal to input the analog-to-digital conversion chip, where i and n are positive integers, and 1≤i≤n;

The analog-to-digital conversion chip is used to collect data according to the received i-th clock signal and input the collected i-th data into the ADC interface module;

The ADC interface module is used to perform data buffering and clock synchronization processing on the collected i-th data, and input the processed i-th data into the data processing module;

The MIG memory interface module is used to read and write the i-th data in the data memory;

The data memory is used to store the i-th data written by the MIG memory interface module;

The data processing module is used to perform filtering and noise reduction processing on the input processed i-th data to obtain filtered and noise-reduced i-th data, and at the same time, the data processing module combines the filtered and noise-reduced i-th data with the The i-th data from the data memory read by the MIG memory interface module is subjected to a weighted average operation to obtain the i-th data after the weighted average, and the i-th data after the weighted average is written into the data through the MIG memory interface module memory;

Wherein, the analog-to-digital conversion chip is a low-rate ADC analog-to-digital conversion chip, and each time data is collected, the embedded CPU controls the analog-to-digital conversion chip through the FPGA processing unit to complete the n-way data of n clock signals Collect and write the obtained n-way data into the data memory respectively;

The CPU data read-write module is used to combine the n-way data in the data memory by phase to obtain the final high-resolution sampling data, and input the final high-resolution sampling data into the embedded CPU through the CPU control register .

Preferably, the multi-phase clock generation module includes a phase selection register and a DCM clock management unit, the DCM clock management unit is used to generate n clock signals with a phase difference of 2π/n according to the received acquisition start signal, and inputting the n clock signals into the phase selection register; the phase selection register inputs the i-th clock signal among the n clock signals into the analog-to-digital conversion chip according to the received acquisition phase signal.

Preferably, the data memory includes n data storage areas, which are phase 0 data storage area to phase n data storage area; wherein, the phase i data storage area is used to store data written under the action of the i-th clock signal.

Preferably, the weighted average operation performed by the data processing module is specifically: multiplying the newly acquired data of phase i by coefficient w0, multiplying the data of phase i stored in the data memory by w1, and then multiplying the two channels The multiplied data are added together to obtain new data of phase i after weighted average.

The principle of the system design scheme of the present invention is to generate n clock signals with a phase difference of 2π/n through the DCM unit of the FPGA, and give the clock signals of different phases to the ADC during each data acquisition to realize data acquisition of different phases, and finally in the FPGA. The data acquisition results of different phases are combined to form a high sampling rate data acquisition result of n times the ADC sampling rate. Among them, the data acquisition of each phase is collected repeatedly for filtering processing, which can eliminate noise and further improve the performance of the data acquisition system.

This solution is mainly composed of a low-rate analog-to-digital conversion chip, FPGA, data memory and embedded CPU. The ADC completes the sampling and quantification of data, FPGA is responsible for the main control and data processing operations, and the data memory is responsible for storing the collected data. . The system implements a low-rate analog-to-digital conversion chip for high-sampling-rate data acquisition. The system is simple to control, requires less computing power of the FPGA, is easy to implement, and collects data with higher precision.

Description of drawings

Fig. 1 is a schematic diagram of the basic principles of the present invention;

Fig. 2 is a schematic composition diagram of the ultra-high sampling rate reproducible data acquisition system of the preferred embodiment of the present invention;

FIG. 3A is a schematic diagram of the composition and structure of a multi-phase clock module in a preferred embodiment of the present invention;

FIG. 3B is a clock signal relationship diagram corresponding to the composition structure of the multi-phase clock module in FIG. 3A;

Fig. 4 is a schematic diagram of the weighted average processing process of the data processing module.

detailed description

In order to better illustrate the present invention, the present invention will be described in detail with a preferred embodiment and with accompanying drawings, specifically as follows:

As shown in Figure 1, 4 samples are taken in each data acquisition. When the data is collected by the analog-to-digital conversion chip ADC with a low sampling rate, the sampling points corresponding to the arrows marked 1 in Figure 1 are collected for the first time, that is, points A, E and I; The sampling points of the arrows, that is, points B, F, and J; the sampling points of the arrows corresponding to the number 3 of the third sampling, that is, points C and G, and the sampling points of the arrows corresponding to the number 4 of the fourth sampling, that is, points D and H . Combining the results of these four samplings through the FPGA, a sampling signal of four times the sampling rate of A, B, C, D, E, F, G, H, I, and J in the above figure is obtained. In this embodiment, 4 clock signals are used for sampling, and 4 sets of clocks with a phase difference of 90 degrees are divided into 4 samples, and the sampling points corresponding to the arrows labeled 1, 2, 3, and 4 in FIG. 1 are respectively collected. Then combined in FPGA, high-speed acquisition of 4 times the sampling rate can be realized.

The ultra-high sampling rate provided by the present embodiment can reproduce the data acquisition system as shown in Figure 2, and this system comprises an analog-to-digital conversion chip 10, embedded CPU20, FPGA processing unit 30 and data memory 40, and FPGA processing unit 30 comprises ADC interface module 31, multi-phase clock generation module 32, data processing module 33, MIG memory interface module 34, CPU data read-write module 35 and CPU control register 36; Wherein, multi-phase clock generation module 32 comprises a phase selection register 321 and A DCM clock management unit 322 .

When the system is working, the CPU control register 36 transmits the acquisition phase signal and the acquisition start signal to the multi-phase clock generation module 32 . As shown in Figure 3A, the DCM clock management unit 322 in the multi-phase clock generation module 32 generates four clock signals with a phase difference of π/2 according to the received acquisition start signal (clk_in), and inputs the four clock signals into the phase Select register 321 . These four signals are shown in FIG. 3B , which are four clock signals of phase 0 (clk 0), phase 90 degrees (clk 90), phase 180 degrees (clk 180) and phase 270 degrees (clk 270). The phase selection register 321 selects the i-th clock signal (with a phase of πi/2) among the four clock signals according to the received acquisition phase signal as the ADC sampling clock to input to the analog-to-digital conversion chip 10 and the ADC interface module 31 . In this embodiment, i is a positive integer, and 1≤i≤4.

The analog-to-digital conversion chip 10 performs data acquisition according to the received i-th clock signal with the clock signal as a clock reference and inputs the collected i-th road data into the ADC interface module 31;

The ADC interface module 31 performs data buffering on the collected i-th road data, and performs clock synchronization processing according to the received i-th road clock signal from the multi-phase clock generation module 32, and inputs the clock synchronously processed data into the data processing module 33.

The MIG memory interface module 34 performs read and write operations on the i-th path of data in the data memory 40 .

The data memory 40 is used to store the i-th way of data written by the MIG memory interface module 34 .

The data processing module 33 performs filtering and noise reduction processing on the i-th data after input clock synchronization processing to obtain the i-th data with filtering and noise reduction, and at the same time, the data processing module 33 combines the i-th data with filtering and noise reduction through the MIG memory interface The i-th road data read by the module 34 from the data memory 40 performs a weighted average calculation to obtain the i-th road data after the weighted average, and write the i-th road data after the weighted average into the data memory 40 through the MIG memory interface module 34 .

Wherein, the analog-to-digital conversion chip 10 is a low-rate ADC analog-to-digital conversion chip, and the data sampling rate of the ADC analog-to-digital conversion chip in this embodiment is 125 MSPS. In the process of using this system to collect data, each time data is collected, the embedded CPU 20 controls the analog-to-digital conversion chip 10 through the FPGA processing unit 30 to complete the data collection of 4 clock signals, and the data of 4 different phases obtained are respectively Write data memory 40.

Embedded CPU 20 sends acquisition data instruction to CPU control register 36, and CPU control register 36 sends control instruction to CPU data read-write module, and the data stored in the data memory is combined by phase by CPU data read-write module 35, obtains final high resolution sampling data, the sampling rate of the sampling data is 4×125MSPS=500 MSPS, and the final high-resolution sampling data is input into the embedded CPU20 through the CPU control register 36 again, that is, one data acquisition work is completed.

As shown in FIG. 4 , the data memory 40 includes four data storage areas, which are phase 0 data storage area, phase 1 data storage area, phase 3 data storage area and phase 4 data storage area. Wherein, the phase i data storage area is used to store the data written under the action of the i-th clock signal. The weighted average calculation of the data processing module 33 is specifically to multiply the newly collected data of the phase i with the coefficient w0, multiply the data of the phase n stored in the data memory 40 with w1, and then add the two-way multiplied data, That is, the new data of the processed phase i (i-th road) (that is, the i-th road data after weighted average) is obtained. Among them, the weighted values w0 and w1 can be set through the embedded CPU according to different requirements, so as to realize flexible noise reduction processing.

Certainly, the present invention is not limited to the above-mentioned embodiments. During specific implementation, each data collection can carry out data collection at a low sampling rate of n clock signals with a phase difference of 2π/n, where n is an integer greater than 1. Correspondingly, other device performance parameters are not limited by the above-mentioned embodiments.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any deformation or replacement made by those skilled in the art within the technical scope disclosed in the present invention shall be Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (3)

1. A reproducible data acquisition system with an ultra-high sampling rate is characterized in that it comprises an analog-to-digital conversion chip, an embedded CPU, an FPGA processing unit and a data memory, and the FPGA processing unit comprises an ADC interface module, a multi-phase clock Generating module, data processing module, MIG memory interface module, CPU data reading and writing module and CPU control register; The embedded CPU is used to write the acquisition phase signal and the acquisition start signal into the CPU control register; The CPU control register is used to transmit the acquisition phase signal and the acquisition start signal to the multi-phase clock generation module; the multi-phase clock generation module is used to generate n phase differences according to the received acquisition start signal and be 2π/n clock signal, and select the i-th road signal in the n clock signals according to the received acquisition phase signal to input the analog-to-digital conversion chip, i, n are positive integers, and 1≤i≤n, the multi-phase clock generates The module includes a phase selection register and a DCM clock management unit, the DCM clock management unit is used to generate n clock signals with a phase difference of 2π/n according to the received acquisition start signal, and input the n clock signals into the A phase selection register; the phase selection register inputs the i-th clock signal in the n clock signals into the analog-to-digital conversion chip according to the received acquisition phase signal; The analog-to-digital conversion chip is used to collect data according to the received i-th clock signal and input the collected i-th data into the ADC interface module; The ADC interface module is used to perform data buffering and clock synchronization processing on the collected i-th data, and input the processed i-th data into the data processing module; The MIG memory interface module is used to read and write the i-th data in the data memory; The data memory is used to store the i-th data written by the MIG memory interface module; The data processing module is used to perform filtering and noise reduction processing on the input processed i-th data to obtain filtered and noise-reduced i-th data, and at the same time, the data processing module combines the filtered and noise-reduced i-th data with the The i-th data from the data memory read by the MIG memory interface module is subjected to a weighted average operation to obtain the i-th data after the weighted average, and the i-th data after the weighted average is written into the data through the MIG memory interface module memory; Wherein, the analog-to-digital conversion chip is a low-rate ADC analog-to-digital conversion chip, and each time data is collected, the embedded CPU controls the analog-to-digital conversion chip through the FPGA processing unit to complete the n-way data of n clock signals Collect and write the obtained n-way data into the data memory respectively; The CPU data read-write module is used to combine the n-way data in the data memory by phase to obtain the final high-resolution sampling data, and input the final high-resolution sampling data into the embedded CPU through the CPU control register . 2. The reproducible data acquisition system with ultra-high sampling rate according to claim 1, wherein the data memory comprises n data storage areas, which are respectively phase 0 data storage area to phase n data storage area; wherein, the phase The i data storage area is used to store data written under the action of the i-th clock signal. 3. The reproducible data acquisition system with ultra-high sampling rate according to claim 1, wherein the weighted average calculation carried out by the data processing module is specifically: combining the newly collected data of phase i with the data set by the embedded CPU Multiply the weighted value w0 of the data memory, multiply the data of the phase i stored in the data memory with the weighted value w1 set by the embedded CPU, and then add the two multiplied data to obtain the phase i after the weighted average of new data.