CN104597802B - A kind of reproducible data collecting system of superelevation sample rate - Google Patents
A kind of reproducible data collecting system of superelevation sample rate Download PDFInfo
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- CN104597802B CN104597802B CN201410701064.4A CN201410701064A CN104597802B CN 104597802 B CN104597802 B CN 104597802B CN 201410701064 A CN201410701064 A CN 201410701064A CN 104597802 B CN104597802 B CN 104597802B
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Abstract
The invention provides a kind of reproducible data collecting system of superelevation sample rate, the system includes ADC modulus conversion chips, embedded type CPU, FPGA processing units and data storage, the clock signal that n phase differs 2 π/n is produced by FPGA DCM units, clock signal during data acquisition to ADC outs of phase each time, realize the data acquisition of out of phase, finally the data acquisition results of out of phase are combined in FPGA, the high sampling rate data acquisition results of n times of ADC sample rates are collectively constituted.Wherein, the data acquisition to each phase be repeated several times collection to be filtered processing, can eliminate noise, further improve the performance of data collecting system.The system realizes the work of the modulus conversion chip progress high sampling rate data acquisition of a low rate, and system control is simple, and the operational capability to FPGA requires relatively low, it is easy to accomplish, and the data precision of collection is higher.
Description
Technical field
The present invention relates to a kind of data collecting system, more particularly to a kind of reproducible data collecting system of superelevation sample rate.
Background technology
Modern electronic technology is developed rapidly so that embeded processor performance constantly lifts, such as current ARM series
Embeded processor, its performance be no less than 1 year before PC processors.The embeded processor of these high speeds derives
Increasing built-in type high speed data processing system.However, data are carried out with the performance of the modulus conversion chip of sample quantization
Lifting but lags far behind the speed of processor performance lifting.Therefore how to realize at a high speed, accurately, the data acquisition of big data quantity
Data turn into where the key and bottleneck of modern embedded data processing system.
Data acquisition unit generally carries out sample quantization to analog signal using modulus conversion chip (ADC) and is converted to number
Font number is acquired afterwards, and the speed of its sampling, i.e. sample rate may be restricted to the sampling rate parameter of modulus conversion chip.For
Realize superfast data acquisition, it is common practice to which, using polylith modulus conversion chip composition AD conversion array, every piece turns
The sampling clock that chip connects out of phase is changed, then the sampled result of different phases is combined using FPGA again, is synthesized
Method in the sampled result of one high sampling rate, such as Patent No. CN202033737U Chinese utility model patent, is profit
The A/D converter time-interleaved for being 125MSPS with two sampling rates sampling signal all the way, realizes 250MSPS sampling speed
Rate.But, the method for this polylith AD conversion chip point phase acquisition needs polylith A/D chip and more FPGA pins, cost
It is higher and to easily cause FPGA resource not enough.In addition from performance, polylith A/D chip data collecting system can also be because of
Some parameter differences of each A/D chip and have certain amplitude and the difference of direct current biasing between causing out of phase, so as to make
It is larger into the distorted signals finally synthesized.
Reproducible data acquisition, refers to that data to be collected can repeat, you can with repeated acquisition, many embedded
Data in measurement application all have this characteristic, such as laser range finder.The present invention is directed to this data acquisition application scenario,
A kind of use low sampling rate modulus conversion chip is proposed by the way that the method that high sampling rate data acquisition is realized in collection is repeated several times.
The content of the invention
It is an object of the invention to provide a kind of reproducible data collecting system of superelevation sample rate, to solve existing use
The distorted signals that the modulus conversion chip of multiple low sampling rates is carried out present in data sampling is larger, it is easy to cause FPGA resource not
Sufficient the problem of.
It is a second object of the invention to provide a kind of reproducible data collecting system of superelevation sample rate, is passed through with realizing
The modulus conversion chip of one low sampling rate realizes the data acquisition of superelevation sample rate by the way that gathered data is repeated several times.
To achieve the above object, the invention provides a kind of reproducible data collecting system of superelevation sample rate, including a mould
Number conversion chip, embedded type CPU, FPGA processing units and data storage, the FPGA processing units include ADC interface mould
Block, multiphase clock generation module, data processing module, MIG memory interfaces module, cpu data module for reading and writing and CPU controls
Register；
The embedded type CPU is used to write acquisition phase signal and collection commencing signal into the CPU control register；
CPU control register is used to send the acquisition phase signal and collection commencing signal to the multiphase clock
Generation module；The multiphase clock generation module be used for according to the collection commencing signal of reception produce n phase difference be 2 π/
N clock signal, and n the i-th roads of clock signal Zhong signal input mould is chosen according to the acquisition phase signal of reception
Number conversion chips, i, n are positive integer, and 1≤i≤n；
The modulus conversion chip is used to carry out data acquisition and by the i-th of collection according to the i-th tunnel clock signal received
Circuit-switched data inputs the ADC interface module；
The ADC interface module is used to carry out the i-th circuit-switched data of collection data buffer storage and clock synchronization process, and will place
The i-th circuit-switched data after reason inputs the data processing module；
The MIG memory interfaces module is used to be written and read operation to the i-th circuit-switched data in the data storage；
The data storage is used for the i-th circuit-switched data for storing the MIG memory interfaces module write-in；
The data processing module is filtered for being filtered noise reduction process to the i-th circuit-switched data after the processing of input
I-th circuit-switched data of noise reduction, while the data processing module will filter the i-th circuit-switched data and the MIG memory interfaces mould of noise reduction
The i-th circuit-switched data from data storage that block is read is weighted average calculating operation, obtains the i-th circuit-switched data after weighted average,
And the i-th circuit-switched data after weighted average is write by data storage by the MIG memory interfaces module；
Wherein, the modulus conversion chip is low rate ADC modulus conversion chips, during each data acquisition, the insertion
The n circuit-switched datas that formula CPU controls the modulus conversion chip to complete n clock signal by the FPGA processing units gather and incite somebody to action
Obtained n circuit-switched datas are respectively written into data storage；
The cpu data module for reading and writing is used to the n circuit-switched datas in the data storage pressing phase combination, obtains final
High-resolution sampled data, it is and by CPU control register that final high-resolution sampled data data input is embedded
CPU。
It is preferred that the multiphase clock generation module includes a Selecting phasing register and a DCM Clock Managing Units,
The DCM Clock Managing Units are used to produce clock signal of the n phase difference for 2 π/n according to the collection commencing signal of reception,
And by Selecting phasing register described in the n roads clock signal input；The Selecting phasing register root according to reception acquisition phase
Signal is by modulus conversion chip described in n the i-th tunnels of clock signal Zhong clock signal input.
It is preferred that data storage includes n data storage area, the respectively data storage area of phase 0 to phase n data are deposited
Storage area；Wherein, phase i data storage areas are used for the data for storing the i-th lower write-in of tunnel clock signal effect.
It is preferred that the weighted mean operation that the data processing module is carried out is specially：By the freshly harvested data of phase i with
Coefficient w0 is multiplied, and the data for the phase i that the data storage is stored are multiplied with w1, then the data phase after two-way is multiplied
Plus, that is, obtain the new data of the phase i after weighted average.
The system design scheme principle of the present invention is to produce the clock that n phase differs 2 π/n by FPGA DCM units
Signal, clock signal during data acquisition to ADC outs of phase, realizes the data acquisition of out of phase, finally exists each time
The data acquisition results of out of phase are combined in FPGA, the high sampling rate data acquisition of n times of ADC sample rates is collectively constituted
As a result.Wherein, the data acquisition to each phase be repeated several times collection to be filtered processing, can eliminate noise,
Further improve the performance of data collecting system.
The main modulus conversion chip by a low rate of this programme, FPGA, data storage and common group of embedded type CPU
Into wherein ADC completes the sample quantization of data, and FPGA is responsible for the main control of completion and data processing operation, data storage
It is responsible for the data of storage collection.The modulus conversion chip that the system realizes a low rate carries out high sampling rate data acquisition
Work, system control is simple, and the operational capability to FPGA requires relatively low, it is easy to accomplish, and the data precision of collection is higher.
Brief description of the drawings
Fig. 1 is basic principle schematic of the invention；
Fig. 2 is the reproducible data collecting system composition schematic diagram of superelevation sample rate of the preferred embodiment of the present invention；
Fig. 3 A constitute structural representation for the multiphase clock module of the preferred embodiment of the present invention；
Fig. 3 B are clock signal graph of a relation corresponding with the multiphase clock module composition structure in Fig. 3 A；
Fig. 4 is the weighted average processing procedure schematic diagram of data processing module.
Embodiment
For the present invention is better described, hereby with a preferred embodiment, and accompanying drawing is coordinated to elaborate the present invention, specifically
It is as follows：
It is shown in Figure 1,4 samplings are carried out in each data acquisition.As the modulus conversion chip ADC using low sampling rate
When being acquired to data, the corresponding sampled point of arrow in Fig. 1 marked as 1, i.e. A, E and I point are gathered for the first time；Adopt for the second time
The sampled point of the sample collection correspondence arrow of label 2, i.e. B, F, J point；The sampled point of the correspondence arrow of third time sampled acquisition label 3, i.e.,
C, G point, the sampled point of the 4th correspondence arrow of sampled acquisition label 4, i.e. D, H point.The result that this four times are sampled by FPGA
Combine, just obtain the sampled signal of a four sampling rates of A, B, C, D, E, F, G, H, I and J in upper figure.The present embodiment
Sampled, the clock for differing 90 degree by 4 groups of phases is divided into 4 samplings, collected respectively corresponding to figure with 4 clock signals
Marked as 1 in 1,2,3, the 4 corresponding sampled point of arrow, then be combined in FPGA, it is possible to realize the height of 4 sampling rates
Speed collection.
The reproducible data collecting system of superelevation sample rate that the present embodiment is provided is as shown in Fig. 2 the system includes a mould
Number conversion chip 10, embedded type CPU 20, FPGA processing units 30 and data storage 40, FPGA processing units 30 include
ADC interface module 31, multiphase clock generation module 32, data processing module 33, MIG memory interfaces module 34, cpu data are read
Writing module 35 and CPU control register 36；Wherein, multiphase clock generation module 32 includes a Selecting phasing register 321
And DCM Clock Managing Units 322.
When the system works, acquisition phase signal and collection commencing signal are transmitted to leggy by CPU control register 36
Clock generation module 32.As shown in Figure 3A, the DCM Clock Managing Units 322 in multiphase clock generation module 32 are according to reception
Collection commencing signal（clk_in）Produce clock signal of 4 phases difference for pi/2, and by the 4 tunnel clock signal input phase
Position mask register 321.This four roads signal as shown in Figure 3 B, respectively phase 0（clk 0）, 90 degree of phase（clk 90）, phase
180 degree（clk 180）And 270 degree of phase（clk 270）Four tunnel clock signals.Selecting phasing register 321 is adopted according to reception
Collection phase signal selects 4 the i-th tunnels of clock signal Zhong clock signals（Phase is π i/2）Mould is inputted as ADC sampling clocks
Number conversion chip 10 and ADC interface module 31.In the present embodiment, i is positive integer, and 1≤i≤4.
Modulus conversion chip 10 carries out data by clock reference of the clock signal according to the i-th tunnel clock signal received and adopted
Collect and the i-th circuit-switched data of collection is inputted into ADC interface module 31；
I-th circuit-switched data of 31 pairs of collections of ADC interface module carries out data buffer storage, and during according to being received from leggy
I-th tunnel clock signal of clock generation module 32, which is combined, does clock synchronization process, and by the data input after clock synchronization process
Data processing module 33.
MIG memory interfaces module 34 performs read-write operation to the i-th circuit-switched data in data storage 40.
Data storage 40 is used for the i-th circuit-switched data for storing the write-in of MIG memory interfaces module 34.
The i-th circuit-switched data after the clock synchronization process of 33 pairs of inputs of data processing module is filtered noise reduction process and filtered
I-th circuit-switched data of ripple noise reduction, while data processing module 33 will filter the i-th circuit-switched data of noise reduction and pass through MIG memory interface moulds
The i-th circuit-switched data from data storage 40 that block 34 is read is weighted average calculating operation, obtains the i-th way after weighted average
According to, and the i-th circuit-switched data after weighted average is write into data storage 40 by MIG memory interfaces module 34.
Wherein, modulus conversion chip 10 is the ADC analog-to-digital conversions in the ADC modulus conversion chips of low rate, the present embodiment
The data sample rates of chip are 125MSPS.It is embedding during each data acquisition during carrying out data acquisition using the system
Enter the data acquisition that formula CPU20 controls modulus conversion chip 10 to complete 4 clock signals by FPGA processing units 30, and incite somebody to action
To the data of 4 kinds of outs of phase be respectively written into data storage 40.
Embedded type CPU 20, which is sent, obtains data command to CPU control register 36, and CPU control register 36 sends control
Instruct and give cpu data module for reading and writing, by cpu data module for reading and writing 35 by the data stored in data storage by phase-group
Close, obtain final high-resolution sampled data, the sampling rate of the sampled data is the MSPS of 4 × 125MSPS=500, and again
It is secondary by CPU control register 36 by final high-resolution sampled data data input embedded type CPU 20, that is, complete once
Data collection task.
As shown in figure 4, data storage 40 includes 4 data storage areas, the respectively data storage area of phase 0, phase 1 is counted
According to memory block, the data storage area of phase 3 and the data storage area of phase 4.Wherein, when phase i data storage areas are used to store the i-th tunnel
The data write under clock signal function.The weighted mean operation of data processing module 33 is specially by the freshly harvested data of phase i
It is multiplied with coefficient w0, the data for the phase n that data storage 40 is stored are multiplied with w1, then the data phase after two-way is multiplied
Plus, produce treated phase i（I-th tunnel）New data（The i-th circuit-switched data i.e. after weighted average）.Wherein, weighted value w0
It can be set with w1 according to different demands by embedded type CPU, realize flexible noise reduction process.
Certainly, the present invention is not limited with above-described embodiment, when it is implemented, data acquisition can carry out n phase every time
Difference is the data acquisition of the low sampling rate of 2 π/n clock signal, and n is the integer more than 1.Correspondingly, remaining device parameter performance
Also do not limited by above-described embodiment.
The foregoing is only a specific embodiment of the invention, but protection scope of the present invention is not limited thereto, any
Those skilled in the art the invention discloses technical scope in, to the present invention deformation or replacement done, should all cover
Within protection scope of the present invention.Therefore, protection scope of the present invention should be defined by described scope of the claims.
Claims (3)
1. a kind of reproducible data collecting system of superelevation sample rate, it is characterised in that including a modulus conversion chip, embedded
CPU, FPGA processing unit and data storage, the FPGA processing units include ADC interface module, multiphase clock and produced
Module, data processing module, MIG memory interfaces module, cpu data module for reading and writing and CPU control register；
The embedded type CPU is used to write acquisition phase signal and collection commencing signal into the CPU control register；
CPU control register is used to send the acquisition phase signal and collection commencing signal to the multiphase clock generation
Module；It is 2 π/n's that the multiphase clock generation module, which is used to produce n phase difference according to the collection commencing signal of reception,
Clock signal, and n the i-th roads of clock signal Zhong signal input modulus turn is chosen according to the acquisition phase signal of reception
Change chip, i, n are positive integer, and 1≤i≤n, the multiphase clock generation module includes a Selecting phasing register and one
DCM Clock Managing Units, the DCM Clock Managing Units are used to produce n phase difference according to the collection commencing signal of reception
For 2 π/n clock signal, and by Selecting phasing register described in the n roads clock signal input；The Selecting phasing register root
According to the acquisition phase signal of reception by modulus conversion chip described in n the i-th tunnels of clock signal Zhong clock signal input；
The modulus conversion chip is used to carry out data acquisition and by the i-th way of collection according to the i-th tunnel clock signal received
According to the input ADC interface module；
The ADC interface module is used to carry out the i-th circuit-switched data of collection data buffer storage and clock synchronization process, and by after processing
The i-th circuit-switched data input the data processing module；
The MIG memory interfaces module is used to be written and read operation to the i-th circuit-switched data in the data storage；
The data storage is used for the i-th circuit-switched data for storing the MIG memory interfaces module write-in；
The data processing module obtains filtering noise reduction for being filtered the i-th circuit-switched data after the processing of input noise reduction process
The i-th circuit-switched data, while the i-th circuit-switched data and the MIG memory interfaces module that the data processing module will filter noise reduction are read
The i-th circuit-switched data from data storage taken is weighted average calculating operation, obtains the i-th circuit-switched data after weighted average, and lead to
Cross the MIG memory interfaces module and the i-th circuit-switched data after weighted average is write into data storage；
Wherein, the modulus conversion chip is low rate ADC modulus conversion chips, during each data acquisition, the embedded type CPU
The n circuit-switched datas for controlling the modulus conversion chip to complete n clock signal by the FPGA processing units are gathered and will obtained
N circuit-switched datas be respectively written into data storage；
The cpu data module for reading and writing is used to the n circuit-switched datas in the data storage pressing phase combination, obtains final height
Resolution ratio sampled data, and by CPU control register by final high-resolution sampled data data input embedded type CPU.
2. the reproducible data collecting system of superelevation sample rate according to claim 1, it is characterised in that data storage bag
Include n data storage area, the respectively data storage area of phase 0 to phase n data storage areas；Wherein, phase i data storage areas are used
In the data of the lower write-in of the i-th tunnel of storage clock signal effect.
3. the reproducible data collecting system of superelevation sample rate according to claim 1, it is characterised in that the data processing
Module carry out weighted mean operation be specially：By the freshly harvested data of phase i and the weighted value w0 set by embedded type CPU
It is multiplied, the data for the phase i that the data storage is stored are multiplied with the weighted value w1 set by embedded type CPU, then will
Data after two-way is multiplied are added, and obtain the new data of the phase i after weighted average.
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105847714B (en) * | 2016-05-24 | 2018-10-09 | 中国科学院长春光学精密机械与物理研究所 | The delay of CMOS input image datas corrects system |
| CN106444352B (en) * | 2016-11-08 | 2019-05-03 | 青岛大豪信息技术有限公司 | A kind of clock method for synchronously measuring and system based on double buffering |
| CN107374621B (en) * | 2017-08-31 | 2020-12-22 | 华南理工大学 | Channel sampling rate high-low distribution method for electroencephalogram signal acquisition |
| CN109738907A (en) * | 2019-03-13 | 2019-05-10 | 武汉海达数云技术有限公司 | Laser waveform data acquisition device and method |
| CN112462192A (en) * | 2020-11-04 | 2021-03-09 | 南京航空航天大学 | ADC frequency increasing system and method for aviation cable fault detection based on TDR technology |
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