CN109116353B - Method for realizing stolt interpolation by using FPGA (field programmable Gate array) and FPGA system - Google Patents

Method for realizing stolt interpolation by using FPGA (field programmable Gate array) and FPGA system Download PDF

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CN109116353B
CN109116353B CN201810799869.5A CN201810799869A CN109116353B CN 109116353 B CN109116353 B CN 109116353B CN 201810799869 A CN201810799869 A CN 201810799869A CN 109116353 B CN109116353 B CN 109116353B
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interpolation
frequency
data
module
coordinates
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CN109116353A (en
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江率
刘霖
曹越
许士杰
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Institute of Electronics of CAS
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/88—Radar or analogous systems specially adapted for specific applications
    • G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
    • G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/88—Radar or analogous systems specially adapted for specific applications
    • G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
    • G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
    • G01S13/9004—SAR image acquisition techniques
    • G01S13/9011—SAR image acquisition techniques with frequency domain processing of the SAR signals in azimuth
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/28—Details of pulse systems
    • G01S7/285—Receivers
    • G01S7/295—Means for transforming co-ordinates or for evaluating data, e.g. using computers

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  • Radar, Positioning & Navigation (AREA)
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  • Signal Processing (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The invention provides a method for realizing stolt interpolation by using an FPGA (field programmable gate array), which comprises the following steps of: s1, calculating frequency coordinates required by the implementation of the stop interpolation according to the system parameters; s2, converting the frequency coordinate into a known frequency coordinate according to the stolt mapping relation, and obtaining a frequency coordinate to be interpolated; s3, obtaining the position of a data point for interpolation according to the frequency coordinate, calculating a sinc function value according to the position of the data point and extracting corresponding radar data; and S4, performing interpolation according to the sinc function value and the radar data, and framing and outputting the interpolated data. The invention also provides an FPGA system for realizing the stolt interpolation. The invention realizes accurate stolt interpolation through the FPGA and reduces the complexity of the system.

Description

Method for realizing stolt interpolation by using FPGA (field programmable Gate array) and FPGA system
Technical Field
The invention relates to the field of radar imaging, in particular to a method for realizing stort interpolation and an FPGA system for realizing the stort interpolation.
Background
The Synthetic Aperture Radar (SAR) is an active remote sensor working in a microwave frequency band, overcomes the defect that optical imaging is limited by weather and illumination conditions, can carry out remote sensing observation on the ground all day long, all weather long distance, and greatly improves the information acquisition capability of the radar. The omega K algorithm is a high-precision SAR imaging algorithm, is suitable for wide-aperture imaging, can correct distance migration along a distance direction in a large-aperture range as long as the condition of constant speed is met, and has the key steps of performing stop interpolation on distance frequency and mapping a distance frequency coordinate axis to a new coordinate axis so as to enable the phase in any direction in a two-dimensional frequency domain to be linear, thereby correcting the dependency relationship between distance and orientation coupling and distance time and orientation frequency.
However, accurate stolt interpolation is very time consuming and two approaches are currently commonly used to solve this problem. One way to do this is by approximation, which eliminates the residual phase modulation through an azimuth-matched filter that varies along the range direction, ignoring residual range-azimuth coupling and residual range migration, which is effective in low squint or narrow swath but is often not well suited for current airborne SAR. The other implementation mode is realized in an FPGA + DSP mode, and a complex interpolation part is completed by using the DSP, however, the structure of the FPGA + DSP not only increases the complexity of hardware design, but also can not meet the requirements of modern radars in the aspects of system power consumption and volume.
Disclosure of Invention
In order to overcome at least one aspect of the above problem, an embodiment of the present invention provides a method for implementing a stolt interpolation by using an FPGA, including the following steps: s1, calculating frequency coordinates required by the implementation of the stop interpolation according to the system parameters; s2, converting the frequency coordinate into a known frequency coordinate according to the stolt mapping relation, and obtaining a frequency coordinate to be interpolated; s3, obtaining the position of a data point for interpolation according to the frequency coordinate, calculating a sinc function value according to the position of the data point and extracting corresponding radar data; and S4, performing interpolation according to the sinc function value and the radar data, and framing and outputting the interpolated data.
According to some embodiments, step S1 further includes: and writing the radar data corresponding to the frequency coordinates into a memory group.
According to some embodiments, step S3 further includes: and reading radar data corresponding to the frequency coordinates by the memory group.
According to some embodiments, the memory group reads the radar data corresponding to the multiple frequency coordinates at the same time, and sorts the radar data corresponding to the multiple frequency coordinates according to the coordinates of the sampling points and outputs the sorted radar data.
According to some embodiments, the memory group includes a first memory group and a second memory group, and the radar data corresponding to the frequency coordinates are sequentially written in the first memory group and the second memory group, respectively.
On the other hand, the embodiment provides an FPGA system for implementing the store interpolation, which includes the following modules: the coordinate construction module is used for calculating frequency coordinates required for realizing the stop interpolation according to the system parameters; the frequency point mapping module is used for converting the frequency coordinates into known frequency coordinates according to the stolt mapping relation to obtain frequency coordinates to be interpolated; the sinc function calculation module is used for obtaining the position of a data point used for interpolation according to the frequency coordinate and calculating a sinc function value according to the position of the data point; the data caching module is used for caching radar data and extracting the radar data according to the position of the data point; the interpolation module is used for carrying out interpolation according to the sinc function value and the radar data; and the output module is used for framing and outputting the data subjected to interpolation.
According to some embodiments, the FPGA system further includes a memory bank read-write control module for controlling read-write operations of the memory bank.
According to some embodiments, the memory bank includes N sub-memories, N being the number of convolution points set for the interpolation operation.
According to some embodiments, the memory bank read-write control module is further configured to control the memory to simultaneously read the radar data corresponding to the multiple frequency coordinates, and output the radar data corresponding to the multiple frequency coordinates after sorting according to the coordinates of the sampling points.
According to some embodiments, the FPGA system further includes a control module, configured to perform state identification and control between the memory bank read-write control module and the frequency point mapping module, the sinc function calculation module, and the interpolation module, and control a start sequence of each module.
Compared with the prior art, the invention has at least one of the following advantages:
(1) the invention completes the accurate stolt interpolation operation without obviously increasing the power consumption and the volume of the system;
(2) in any signal processing system needing interpolation operation, the method can be adopted to carry out interpolation operation, and the application range is wide;
drawings
Other objects and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings, and may assist in a comprehensive understanding of the invention.
FIG. 1 is a work flow diagram of one embodiment of the present invention;
FIG. 2 is a schematic diagram of a data storage method and output according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs.
The invention provides a method for realizing the stolt interpolation by using an FPGA (field programmable gate array), which realizes the accurate interpolation of the stolt without obviously increasing the power consumption and the volume of a system. The embodiments of the present invention will be further described with reference to the accompanying drawings.
FIG. 1 is a workflow diagram according to an embodiment of the invention. As shown in fig. 1, the method for implementing stop interpolation by using FPGA in the embodiment of the present invention includes the following steps:
and S1, calculating frequency coordinate data required by realizing the stop interpolation according to the system parameters.
When the synthetic aperture radar is used for imaging, parameters, such as a resolution value, a pulse width value and the like, need to be set, and these parameters are called system parameters, and frequency coordinate data required for realizing the stop interpolation can be calculated according to these system parameters. The frequency coordinate data may be, for example, a frequency range and a unit frequency length in a new frequency coordinate, and a frequency coordinate vector in the new frequency coordinate may be obtained from the frequency coordinate data.
According to a preferred embodiment, step S1 further includes: and writing the radar data corresponding to the frequency coordinates into a memory group. N sub-memories form a memory group, the number of each sub-memory is respectively set to be 0, 1 and 2. The memory bank is used for storing each frame data. The memory group adopts a distributed storage mode, namely, each frame of data is written into the N sub-memories in a distributed mode. In the process of writing data, the radar data corresponding to the frequency coordinates are written into the memory group in series according to the sequence, namely, the adjacent N data are respectively written into the N sub-memories.
And S2, converting the frequency coordinate into a known frequency coordinate according to the stolt mapping relation, and obtaining the frequency coordinate to be interpolated.
The frequency coordinate vector under the new frequency coordinate and the known frequency coordinate have a specific corresponding relationship, and the corresponding relationship is called a stop mapping relationship. According to the stop mapping relationship, the frequency coordinate in the new frequency coordinate can be converted into the known frequency coordinate. And obtaining the frequency coordinate to be interpolated according to the frequency point value.
And S3, obtaining the position of a data point for interpolation according to the frequency coordinate, calculating a sinc function value according to the position of the data point and extracting corresponding radar data.
Frequency point coordinates can be further obtained according to the frequency coordinates to be interpolated, the number of the frequency points can be set manually, for example, the number can be 16, and correspondingly, the 16 frequency point coordinates can be obtained. And generating corresponding 16 sinc function values in parallel in real time according to the 16 frequency point coordinates. In other embodiments, the number of frequency points may also be N, so that N corresponding sinc function values may be generated. The positions of data points used for interpolation can be obtained according to the frequency point coordinates, and in addition, the sinc function values and the corresponding radar data need to be operated in the interpolation, so that the corresponding radar data can be extracted according to the positions of the data points.
According to a preferred embodiment, step S3 further includes: and reading radar data corresponding to the frequency coordinates by the memory group. When the radar data corresponding to the frequency coordinates are read, the memory group can simultaneously read the radar data corresponding to the frequency coordinates, the read data are output after being sorted according to the coordinates of the sampling points, and the radar data corresponding to the frequency coordinates can be sorted and output from small to large according to the sequence of the serial numbers.
And S4, performing interpolation according to the sinc function value and the radar data, and framing and outputting the interpolated data.
The extracted radar data and the corresponding sinc function values are subjected to interpolation operation, and each data after the interpolation operation is finished is independent, so that the data can be combined in sequence for subsequent work and output.
According to a preferred embodiment, the memory groups include a first memory group and a second memory group, and the radar data corresponding to the frequency coordinates are sequentially written in the first memory group and the second memory group, respectively. In this embodiment, the writing into the first memory group and the second memory group respectively in sequence means that input data is input sequentially in two ways, first frame data is written into the first memory group, the first memory group reads data to perform interpolation operation, and the second memory group starts to write second frame data, after the interpolation of the first memory group is completed, the writing into a new frame of data can be started to wait, and after the writing into data of the second memory group is completed, the parallel reading of data can be started to perform interpolation operation. The first memory group and the second memory group alternately write data and interpolate, which can greatly improve efficiency.
Fig. 2 is a schematic diagram of a storage manner of a frame of data to be interpolated in a memory bank and output data of one clock cycle, as shown in fig. 2, taking the number N of convolution points as 16 as an example, one memory bank includes 16 memories, which are respectively a RAM0 and a RAM 15. sig [0], sig [1]... sig [ NR-1] are data points of a frame of data, length of a frame of data is NR, sig [ p-8: p +7 represents 16 data points to be interpolated, p is the serial number of the data in one frame of data, and p is more than or equal to 0 and less than or equal to NR-1. Data are output according to the number of the memories, namely according to the sequence of the RAM0 and the RAM1 … … RAM15, so that the output is sig [ p +2], sig [ p +3]. Then, sequencing is carried out according to the serial number of the data points to be interpolated, namely the final output is sig [ p-8], sig [ p-7].
Based on the same concept, the embodiment of the invention also provides an FPGA system for realizing the stolt interpolation, which comprises the following modules:
the coordinate construction module is used for calculating frequency coordinates required for realizing the stop interpolation according to the system parameters;
the frequency point mapping module is used for converting the frequency coordinates into known frequency coordinates according to the stolt mapping relation to obtain frequency coordinates to be interpolated;
the sinc function calculation module is used for obtaining the position of a data point used for interpolation according to the frequency coordinate and calculating a sinc function value according to the position of the data point;
the data caching module is used for caching radar data and extracting the radar data according to the position of the data point;
the interpolation module is used for carrying out interpolation according to the sinc function value and the radar data;
and the output module is used for framing and outputting the data subjected to interpolation.
According to the preferred embodiment, the FPGA system further includes a memory bank read-write control module for controlling the read-write operation of the memory bank. The memory bank includes N memories, N being the number of convolution points set for the interpolation operation.
The memory group read-write control module can generate an enable signal and a write address signal of each memory when controlling the memory group to perform write operation. Counting input data, and the count value is complemented by N, the obtained value corresponds to a memory with a corresponding number, the count value is divided by N, and the integer part of the obtained value corresponds to the write address of the memory. For example, the count value is 20, N is 16, the count value is complemented by N to yield 4, corresponding to the memory enable numbered RAM3, the count value is divided by N to yield 1.25, and the integer portion 1 corresponds to the write address of memory RAM 3.
When the memory bank read-write control module controls the memory bank to read, the read addresses of the memory bank can be generated in parallel, and data can be output in an ordering mode according to sampling point coordinates. Obtaining the position of a point to be interpolated through a frequency point mapping module, rounding the position coordinate to the nearest integer coordinate, then obtaining N pieces of integer position information near the point to be interpolated, and converting the position information into a read address of a memory group, wherein the specific conversion method comprises the following steps: and respectively adding the N position information to N to obtain the number of the corresponding memory, and respectively dividing the number by the integer part obtained by N to obtain the read address of the memory group. The data corresponding to the N coordinate positions are respectively located in the N memories and cannot repeatedly appear in the same memory group, and parallel processing can be achieved. According to the preferred embodiment, the memory group read-write control module is further configured to control the memory to simultaneously read radar data corresponding to the multiple frequency coordinates, and output the read data after sorting according to the coordinates of the sampling points.
The FPGA system also comprises a control module which is used for carrying out state identification and control between the memory bank read-write control module and the frequency point mapping module, between the sinc function calculation module and between the memory bank read-write control module and the interpolation module, and controlling the starting sequence of each module. For example, after one frame of data is written into the memory, frequency point mapping is started, after the frequency point mapping is completed, data is started to be read, and meanwhile, the sinc function calculating module is started to calculate the sinc function value.
The embodiment of the invention completes accurate stolt interpolation operation, is not limited to stolt interpolation operation, and can be used for interpolation operation in any signal processing system needing interpolation operation by adopting the interpolation method in the embodiment of the invention; the invention is completely realized based on FPGA design and has wide application range. The invention stores the data to be interpolated through the distribution of the plurality of memories, so that the signals corresponding to N integer frequency points near any frequency point to be interpolated are respectively stored in N different memories, and all required sampling point data can be simultaneously taken out in one clock period, thereby achieving the effect of interpolating by processing N groups of data in parallel; the invention can meet the processing requirement of a high data rate system by the operation of alternately processing data interpolation by double threads; according to the invention, under the condition that system storage resources are not additionally increased, the interpolation precision can be selected by a user according to the requirement between the omega K imaging precision and the calculation complexity, the stop interpolation precision can be improved by increasing the number of the memories, and the total amount of the data to be stored is unchanged, so that more FPGA capacity is not occupied.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (5)

1. A method for realizing the stolt interpolation by using an FPGA is characterized by comprising the following steps:
s1, calculating frequency coordinates required by the implementation of the stop interpolation according to the system parameters; writing the radar data corresponding to the frequency coordinates into a memory group;
s2, converting the frequency coordinate into a known frequency coordinate according to the stolt mapping relation, and obtaining a frequency coordinate to be interpolated;
s3, obtaining the position of a data point for interpolation according to the frequency coordinate to be interpolated, calculating a sinc function value according to the position of the data point and extracting corresponding radar data; simultaneously reading radar data corresponding to the frequency coordinates from the memory group, and sequencing and outputting the radar data according to coordinates of sampling points;
and S4, performing interpolation according to the sinc function value and the radar data, and framing and outputting the interpolated data.
2. The method for realizing a stolt interpolation by using the FPGA as claimed in claim 1, wherein the memory banks include a first memory bank and a second memory bank, and the radar data corresponding to the frequency coordinate are sequentially and respectively written into the first memory bank and the second memory bank.
3. An FPGA system that implements a store interpolation, the FPGA system comprising:
the coordinate construction module is used for calculating frequency coordinates required for realizing the stop interpolation according to the system parameters;
the frequency point mapping module is used for converting the frequency coordinates into known frequency coordinates according to the stolt mapping relation to obtain frequency coordinates to be interpolated;
the sinc function calculation module is used for obtaining the position of a data point used for interpolation according to the frequency coordinate to be interpolated and calculating a sinc function value according to the position of the data point;
the data caching module is used for caching radar data and extracting the radar data according to the position of the data point;
the interpolation module is used for carrying out interpolation according to the sinc function value and the radar data; and
the output module is used for framing and outputting the data subjected to interpolation;
and the memory group read-write control module is used for controlling the read-write operation of the memory group, controlling the memory group to simultaneously read a plurality of radar data corresponding to the frequency coordinates, and sequencing and outputting the plurality of radar data corresponding to the frequency coordinates according to the coordinates of sampling points.
4. The FPGA system of claim 3, wherein the memory bank comprises N sub-memories, N being a number of convolution points set for an interpolation operation.
5. The FPGA system of claim 3, further comprising a control module configured to perform state identification and control between the memory bank read-write control module and the frequency point mapping module, between the sinc function calculation module and between the memory bank read-write control module and the interpolation module, and to control a start sequence of each module.
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