CN102866390B - Synthetic aperture radar echo simulator and echo simulation processing method - Google Patents
Synthetic aperture radar echo simulator and echo simulation processing method Download PDFInfo
- Publication number
- CN102866390B CN102866390B CN201210353283.9A CN201210353283A CN102866390B CN 102866390 B CN102866390 B CN 102866390B CN 201210353283 A CN201210353283 A CN 201210353283A CN 102866390 B CN102866390 B CN 102866390B
- Authority
- CN
- China
- Prior art keywords
- echo
- scene
- module
- time
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention belongs to the field of the radar signal processing technology and discloses a synthetic aperture radar echo simulator and an echo simulation processing method. The simulator comprises an FPGA (field programmable gate array) chip, a DDR (double data rate), a power module, an upper computer, a network interface module, a D/A (digital to analog) module, a high-speed interface module and a data logger. The simulation method includes the steps of configuration parameter writing, full scene equivalent scattering coefficient determination, system impact response component determination and time-frequency transformation, time-frequency transformation of emission signals, inverse time-frequency transformation processing, small scene or large scene echo signal output and large scene echo signal playback. The single FPGA chip, the DDR and the data logger are only adopted for the main structure, the echo simulation process is achieved by the aid of assembly line work, and the synthetic aperture radar echo simulator has the advantages of simple system structure, high reliability, capabilities of effectively increasing the simulation speed of SAR (synthetic aperture radar) small scene echo signals, achieving real-time simulation of small scene echoes and being used for large scene echo signal simulation and echo signal playback and output, and the like.
Description
Technical field
The invention belongs to Radar Signal Processing Technology field, particularly a kind of synthetic-aperture radar (SAR) echo simulator and SAR analogue echoes disposal route based on field programmable gate array (FPGA).
Background technology
Synthetic-aperture radar (Synthetic Aperture Radar, SAR) is a kind of high-resolution microwave imaging radar, since coming out the fifties in last century, has obtained so far rapid development.In order to assess the indices of SAR system, need a large amount of original echo data, if these data obtain by real carried SAR and satellite-borne SAR, its cost will be very huge, and therefore obtaining needed original echo data by the method for analogue echoes is the important means that address this problem.
The Wang Hongxian of Xian Electronics Science and Technology University etc. has proposed a kind of " the SAR echo simulation Fast implementation based on FPGA " (" systems engineering and electronic technology ", 2010, Vol.32), the method adopts 4 field programmable gate arrays (FPGA) as main process chip, and each fpga chip has distinguished the double digit rate synchronous DRAM of the second generation (DDR) of 1GB external.Interconnected between two by high velocity, low pressure differential signal (LVDS) between each fpga chip.And adopt and SAR echo is carried out to analogue simulation as the flow process of Fig. 1.This technology only needs 8s can complete 6144 echo simulations of 1000 × 1000 scenes, although the speed than traditional PC simulation has improved thousands of times, but the flow process of the method is each echo-pulse need wait that whole scene equivalence scattering coefficient is determined, system shock response FFT, FFT both results are multiplied each other and then carried out after IFFT transmits, could start the processing of next echo-pulse, thereby can only realize the Fast simulation of the little scene echoes in 1km × 1km left and right, and cannot realize the more simulation of large scene echo and the playback of echo; In addition, due to the method adopt echo simulation device be by 4 FPGA by high velocity, low pressure differential signal (LVDS) between two interconnected and every FPGA also need to configure respectively a DDR, therefore system architecture complexity and data loaded down with trivial details alternately not only, the reliability of its work is also poor.Thereby, there is the echo simulation device system architecture complexity that adopts in the method, data alternately loaded down with trivial details, its treatment capacity is little, reliability is also poor, simulation and its analog rate that can only realize little scene echoes are still slower, and can not be used for the disadvantage such as simulation and the playback output of echo to large scene echo.
Summary of the invention
The object of the invention is for the defect existing in background technology, a kind of synthetic-aperture radar echo simulator of research and design and analogue echoes disposal route, reaching at simplied system structure, improve the analog rate that not only can effectively improve the little scene echoes signal of SAR on the basis of its reliability, realize the real time modelling of little scene echoes, but also can be used for the object such as simulation and the playback output of echoed signal to large scene echoed signal.
Technical scheme of the present invention be in the structure of echo simulator, adopt monolithic FPGA+ monolithic DDR, to simplify its system architecture, the mutual link of data in minimizing system is set up a datalogger effectively improving the treatment capacity of echo simulator to echo data, to realize pipelining in analogue echoes processing procedure and to increase the playback output function of echoed signal simultaneously; The present invention realizes its goal of the invention with this.Thereby, echo simulator of the present invention comprises FPGA signal processing chip, synchronous DRAM (DDR), power module, key is that this echo simulator also comprises host computer, Network Interface Module, digital-to-analog conversion (D/A) module, High-speed Interface Card and datalogger; FPGA signal processing chip is that inner Ethernet control module, ram cell, echo generation unit, D/A control module, memory control unit and high-speed interface (CPCI) control module of containing of a slice is at interior FPGA signal processing chip; Ram cell in FPGA signal processing chip is connected with Ethernet control module, and echo generation unit is connected with ram cell, high-speed interface (CPCI) control module, memory control unit and D/A control module respectively; FPGA signal processing chip is connected with host computer by Ethernet control module and Network Interface Module, be connected with synchronous DRAM (DDR) by memory control unit, be connected with High-speed Interface Card by high-speed interface (CPCI) control module, be connected with digital-to-analog conversion (D/A) module by D/A control module; High-speed Interface Card is connected with datalogger again simultaneously, and power module is the power supply that provides to corresponding chip and module.
Above-mentioned D/A module comprises two D/A chips, for the IQ two-way SAR echo digital signal of FPGA signal processing module input is transformed to analog signal output.Described High-speed Interface Card comprises a compact peripheral component interconnection (CPCI) high-speed interface, and the echoed signal that the echoed signal high-speed transfer of generation can be stored and read storage to datalogger from datalogger being connected with datalogger by backboard is carried out the High-speed Interface Card of real-time playback.And described power module is voltage chip PTH05010W and TPS51100; TPS51100 output 1.8V voltage is that DDR power supply, PTH05010W export three groups of voltages altogether, and wherein two groups of voltages of 2.5V and 1.0V are that the power supply of FPGA signal processing module, 3.3V are Network Interface Module and digital-to-analog conversion (D/A) module for power supply.
Synthetic-aperture radar analogue echoes disposal route of the present invention, the steps include:
Writing of step 1. configuration parameter: host computer will transmit and Doppler's component deposits in the ram cell of FPGA signal processing chip, radar system parameter and SAR haplopia complex pattern data (RCS) are deposited in by memory control unit as scene objects backscattering coefficient in synchronous DRAM (DDR) by ethernet signal receiving element through Network Interface Module;
Determining of step 2. whole scene equivalence scattering coefficient: first get first burst length, the each impact point backscattering coefficient of read-out system parameter and scene from DDR, then carries out:
Determining of the instantaneous oblique distance of 2a. and equidistant ring: according to each impact point and Texas tower coordinate, utilize 2 range formulas, calculate each impact point in scene instantaneous oblique distance to Texas tower, and divide equidistant ring according to instantaneous oblique distance;
2b. determines the equivalent scattering coefficient of each rang ring: the impact point scattering coefficient in an equidistant ring is superposeed to determine to the equivalent scattering coefficient of this rang ring, and successively the equivalent scattering coefficient of each rang ring deposited in ram cell, determined to whole scene equivalence scattering coefficient;
Determining of step 3. system shock response component: read Doppler's component from ram cell, and do Complex multiplication processing with step 2b gained whole scene equivalence scattering coefficient, obtain the system shock response component of this pulse, go to step 4;
Step 4. time-frequency conversion processing: step 3 gained system shock response component is carried out FFT conversion, system shock response component is transformed to frequency domain, go to step 5; Return to step 1 simultaneously and carry out the processing of next pulse cycle, complete, go to step 5 to the time-frequency conversion of last pulse cycle completion system shock response component and stop;
The time-frequency conversion processing that step 5. transmits: read from ram cell and transmit and carry out FFT conversion, its result and do Complex multiplication processing with the frequency-region signal of the system shock response component of each pulse cycle of step 4 gained successively, obtain the frequency-region signal of each pulse cycle echo, its result goes to step 6 successively;
The output of step 6. inverse time frequency conversion process and echoed signal: the frequency-region signal to each pulse cycle echo of inputting successively carries out respectively IFFT conversion process, obtain the time-domain signal of each pulse cycle echo, the time-domain signal of the each pulse cycle echo of gained is exported by following situation:
The output of the little scene echoes signal of 6a.: if the time-frequency conversion that FPGA can completing steps 4 time-frequency conversion processing, step 5 transmit within each interpulse period (PRT) is processed and step 6 in inverse time conversion process flow process frequently, directly export in real time by D/A module as little scene echoes signal;
The output of 6b. large scene echoed signal: if FPGA cannot completing steps 4 time-frequency conversion processing within each interpulse period (PRT), the time-frequency conversion that transmits of step 5 process and step 6 in inverse time conversion process flow process frequently, as large scene echoed signal through high-speed interface (CPCI) control module and High-speed Interface Card, input successively datalogger storage, to whole scene echo signal processing, store complete;
The playback output of step 7. large scene: step 6b gained whole scene echoed signal is read in to D/A module successively by High-speed Interface Card and high-speed interface (CPCI) control module, D/A control module, by exporting after D/A module converts.
Echo simulator of the present invention is owing to only adopting monolithic FPGA+ monolithic DDR and a datalogger in agent structure; The consumption of FPGA and DDR is only 1/4th of background technology, not only significantly reduce the traffic between the sheet of signal, improved the reliability of system, datalogger adopts and effectively improves again the treatment capacity of echo simulator to echo data, in analogue echoes processing procedure, be able to by pipelining, realized the simulation of large scene echo and the playback of echo output, also improved analog rate to little scene echoes signal simultaneously, realized the real time modelling of little scene echoes; Adopt simulator of the present invention and 1024 × 1024 pixel scene radar returns of method simulation thereof, each echo-pulse generation time is 0.78ms, be less than pulse repeats (interval) time 1.0ms, met requirement of real-time, export only used time 4.096s of 4096 pulse echos of whole scene, compared with background technology, SAR echoed signal analog rate has been improved to 24%.Thereby the present invention has, and system architecture is simple, reliability is high, not only can effectively improve the little scene echoes signal of SAR analog rate, realize the real time modelling of little scene echoes, but also can be used for the feature such as simulation and the playback output of echoed signal to large scene echoed signal.
Accompanying drawing explanation
Fig. 1 is synthetic-aperture radar echo simulator structural representation of the present invention (block scheme);
Fig. 2 is synthetic-aperture radar analogue echoes process flow schematic diagram of the present invention (block scheme);
Fig. 3 is carried SAR actual ghosts image;
Fig. 4 is for adopting embodiment 1 echo simulator and analogue echoes disposal route gained SAR echo real time imagery figure.
Specific embodiments
Embodiment mono-: in the present embodiment synthetic-aperture radar echo simulator: FPGA signal processing chip adopts model field programmable gate array (FPGA) logical device that is XilinxXC6VLX240T by the reconfiguring of internal logic resource, composition comprises too net control module, ram cell, echo generation unit, D/A control module, memory control unit and high-speed interface (CPCI) control module; Synchronous DRAM (DDR) model is the WD2RE01GX809 of WINTEC company, and its capacity is 1GB, maximum operation frequency 200MHz; Power module is voltage chip PTH05010W and TPS51100; TPS51100 output 1.8V voltage is that DDR power supply, PTH05010W export three groups of voltages altogether, and wherein two groups of voltages of 2.5V and 1.0V are that the power supply of FPGA signal processing module, 3.3V are Network Interface Module and digital-to-analog conversion (D/A) module for power supply; TPS51100 is synchronous DRAM (DDR) power supply; Host computer adopts a Daepori to lead to PC, and CPU is Dual-Core E5400, and 2.70GHz inside saves as 2.0GB; Network Interface Module adopts an Ethernet chip that model is M88E1111; It is AD9780 digital-to-analog conversion (D/A) chip that digital-to-analog conversion (D/A) module adopts two models; High-speed Interface Card adopts CPCI interface, adopts 64 potential differences to divide high-speed interface to be directly connected with FPGA, every couple of about 132Mbps of differential signal line operating rate, and aggregate date rate is not less than 8.64Gbps; Datalogger model is HWA-RUR-4000, and memory capacity is 1TB, read or write speed 8GB/s.
Adopt the analogue echoes disposal route of above-mentioned echo simulator Technologies Against Synthetic Aperture Radar as follows:
Take analog image pixel size as 1024 × 1024 airborne haplopia High Resolution SAR Images are as example, as the target backscattering coefficient echo simulation of real scene, simulation system configuration parameter is as following table:
Table 1 simulation system configuration parameter
Writing of step 1. configuration parameter: host computer will transmit and Doppler's component deposits in the ram cell of FPGA signal processing chip, simulation system configuration parameter described in table 1 and SAR haplopia complex pattern data (RCS) are deposited in by memory control unit as scene objects backscattering coefficient in synchronous DRAM (DDR) by ethernet signal receiving element through Network Interface Module;
Determining of step 2. whole scene equivalence scattering coefficient: according to system configuration parameter, need to carry out altogether 4096 subpulse analogue echoes, first get first burst length, the each impact point backscattering coefficient of read-out system parameter and scene from DDR, then carries out according to the following steps:
Determining of the instantaneous oblique distance of 2a. and equidistant ring: according to the design's configuration parameter, distance is 1m × 1m to azimuth resolution, scene size is 1024m × 1024m, thereby have 1024 × 1024 impact points, according to each impact point and Texas tower coordinate, utilize 2 range formulas, calculate each impact point in scene instantaneous oblique distance to Texas tower, and be divided into 16384 equidistant rings according to instantaneous oblique distance;
2b. determines the equivalent scattering coefficient of each rang ring: the equivalent scattering coefficient that the impact point scattering coefficient in an equidistant ring is superposeed to determine to this rang ring, and successively the equivalent scattering coefficient of each rang ring is deposited in ram cell, determine to the 16384th rang ring equivalence scattering coefficient;
Determining of step 3. system shock response component: read Doppler's component from ram cell, and do Complex multiplication processing with step 2b gained whole scene equivalence scattering coefficient, obtain the system shock response component of this pulse, go to step 4;
Step 4. time-frequency conversion processing: step 3 gained system shock response component is carried out FFT conversion, system shock response component is transformed to frequency domain, go to step 5; Return to step 1 simultaneously and carry out the processing of next pulse cycle, complete, go to step 5 to the time-frequency conversion of the 4096th subpulse circulation completion system shock response component and stop;
The time-frequency conversion processing that step 5. transmits: read from ram cell and transmit and carry out FFT conversion, its result and do Complex multiplication processing with the frequency-region signal of the system shock response component of each pulse cycle of step 4 gained successively, obtain the frequency-region signal of each pulse cycle echo, its result goes to step 6 successively;
The output of step 6. inverse time frequency conversion process and the little scene echoes signal of step 6a.: the frequency-region signal to each pulse cycle echo of inputting successively carries out respectively IFFT conversion process, obtains the time-domain signal of each pulse cycle echo; The time-frequency conversion that process (step 4) because FPGA can complete time-frequency conversion within each interpulse period (PRT), transmits is processed (step 5) and (in step 6) inverse time conversion process flow process frequently, and each pulse cycle echo adopts the mode of step 6a directly by output in real time after D/A module converts as little scene echoes signal;
The echoed signal of the present embodiment output adopts Chip Scaling imaging algorithm to carry out imaging to it, and imaging results as shown in Figure 4; Comparison diagram 3 and Fig. 4, the scattering properties that the latter can fine sign actual ground scene, thus can verify the accuracy of SAR analogue echoes disposal route; On the used time, the system clock frequency of setting FPGA work is 200MHz, and the frequency of operation of DDR is set as 200MHz, 1024 × 1024 pixel scene radar returns of simulator real time modelling.Each echo-pulse generation time is 0.78ms, is less than (PRT) 1ms interpulse period, i.e. requirement of real time, exports only used time 4.096s of 4096 pulse echos of whole scene.
Embodiment bis-: the present embodiment synthetic-aperture radar echo simulator is identical with embodiment mono-.
The analogue echoes disposal route of Technologies Against Synthetic Aperture Radar is as follows:
Take analog image pixel size as 4096 × 4096 airborne haplopia High Resolution SAR Images are as example, as the target backscattering coefficient echo simulation of real scene, simulation system configuration parameter also with embodiment together; According to configuration parameter, distance is 1m × 1m to azimuth resolution, and scene size is 4096m × 4096m, thereby has 4096 × 4096 impact points.
Step 1 is identical with embodiment mono-to the processing of step 5;
The output of step 6. inverse time frequency conversion process and step 6b. large scene echoed signal: the time-frequency conversion that process (step 4) because FPGA cannot complete time-frequency conversion within each interpulse period (PRT), transmits is processed (step 5) and (in step 6) inverse time conversion process flow process frequently, adopt the mode of step 6b through high-speed interface (CPCI) control module as large scene echoed signal, pass through High-speed Interface Card, input successively datalogger storage, to whole scene echo signal processing, store complete;
The playback output of step 7. large scene echoed signal: by High-speed Interface Card, high-speed interface (CPCI) control module, D/A control module read in D/A module successively, by exporting after D/A module converts by step 6b gained whole scene echoed signal.
The present embodiment is on the used time, and when the system clock frequency of FPGA work is 200MHz, when the frequency of operation of DDR is set as 200MHz, each echo-pulse generation time is 2.6ms, exports 4096 pulse echo used time 10.7s of whole scene.
Claims (1)
1. the analogue echoes disposal route based on synthetic-aperture radar echo simulator, wherein simulator is including the inner FPGA signal processing chip containing Ethernet control module, ram cell, echo generation unit, D/A control module, memory control unit and high-speed interface control module, synchronous DRAM, host computer, Network Interface Module, D/A module, High-speed Interface Card and datalogger, power module; Ram cell in FPGA signal processing chip is connected with Ethernet control module, and echo generation unit is connected with ram cell, high-speed interface control module, memory control unit and D/A control module respectively; FPGA signal processing chip is connected with host computer by Ethernet control module and Network Interface Module, be connected with synchronous DRAM by memory control unit, be connected with High-speed Interface Card by high-speed interface control module, be connected with D/A module by D/A control module; High-speed Interface Card is connected with datalogger again simultaneously, and power module provides power supply to corresponding chip and module;
Analogue echoes disposal route comprises:
Writing of step 1. configuration parameter: host computer will transmit and Doppler's component deposits in the ram cell of FPGA signal processing chip, radar system parameter and SAR haplopia complex pattern data are deposited in synchronous DRAM by memory control unit as scene objects backscattering coefficient by ethernet signal receiving element through Network Interface Module;
Determining of step 2. whole scene equivalence scattering coefficient: first get first burst length, the each impact point backscattering coefficient of read-out system parameter and scene from synchronous DRAM, then carries out:
Determining of the instantaneous oblique distance of 2a. and equidistant ring: according to each impact point and Texas tower coordinate, utilize 2 range formulas, calculate each impact point in scene instantaneous oblique distance to Texas tower, and divide equidistant ring according to instantaneous oblique distance;
2b. determines the equivalent scattering coefficient of each rang ring: the impact point scattering coefficient in an equidistant ring is superposeed to determine to the equivalent scattering coefficient of this rang ring, and successively the equivalent scattering coefficient of each rang ring deposited in ram cell, determined to whole scene equivalence scattering coefficient;
Determining of step 3. system shock response component: read Doppler's component from ram cell, and do Complex multiplication processing with step 2b gained whole scene equivalence scattering coefficient, obtain the system shock response component of this pulse, go to step 4;
Step 4. time-frequency conversion processing: step 3 gained system shock response component is carried out FFT conversion, system shock response component is transformed to frequency domain, go to step 5; Return to step 1 simultaneously and carry out the processing of next pulse cycle, complete, go to step 5 to the time-frequency conversion of last pulse cycle completion system shock response component and stop;
The time-frequency conversion processing that step 5. transmits: read from ram cell and transmit and carry out FFT conversion, its result and do Complex multiplication processing with the frequency-region signal of the system shock response component of each pulse cycle of step 4 gained successively, obtain the frequency-region signal of each pulse cycle echo, its result goes to step 6 successively;
The output of step 6. inverse time frequency conversion process and echoed signal: the frequency-region signal to each pulse cycle echo of inputting successively carries out respectively IFFT conversion process, obtain the time-domain signal of each pulse cycle echo, the time-domain signal of the each pulse cycle echo of gained is exported by following situation:
The output of the little scene echoes signal of 6a.: if the time-frequency conversion that FPGA can completing steps 4 time-frequency conversion processing, step 5 transmit within each interpulse period is processed and step 6 in inverse time conversion process flow process frequently, directly export in real time by D/A module as little scene echoes signal;
The output of 6b. large scene echoed signal: if FPGA cannot completing steps 4 time-frequency conversion processing within each interpulse period, the time-frequency conversion that transmits of step 5 process and step 6 in inverse time conversion process flow process frequently, as large scene echoed signal through high-speed interface control module and High-speed Interface Card, input successively datalogger storage, to whole scene echo signal processing, store complete;
The playback output of step 7. large scene: step 6b gained whole scene echoed signal is read in to D/A module successively by High-speed Interface Card and high-speed interface control module, D/A control module, by exporting after D/A module converts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210353283.9A CN102866390B (en) | 2012-09-21 | 2012-09-21 | Synthetic aperture radar echo simulator and echo simulation processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210353283.9A CN102866390B (en) | 2012-09-21 | 2012-09-21 | Synthetic aperture radar echo simulator and echo simulation processing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102866390A CN102866390A (en) | 2013-01-09 |
| CN102866390B true CN102866390B (en) | 2014-06-18 |
Family
ID=47445373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210353283.9A Expired - Fee Related CN102866390B (en) | 2012-09-21 | 2012-09-21 | Synthetic aperture radar echo simulator and echo simulation processing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102866390B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104076341B (en) * | 2014-07-04 | 2017-01-11 | 西安电子科技大学 | Radar echo real-time simulation method based on FPGA and DSP |
| CN105955899B (en) * | 2016-04-22 | 2019-01-11 | 西安电子科技大学 | Radar digital signal processing device based on all solid state semicondctor storage array |
| CN107728120A (en) * | 2017-01-23 | 2018-02-23 | 中国船舶工业系统工程研究院 | A kind of analogy method of marine radar target echo |
| CN108169727B (en) * | 2018-01-03 | 2019-12-27 | 电子科技大学 | Moving target radar scattering cross section measuring method based on FPGA |
| CN108982051A (en) * | 2018-08-29 | 2018-12-11 | 河海大学 | A kind of impact echo detection system and method based on smart phone |
| CN112631977B (en) * | 2020-12-17 | 2022-12-30 | 中国科学院光电技术研究所 | Dynamic multi-target electric simulation system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3600826B2 (en) * | 2002-08-29 | 2004-12-15 | 東芝電波プロダクツ株式会社 | Inverse synthetic aperture radar image simulator |
| CN101782647B (en) * | 2010-02-09 | 2012-11-28 | 南京大学 | Dynamic radar signal simulator |
-
2012
- 2012-09-21 CN CN201210353283.9A patent/CN102866390B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN102866390A (en) | 2013-01-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102866390B (en) | Synthetic aperture radar echo simulator and echo simulation processing method | |
| CN108051786A (en) | A kind of broadband target simulator verification platform and verification method | |
| CN108958638A (en) | Ultrahigh speed SAR data recorder and data record method | |
| CN101968539B (en) | Multifunctional digital signal processor for skyborne or spaceborne radar altitude gauge | |
| CN104881666B (en) | A kind of real-time bianry image connected component labeling implementation method based on FPGA | |
| CN103412284B (en) | Matrix transposition method in SAR imaging system based on DSP chip | |
| CN101576619B (en) | UWB radar signal simulator based on FPGA and UWB radar signal generation method | |
| CN101441271A (en) | SAR real time imaging processing device based on GPU | |
| CN104216324B (en) | Related methods of synthetic aperture radar task management controller | |
| CN103176068A (en) | Bus-based test module | |
| CN109613536B (en) | Satellite-borne SAR real-time processing device and method | |
| CN105137428A (en) | Dechirp signal polar format imaging algorithm FPGA (Field Programmable Gate Array) realization method | |
| CN105676197A (en) | Array radar echo simulator and simulation method thereof | |
| CN104535980B (en) | Five-dimensional dynamic stereoscopic clutter map implementation method based on DDR3-SDRAM | |
| CN107066670A (en) | A kind of active power distribution network real-time simulator A/D interface design method based on FPGA | |
| CN101025625A (en) | DSP based embedded intelligent controller | |
| CN202661624U (en) | Signal processor of laser Doppler radar based on FPGA | |
| CN103389413A (en) | Real-time statistical method for frequency spectrum histogram | |
| Wang et al. | Video SAR high-speed processing technology based on FPGA | |
| CN204679631U (en) | A kind of imaging radar echo simulator | |
| CN102353940A (en) | Pulse compression optimization method based on field programmable gate array (FPGA) | |
| CN201909847U (en) | Double-channel digital signal acquisition device on basis of VXI (VME <Virtual Machine Enviroment> bus Extension for Instrumentation) interface | |
| CN201497807U (en) | UWB radar signal simulator based on FPGA | |
| CN107561948A (en) | Processing unit system for flight simulation emulation testing | |
| CN110532215B (en) | High-speed signal acquisition and storage system of unmanned aerial vehicle-mounted polarization interference synthetic aperture radar |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140618 Termination date: 20160921 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |