CN202661624U - Signal processor of laser Doppler radar based on FPGA - Google Patents

Abstract

The utility model discloses a signal processor of a laser Doppler radar based on an FPGA (field programmable gate array), and relates to the field of radar signal processing. The signal processor comprises an ADC (analog to digital converter) sampling unit, a storage unit and an FPGA processing unit, wherein the FPGA processing unit comprises an ADC configuration module, a storage interface module, a sampled data receiving module, a data input module, an intermediate frequency wave trap module, a diploid down sampling module, an FFT (fast Fourier transform) module, a pulse accumulating module, a peak extracting and Doppler frequency output module and a control module. After electrification, the FPGA configures an ADC and waits for an external trigger signal; after the signal is effective, the FPGA begins receiving data sampled by the ADC; and the sampled data are all stored in the storage unit for caching through the FPGA, and then are read into the FPGA from the storage unit to be processed. By using the signal processor, the characteristics of the FPGA are adequately utilized; the processing speed is high; the structure is simple; the problems of intermediate frequency interference, large data size and the like when the laser Doppler radar is used for speed measurement are solved, thereby being beneficial to control on the cost and the complexity of the laser Doppler radar.

Description

Laser Doppler radar signal processor based on FPGA

Technical field

The utility model relates to radar signal processing field, is specifically related to a kind of signal processor of the laser Doppler radar based on FPGA.

Background technology

Radar Doppler is to utilize the radar of because of the Doppler effect of caused by relative motion target being surveyed between radar and target, and what laser Doppler radar was launched is laser signal.Compare with microwave radar, the characteristics such as it is shorter that the laser Doppler radar radar has operation wavelength, and Angle of beam divergence is little have high angle resoluting ability, distance resolution and Doppler range rate measurement resolution.Utilize the accurately movement velocity of measurement target object of laser Doppler radar: with Doppler shift, from echo, extract Doppler frequency and can calculate target velocity after pulse signal of radar emission, signal return from target.Can extract real-time and accurately the performance that Doppler frequency depends on radar signal processor.

The characteristics that the laser Doppler radar signal is processed are big data quantities, because sample frequency is often higher, and data sudden very strong, static memory is difficult to realize data storage so at a high speed, although and dynamic storage can be realized using complicated.Therefore how preserving in real time the echo data with such characteristics is that the laser Doppler radar signal is processed a problem that faces.

Measure the occasion of negative velocity for needs, i.e. target and radar reverse direction motion, the Doppler frequency of this moment is negative value.The photodetector of radar front end can't obtain the output of negative frequency signal, therefore transmitted wave need to add an IF-FRE, echo is not actually Doppler frequency and adds IF-FRE with adding the frequency values that obtains after the local oscillation signal mixing of intermediate frequency like this, negative Doppler frequency can be moved the positive frequency place.Because utilizing emitted light leaks into the impact of receiving light path etc., meeting is so that the signal after the demodulation contains middle frequency interference signal, the amplitude of this IF-FRE is much larger than the amplitude at Doppler frequency place, so that dynamic range of signals is very large, is unfavorable for follow-up processing and saves calculation resources.This is that the laser Doppler radar signal is processed another problem that faces.

Speed dynamic range, rate accuracy and the real-time that laser Doppler radar can be measured is its important indicator, and the speed dynamic range that can measure is larger, and the usable range of expression radar is wider; Rate accuracy is higher, and its result is more reliable; The speed refresh rate is higher, and radar can draw the result that tests the speed more rapidly, and the range rate error that the while acceleration brings is less.Large speed dynamic range means large Doppler frequency scope, also just means that the echoed signal after the demodulation has large bandwidth, and this need to use the analog to digital converter (ADC) of higher sample frequency, and is many thereby number of data points becomes; Rate accuracy is high, represents the just larger bit wide of needs of each data point.Therefore, what the raising of these two indexs brought is the increase of data volume, and requirement of real-time needs to process a large amount of echo datas in the short time.This is that the laser Doppler radar signal is processed the 3rd problem that faces.

The operating distance of radar represents radar can be surveyed the target in how many distance ranges.In the situation that front end hardware condition and surrounding environment are constant, target range is far away, and useful signal intensity is more weak, and signal to noise ratio (S/N ratio) is lower.Therefore how from afar detecting useful signal in the echo of target is that the laser Doppler radar signal is processed the four problems that faces.

Along with the development of computing machine and large scale integrated circuit technology, Digital Signal Processing becomes the core of Radar Signal Processing.The echo that laser Doppler radar receives utilizes ADC to analog signal sampling after nursing one's health through preliminary mimic channel, converts thereof into digital signal, then utilizes the method for digital signal processing to obtain required target information.

In the digital signal processing hardware of radar was realized, prior art mainly was to adopt digital signal processor (DSP), is responsible for all calculation tasks such as pre-service, FFT and frequency abstraction.The deficiencies in the prior art are, in the certain situation of clock frequency, the arithmetic speed of DSP mainly depends on the number of multiplicaton addition unit, and its multiplicaton addition unit number is extremely limited, and this has limited the speed of DSP when filtering etc. needs a large amount of multiply-add operation.For example the TMS320C64x of TI series fixed DSP has two multipliers, can carry out simultaneously 4 16 * 16bit computings a clock period.Be the FIR wave filter that a DSP of 800MHz realizes 100 coefficients with this series clock speed, its filtering processing speed only is 32MHz.As previously mentioned, the data volume of laser Doppler radar is large, and requirement of real-time is high, can only utilize so multi-DSP to carry out parallel processing, and complexity and power consumption that this has increased system have reduced stability, also are unfavorable for controlling cost.

Therefore, laser Doppler radar needs the signal processor that a kind of speed is fast, precision is high, simple in structure.

Summary of the invention

Process the problem that faces and all deficiencies of current techniques for the laser Doppler radar signal of above analysis, the purpose of this utility model provides a kind of signal processor of the laser Doppler radar based on field programmable gate array (FPGA).The technical problems to be solved in the utility model is: the buffer memory of Radar Signal Processing high speed, mass data and process in real time problem, the intermediate frequency interference problem of laser Doppler radar and the low signal-to-noise ratio problem of long-range detection.The utility model takes full advantage of the characteristics of FPGA, cooperates ADC and static memory (SRAM), finishes in real time whole work that the laser Doppler radar signal is processed.

For this reason, the utility model provides a kind of signal processor of the laser Doppler radar of realizing with FPGA, and referring to Fig. 1, the structure of this signal processor comprises ADC sampling unit, storage unit and FPGA processing unit.

Described ADC sampling unit is made of a slice ADC, and model is the ADC12D1000 of National Semiconductor, and the simulating signal of input is carried out analog to digital conversion, and output digit signals is to the FPGA processing unit; This model ADC has ten configuration pin: PDI, PDQ, ECE, DES, TPM, NDM, FSR, CALDLY, CAL, DDRPHASE, these ten pins all are connected to FPGA, configured by configuration bus by it, ADC is configured to two passages samples respectively, export shunt pattern, full scale input, upper electric delay 17ms calibration, clock than the data delay semiperiod;

Described storage unit is made of two parallel SRAM, and the SRAM model is the CY7C1034DV33 of Cypress company; This model SRAM has three controls pin: CE, WE, OE, and these three pins are connected to FPGA and are controlled by the SRAM control signal by it;

Described FPGA processing unit is made of a slice FPGA, adopts the Virtex-II series of Xilinx company, and concrete model is XC2V3000; The FPGA processing unit comprises following ten modules:

The ADC configuration module, output configuration end signal is to control module, and the output configuration bus is connected to the ADC sampling unit;

Store interface module is input as data, address, the SRAM control signal of sampled data receiver module and data input module, and output data, address, SRAM control signal are to storage unit;

The sampled data receiver module is input as signal after external sampling trigger pip, the ADC sampling and the reset signal of control module, is output as buffering write data, address, SRAM control signal and sampling end signal;

Data input module is input as the buffer memory sense data with reset signal, store interface module of enabling of control module, is output as address, SRAM control signal, data useful signal and serial data;

Intermediate frequency trap module is input as the reset signal of control module, data useful signal and the serial data of data input module, is output as data behind data useful signal and the trap;

2 times of down-sampled modules are input as data behind the data useful signal of reset signal, intermediate frequency trap module of control module and the trap, are output as data useful signal and down-sampled rear data;

The FFT module is input as data useful signal and the down-sampled rear data of the reset signal of control module, 2 times of down-sampled modules, is output as data useful signal and frequency spectrum data;

Pulse accumulation module is input as data useful signal and the frequency spectrum data of the reset signal of control module and cumulative frequency control signal, FFT module, is output as frequency spectrum data;

Peak extraction and Doppler frequency are calculated module, are input as the frequency spectrum data of the enabling of control module, reset signal and pulse accumulation module;

Control module is input as the configuration end signal of ADC configuration module and the sampling end signal of sampled data receiver module, is output as reset signal, enable signal and cumulative frequency control signal;

The annexation of inner each module of FPGA is: the ADC configuration module is connected to control module by the configuration end signal; The sampled data receiver module is connected with control module with reset signal by the sampling end signal, is connected with store interface module by buffering write data, address and SRAM control signal; Store interface module is connected with data input module with the SRAM control signal by buffer memory sense data, address; Data input module is connected with control module with reset signal by enabling, and is connected with intermediate frequency trap module with serial data by the data useful signal; Intermediate frequency trap module is connected with control module by reset signal, is connected data with trap by the data useful signal and is connected with 2 times of down-sampled modules; 2 times of down-sampled modules are connected with control module by reset signal, by the data useful signal be connected rear data and be connected with the FFT module; The FFT module is connected with control module by reset signal, is connected with pulse accumulation module with frequency spectrum data by the data useful signal; Pulse accumulation module is connected with control module with the cumulative frequency control signal by reset signal, is connected module with peak extraction with Doppler frequency by frequency spectrum data and is connected; Peak extraction is connected module and is connected with control module with enable signal by resetting with Doppler frequency;

External analog signal is connected to the analog input pin of the contained ADC of ADC sampling unit, the configuration bus of the I/O pin output of FPGA is connected to each configuration pin of ADC, the digital output pin of ADC is connected to the I/O pin of FPGA, the external sampling trigger pip is connected to the I/O pin of FPGA, the address of the I/O pin output of FPGA and the address pin that the SRAM control signal is connected respectively to the contained SRAM of storage unit and each control pin, the data of the I/O pin input and output of FPGA are connected to the data pin of SRAM.

The signal processor of the utility model provides this laser Doppler radar of realizing with FPGA, referring to Fig. 2, the flow process of its work is:

The a.ADC configuration module is configured ADC, and this step forwards step b to after finishing.

B. outer triggering signal effectively after, the single pulse signal of sampled data receiver module buffer memory ADC sampling unit, and with the SRAM in its write storage unit.After having stored a plurality of pulses of predetermined number, the sampled data receiver module sends the sampling end signal to control module.This step forwards step c to after finishing.

C. control module receive the sampling end signal after the log-on data load module, from storage unit, read the monopulse echo data, data are passed through intermediate frequency trap module and 2 times of down-sampled modules successively, carry out respectively trap and 2 times of down-sampled processing.This step forwards steps d to after finishing.

D.2 doubly the data of down-sampled module output are input to the FFT module, carry out Fourier transform, obtain the frequency spectrum of monopulse echo.This step forwards step e to after finishing.

E. after monopulse FFT finished, pulse accumulation module started, and frequency spectrum is accumulated among the FIFO of this module.This step forwards step f to after finishing.

F. the accumulation of monopulse echo complete after, judge by control module whether current cumulative frequency reaches designated value, when not reaching designated value, forward step c to; If reach designated value, forward step g to.

G. peak extraction and Doppler frequency are calculated the module startup, read the multiple-pulse accumulation frequency spectrum of storing among the FIFO of pulse accumulation module, find out the position of peak point in sequence of frequency spectrum, then calculate Doppler frequency, and the signal processing finishes.

The advantage of this radar signal processor is:

(1) takes full advantage of the large I/O bandwidth of FPGA and the characteristics with high speed Block RAM in a large amount of sheets, make up the interior FIFO of sheet the data of ADC are carried out buffer memory.Then adopt the multi-disc high-speed SRAM, multi-site data is parallel, with the data cached SRAM that deposits in of FIFO in the sheet.Solved the echo data storage problem of high sampling rate, high sudden, big data quantity, and realize simple, flexible design, reliability is high.

(2) with the trapper module, the amplitude of frequency interference signal makes it suitable with the useful signal amplitude in can significantly suppressing, thereby reduces the dynamic range of data.In the situation that data bit width is certain in the actual treatment, can prevents like this that the useful signal amplitude is too small and reduce accuracy of detection.

(3) utilize down-sampled and suitably reduce data volume in the situation that guarantee precision.The minimizing of data volume has brought the processing time minimizing, can reduce the use of internal storage space simultaneously.

(4) with frequency spectrum accumulation module, so that this processor can be processed the very little distant object echoed signal of signal to noise ratio (S/N ratio).

(5) take full advantage of the inner abundant register resources of FPGA, design flow waterline.When data process data input module, intermediate frequency trap module and 2 times of down-sampled modules, adopt pipeline system, therefore 2 times of down-sampled modules can begin to export the data after down-sampled after through a small amount of the delay, have reduced the use of processing time and storage inside.

(6) the required constant multiplier of wave filter of intermediate frequency trap module and 2 times of down-sampled modules utilizes the Slice of FPGA inside to realize, speed is than fast with embedded multiplier.Each multiplier of wave filter is Parallel Implementation, can export a filtering data in one-period, has accelerated processing speed.The filter coefficient of 2 times of down-sampled modules is designed to have symmetry, can multiplexing multiplier, reduced half number of multipliers.The structure of wave filter has improved maximum operational speed through transposition.

Description of drawings

Fig. 1 is the signal processor general structure block diagram that the utility model proposes.

Fig. 2 is the signal processor workflow diagram that the utility model proposes, and wherein M represents cumulative frequency.

Fig. 3 is trapper structural drawing, wherein f _iBe the intermediate frequency interfering frequency.

Fig. 4 is the structural drawing of down-sampled required low-pass filter.

Embodiment

The velocity range that the laser Doppler radar that the utility model is used for need to be measured is-20m/s ~ 100m/s, and negative speed represents that target and radar are away from, the Doppler frequency f that this velocity range is corresponding with the Emission Lasers of 1550nm wavelength _dFor-25.8MHz ~ 129MHz, IF-FRE adopts f _i=62.5MHz, the frequency range of echoed signal becomes 36.7MHz ~ 191.5MHz so.Sample frequency according to sampling thheorem ADC is decided to be 500MHz, and the sampling time is 32.768us, and so once sampling obtains N=16384 point data.The transponder pulse repetition is 10KHz, i.e. twice recurrent intervals 100 μ s.

The below introduces implementation of the present utility model in detail according to specific targets set forth above.

(1) ADC sampling unit.Be to realize the high-speed, high precision sampling, the utility model adopts the ADC12D1000 type ADC of National Semiconductor's (now having incorporated Texas Instruments into), and this ADC is 12bit, and high sampling rate is 2GSPS.The utility model is configured to sample frequency 500MHz, and with the parallel 12bit data of frequency output two-way of 250MHz, the output sampling clock is 125MHz.

(2) storage unit.SRAM adopts the CY7C1034DV33 of Cypress company, and this model SRAM capacity is 256K * 24bit, and the fastest read or write speed reaches 125MHz.Storage unit of the present utility model contains 2 SRAM and carries out parallel processing, and the I/O bandwidth of 48bit is provided, and write clock is 75MHz, two SRAM multipotency storage 64 * 16384 12bit data, the i.e. data of 64 monopulses.

(3) FPGA processing unit.The utility model adopts the Virtex-II Series FPGA of Xilinx company, and model is XC2V3000.This model FPGA has 14336 Slice, 96 embedded multipliers, and 96 embedded RAM of 18Kbit can satisfy the high speed mass data processing and use.

(4) sampled data receiver module.The output interface bandwidth of aforementioned ADC is 24bit, and the output data frequency is 250MHz, and the input interface of this module utilizes the synchronously 125MHz sampling clock of output of ADC, is designed to the rise and fall of clock along simultaneously operation, can satisfy the data rate of ADC.After receiving sampled data, module is once gone here and there and is changed, and the 24bit data are converted to the 48bit data, and the capacity of being written to is among the FIFO of 2048 * 48bit, and the write clock of this FIFO is 125MHz.As previously mentioned, the interface bandwidth of FIFO and sheet external memory unit (two SRAM are parallel) is 48bit, and readout clock is 75MHz.The required maximum buffer of 16384 12bit data that writes once sampling is 6553.6 * 12bit, so the capacity of FIFO is enough.

(5) intermediate frequency trap module.For the excessive problem of velocity radar intermediate frequency interference magnitude, the utility model adds the intermediate frequency trapper in treatment scheme, intermediate frequency is carried out trap, and the amplitude that makes its amplitude and Doppler frequency place quite or less, so that the dynamic range of echo data reduces greatly, be beneficial to the detection useful signal.

Trapper extracts initial phase and the range parameter that intermediate frequency disturbs from signal, then utilize the newly-generated signal of these two parameter renegotiation, this signal is the same with the intermediate frequency interference with initial phase in the amplitude at IF-FRE place, deducts this signal of generation from original signal, realizes trap.Its structural drawing as shown in Figure 3.

(6) 2 times of down-sampled modules comprise shift frequency, low-pass filtering and extraction.As previously mentioned, the data volume that the ADC single pulse sampling obtains is 16384 points, and data volume is constant behind the trap.13684 data are directly carried out the FFT conversion, and the required time, resource long, that take was many, therefore in the situation that the assurance precision is carried out 2 times of down-sampled processing to the data behind the trap.

According to down-sampled theory, 2 times of down-sampled meetings make 2 times of video stretchings, directly down-sampled meeting makes its spectral range become 73.4MHz ~ 383MHz to this signal, and the signal highest frequency of sampling thheorem restriction is 250MHz, therefore directly carries out down-sampled meeting so that highest frequency surpasses the restriction of sampling thheorem and spectral aliasing occurs.Solution is the single-side belt of the only number of winning the confidence, because the symmetry of real signal frequency spectrum, its single-side belt has kept its whole spectrum informations.The frequency range of preparing to keep is 20MHz ~ 200MHz, and this frequency range has comprised the frequency of useful signal fully.Signal at first carries out shift frequency by frequency shifter behind the trap, with signal times behind the trap with complex frequency signal cos (2 π f ₁T)-jsin (2 π f ₁T), f ₁=110MHz, the frequency spectrum integral body of echoed signal 110MHz that moves to left so, the spectral range of intending keeping becomes-90MHz ~ 90MHz.Then be-low-pass filter of 90MHz ~ 90MHz that the signal of gained is the signal at former 20MHz ~ 200MHz place by passband.Notice that present signal becomes 16284 plural numbers by 16284 original real numbers.At last this complex data is carried out 2 times of extractions, can obtain 8192 data, operand becomes original half.

Can utilize easily multiplier and inner Block RAM to consist of frequency shifter among the FPGA.BlockRAM is configured to the ROM form, wherein has the sample value of shift frequency frequency signal.Low-pass filter structure is designed to 32 FIR wave filters as shown in Figure 4, and coefficient has symmetry, and multiplier of the common use of identical coefficient has been saved resource.Wave filter realizes with transpose configuration, and this can reduce required foundation the retention time when using FPGA to realize, be beneficial to the raising maximum operational speed.The coefficient of considering wave filter is constant, uses Slice structure multiplier rather than embedded multiplier, and such benefit is that realization speed is fast, and has saved the resource of embedded multiplier.Because the FIR wave filter needs a large amount of multipliers, if use embedded multiplier, only have the FPGA of a few high-end model just can provide so many quantity, this obviously is unfavorable for cost control, and easily causes the waste of a large amount of other resources.And utilize distributed implementation, and do not take embedded multiplier, also can take full advantage of remaining logical resource.Compare with DSP, FPGA can realize various structures according to actual needs neatly by the deviser, uses inner logical resource, can the distributed multiplier of Parallel Implementation, so wave filter can parallel processing, has accelerated processing speed.

(7) FFT module.This module is carried out FFT to the data after down-sampled, obtains frequency spectrum.Because passed through before the FFT down-sampledly, data volume reduces, to the Speed Reduction of FFT requirement, FFT module of the present utility model be base 2 realizations, uses completely serial structure, namely only has a butterfly processing element.This mode is than parallel mode simplicity of design, and it is convenient to realize, maintainable strong, the utilization of resources is also less.Do not consider the cycle of read-write cache etc., this processor realizes that 8192 FFT need 4096 * 13=53248 cycles, needs times spent 1064.96 μ s when clock frequency is 50MHz.The Block RAM aboundresources of FPGA inside can provide for FFT the buffer memory of intermediate data.

(8) pulse accumulation module.The echoed signal that pulse of the every emission of radar obtains is a monopulse echo, and radar is when detection is remote, and a little less than the echoed signal that obtains, and noise is relatively strong, so the signal to noise ratio (S/N ratio) of monopulse is very low, needs to adopt multiple-pulse accumulation mode improve signal to noise ratio (S/N ratio).Pulse accumulation is divided into the coherent pulse accumulation and incoherent pulses are accumulated, coherent accumulation to the raising of signal to noise ratio (S/N ratio) as shown in the formula shown in (1)

SNR _Mcoherent=M×SNR _s （1）

In the formula, SNR _McoherentBe the signal to noise ratio (S/N ratio) behind the coherent accumulation, M is the pile-up pulse number, SNR _sBe the monopulse signal to noise ratio (S/N ratio).The coherent pulse accumulative effect is better, but requires the phase place of pulse to have correlativity, is difficult to accomplish in reality.The utility model adopts non-coherent accumulation, non-coherent accumulation to the raising of signal to noise ratio (S/N ratio) as shown in the formula shown in (2)

${\mathrm{SNR}}_{\mathrm{Mnoncoherent}}=\sqrt{M}\×{\mathrm{SNR}}_s---\left(2\right)$

In the formula, SNR _MnoncoherentBe the signal to noise ratio (S/N ratio) after the non-coherent accumulation.Non-coherent accumulation does not require that impulse phase has correlativity, and the monopulse frequency spectrum data of FFT module output is directly inputted the accumulation module, is added among the FIFO.Speed refresh rate and monopulse according to system requirements are processed the required time, can calculate the number of times of maximum accumulations.As seen, the processing speed of monopulse, namely the speed of the down-sampled and FFT of intermediate frequency trap, 2 times is directly relevant with the pulse number that can accumulate.If the monopulse processing speed is slow, cumulative frequency is few so, and signal to noise ratio (S/N ratio) is low, even signal is buried in the noise fully, can't detect Doppler frequency.The monopulse processing speed is faster, and the number of times that can accumulate at system's in setting time is just more, and the signal to noise ratio (S/N ratio) that obtains is just larger, more easily detects signal.

(9) peak extraction and calculating Doppler frequency module.After accumulating certain number of times, obtain final frequency spectrum, need to detect the sequence number corresponding to maximal value of spectrum amplitude.If corresponding n the data point in spectrum peak, and 0≤n＜N/2 is arranged.If n, illustrates that the spectrum peak is at the positive frequency place less than N/4; If n, illustrates that the spectrum peak at the negative frequency place, need to be converted to negative value with it greater than N/4.Consider that 2 times down-sampledly have video stretching and the frequently 110MHz that moves to left, the spectrum peak place frequency f of so former echoed signal _MaxAs the formula (3)

$f_{\max }=\left\{\begin{array}{cc}\frac{n}{N}\&times;500\mathrm{MHz}+110\mathrm{MHz},& 0\&le;n<N/4\\ \frac{n}{N}\&times;500\mathrm{MHz}-250\mathrm{MHz}+110\mathrm{MHz},& N/4\&le;n<N/2\end{array}\right.---\left(3\right)$

Consider transmitted wave with IF-FRE, so actual Doppler frequency fd should be

f _d=f _max-62.5MHz （4）

Utilize the multiplier of FPGA inside and totalizer can calculate Doppler frequency according to formula (3) (4).

The situation that top speed and resource were used when FPGA of the present utility model unit was realized at the XC2V3000 of Xilinx company model FPGA is as shown in table 1.Maximum clock frequency in the attention table is the frequency of whole system, and the sampled data receiver module of its front end still can adopt the clock that is higher than this frequency that data are received and dispatched.

Speed and resource after table 1 FPGA realizes are used

The twice emitting recurrent intervals 100 μ s of laser Doppler radar, if carry out M accumulation, all to store the required time of SRAM into be M * 100 μ s to M sampled data so.When XC2V3000 is 50MHz at system clock frequency, 16384: 12 bit data are read in and carry out the intermediate frequency trap and 2 times of down-sampled required times are 327.7 μ s, then carrying out the required time of FFT is 1065.0 μ s, then once accumulating the required time is 163.8 μ s, thus monopulse to process required T.T. be 1556.5 μ s.Suppose that velocity radar needs the speed refresh rate of 10Hz, the processing time of a speed data permission is 100ms so, and the cumulative frequency that can realize at most can be obtained by following formula

M×100μs+M×1556.5μs＜100ms (5)

Obtained by formula (5) and can accumulate at most 60 times.The utility model cumulative frequency is decided to be 50 times, and processing so required T.T. is 82.8ms.

In sum, this that the utility model proposes is simple based on the laser Doppler radar signal processor structure of FPGA, and processing speed is fast, satisfies the signal processing demands of laser Doppler radar.

Claims (1)

1. the laser Doppler radar signal processor based on FPGA comprises ADC sampling unit, storage unit and FPGA processing unit; It is characterized in that:

Described ADC sampling unit is made of a slice analog to digital converter ADC, and model is the ADC12D1000 of National Semiconductor, and the simulating signal of input is carried out analog to digital conversion, and output digit signals is to the FPGA processing unit; This model ADC has ten configuration pin: PDI, PDQ, ECE, DES, TPM, NDM, FSR, CALDLY, CAL, DDRPHASE, these ten pins all are connected to FPGA, configured by configuration bus by it, ADC is configured to two passages samples respectively, export shunt pattern, full scale input, upper electric delay 17ms calibration, clock than the data delay semiperiod;

Described storage unit is made of two parallel static memory SRAM, and the SRAM model is the CY7C1034DV33 of Cypress company; This model SRAM has three controls pin: CE, WE, OE, and these three pins are connected to FPGA and are controlled by the SRAM control signal by it;

Described FPGA processing unit is made of a slice on-site programmable gate array FPGA, adopts the Virtex-II series of Xilinx company, and concrete model is XC2V3000; The FPGA processing unit comprises following ten modules:

The ADC configuration module, output configuration end signal is to control module, and the output configuration bus is connected to the ADC sampling unit;

Store interface module is input as data, address, the SRAM control signal of sampled data receiver module and data input module, and output data, address, SRAM control signal are to storage unit;

The sampled data receiver module is input as signal after external sampling trigger pip, the ADC sampling and the reset signal of control module, is output as buffering write data, address, SRAM control signal and sampling end signal;

Data input module is input as the buffer memory sense data with reset signal, store interface module of enabling of control module, is output as address, SRAM control signal, data useful signal and serial data;

Intermediate frequency trap module is input as the reset signal of control module, data useful signal and the serial data of data input module, is output as data behind data useful signal and the trap;

2 times of down-sampled modules are input as data behind the data useful signal of reset signal, intermediate frequency trap module of control module and the trap, are output as data useful signal and down-sampled rear data;

The FFT module is input as data useful signal and the down-sampled rear data of the reset signal of control module, 2 times of down-sampled modules, is output as data useful signal and frequency spectrum data;

Pulse accumulation module is input as data useful signal and the frequency spectrum data of the reset signal of control module and cumulative frequency control signal, FFT module, is output as frequency spectrum data;

Peak extraction and Doppler frequency are calculated module, are input as the frequency spectrum data of the enabling of control module, reset signal and pulse accumulation module;

Control module is input as the configuration end signal of ADC configuration module and the sampling end signal of sampled data receiver module, is output as reset signal, enable signal and cumulative frequency control signal;

The annexation of inner each module of FPGA is: the ADC configuration module is connected to control module by the configuration end signal; The sampled data receiver module is connected with control module with reset signal by the sampling end signal, is connected with store interface module by buffering write data, address and SRAM control signal; Store interface module is connected with data input module with the SRAM control signal by buffer memory sense data, address; Data input module is connected with control module with reset signal by enabling, and is connected with intermediate frequency trap module with serial data by the data useful signal; Intermediate frequency trap module is connected with control module by reset signal, is connected data with trap by the data useful signal and is connected with 2 times of down-sampled modules; 2 times of down-sampled modules are connected with control module by reset signal, by the data useful signal be connected rear data and be connected with the FFT module; The FFT module is connected with control module by reset signal, is connected with pulse accumulation module with frequency spectrum data by the data useful signal; Pulse accumulation module is connected with control module with the cumulative frequency control signal by reset signal, is connected module with peak extraction with Doppler frequency by frequency spectrum data and is connected; Peak extraction is connected module and is connected with control module with enable signal by resetting with Doppler frequency;

External analog signal is connected to the analog input pin of the contained ADC of ADC sampling unit, the configuration bus of the I/O pin output of FPGA is connected to each configuration pin of ADC, the digital output pin of ADC is connected to the I/O pin of FPGA, the external sampling trigger pip is connected to the I/O pin of FPGA, the address of the I/O pin output of FPGA and the address pin that the SRAM control signal is connected respectively to the contained SRAM of storage unit and each control pin, the data of the I/O pin input and output of FPGA are connected to the data pin of SRAM.

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