CN108614266A - A kind of implementation method of the FPGA of video SAR high-speed processing technologies - Google Patents
A kind of implementation method of the FPGA of video SAR high-speed processing technologies Download PDFInfo
- Publication number
- CN108614266A CN108614266A CN201810203581.7A CN201810203581A CN108614266A CN 108614266 A CN108614266 A CN 108614266A CN 201810203581 A CN201810203581 A CN 201810203581A CN 108614266 A CN108614266 A CN 108614266A
- Authority
- CN
- China
- Prior art keywords
- data
- pulse
- processing
- fpga
- distance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9021—SAR image post-processing techniques
- G01S13/9029—SAR image post-processing techniques specially adapted for moving target detection within a single SAR image or within multiple SAR images taken at the same time
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9004—SAR image acquisition techniques
Landscapes
- Engineering & Computer Science (AREA)
- Remote Sensing (AREA)
- Radar, Positioning & Navigation (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Radar Systems Or Details Thereof (AREA)
Abstract
The invention discloses a kind of implementation methods of the FPGA of video SAR high-speed processing technologies, belong to radar imaging technology field and digital signal processing technique field.This method comprises the following steps：1, SAR raw radar datas and parameter profit are sent to fpga chip by host computer and gigabit Ethernet；2, by echo data to there is overlap mode to carry out frame extraction, frame per second is improved by the way that Duplication is arranged；And calculate required parameter in each frame data PFA processing procedures；3, multiple-pulse is realized based on change of scale principle and row distance is to processing, improves distance to processing speed；4, by distance into the data transposition write-in DDR handled；5, orientation multiple-pulse parallel processing is realized based on high-precision SINC interpolation.This method can realize video SAR high speed processings, realize the imaging speed more than 5 frames/second, lay the foundation for the real-time of video SAR imagings.
Description
Technical field
The present invention relates to a kind of implementation methods of the FPGA of video SAR high-speed processing technologies, belong to radar imaging technology neck
Domain and digital signal processing technique field.
Background technology
Close air support system, by taking U.S. AC-130 as an example, mostly use greatly optical sensor to target carry out detection and
Tracking.Although optical sensor has many advantages, such as wavelength, short angle measurement accuracy is high, is easily influenced by atmospheric attenuation dust and strong light,
Detection range is limited, it is difficult to adapt to the battlefield surroundings that the changeable smoke of gunpowder of weather rises from all around.Compared to optical sensor, synthetic aperture radar
(synthetic aperture radar, SAR) has the characteristics that the round-the-clock high resolution of round-the-clock and penetration capacity are strong, no
It is influenced by fog precipitation cloud etc. is boisterous, becomes the important means of current earth observation and military surveillance.(video closes VideoSAR
At aperture radar) as a kind of new imaging pattern, realize the research hotspot that the high speed processing of its echo data is current.
VideoSAR Real-time processings system can carry out real time imagery prison under conditions of round-the-clock, round-the-clock to target scene
Depending on can in real time be monitored to the geographical location of operation situation and enemy army's warfare equipment movement on battlefield, control enemy in time
The latest development dynamic of army.
The concept of VideoSAR is in 2003 by U.S. Sandia National Labs (SandiaNational
Laboratories LarsWell etc.) proposes first, i.e., the reconstruction of scenes information in a manner of similar film (movie-like),
It realizes and the dynamic of maneuvering target is observed.The it is proposed of this concept causes the extensive concern of remote sensing circle.2012, U.S. national defense
Advanced research projects agency of portion proposes, to develop the extremely high frequency full-motion video high-resolution video SAR system of complete set, and in same
Year 2 parts of BAA files of successively issue, the design and utility strategies of VideoSAR systems are consulted to the whole world.Obviously, video SAR conducts
A kind of new imaging pattern, once realize that high-resolution is handled in real time, so that it may with the ground to targets such as enemy's vehicle tank warships
The progress such as reason position moving direction mobile route or even speed is round-the-clock to be traced and monitored, and the latest development for grasping enemy army in time is dynamic
State.
Field programmable gate array (Filed Programmable Gate Array, FPGA) has abundant look-up table
And register resources, using parallel processing manner, arithmetic speed is fast, low in energy consumption.SAR echo datas big, data with data volume
FFT, complex multiplication addition, cordic algorithm can be rapidly completed using FPGA processing compared to DSP in the high feature of rate
Etc. Digital Signal Processing basic operation.
Invention content
To realize speed is fast, degree of parallelism is high video SAR imagings, the present invention proposes at a kind of video SAR high speeds
The implementation method of the FPGA of reason technology realizes the Real-time processing to video SAR high-speed parallels.
The present invention is to solve its technical problem to adopt the following technical scheme that：
A kind of implementation method of the FPGA of video SAR high-speed processing technologies, includes the following steps：
Step 1, SAR raw radar datas and parameter are sent to fpga chip by host computer and Ethernet；
Step 2, to there is overlap mode to carry out frame extraction Duplication is arranged, and calculate each frame data PFA in echo data
Required parameter in processing procedure；
Step 3, being based on change of scale principle realizes multiple-pulse and row distance to processing；
Step 4, by distance into the data transposition write-in DDR1 handled；
Step 5, it is based on high-precision SINC interpolation and realizes orientation multiple-pulse parallel processing；
It step 6, will be in the complete data deposit DDR2 of orientation multiple-pulse parallel processing.
The detailed process of the step 3 is as follows：By step 2 calculating parameters obtained be stored in respectively in 4 RAM, then respectively from
Four pulses are read in DDR3 SDRAM, run through the reading of progress Article 2 pulse after first pulse；A pulse is often read,
Distance is input to processing module into row distance to processing.
The detailed process of the step 4 is as follows：In the data transposition write-in DDR that parallel processing in step 3 is finished, use
Fragmented storage method realizes the ranks transposition operation of radar data, and the raw column data of equivalent is stored in same a line of SDRAM.
The detailed process of the step 5 is as follows：First simultaneously four orientation pulse SINC interpolation of parallel computation when input
The frequency coordinate of point, the data that step 3 middle-range descriscent is disposed Pulse by Pulse transposition from DDR are read, and timesharing reads four
Pulse, each pulse are read, and just turn to pinpoint IP kernel and be converted to determine by floating-point by 64 double-precision floating point echo datas of SAR
Point data, then using the integer part for pinpointing echo data as address ram, piecemeal storage echo data and fractional part, pass through
The weighted sum that echo data is completed in addressing operation obtains SINC interpolation results.
The detailed process of the step 6 is as follows：Using binary channels DDR, be completed at the same time data from DDR1 reading with
The write-in storage of data in DDR2.
Beneficial effects of the present invention are as follows：
The present invention, which uses, is based on FPGA technology, realizes the extraction of data overlap frame, sub-aperture distance to change of scale, data
A series of imaging signal process flows such as ranks transposition, orientation SINC (Singh) interpolation.Data weight is carried out to SAR echo datas
Folded frame extracts and is based on each frame data of PFA algorithms is imaged high speed processing into row distance to orientation, which is not squinted
Angle influences, and is converted by the Keystone of orientation, can solve the more resolution elements far from imaging area centers scatter point and walk
Dynamic problem；By adjust the distance to orientation carry out multiple-pulse parallel processing structure optimization, can meet 5 frames of video SAR/
The high speed processing rate request of second, for video SAR, processing lays the foundation in real time.
Description of the drawings
Fig. 1 is the principle of the present invention realization figure.
Fig. 2 is that the FPGA of the present invention realizes block diagram.
Fig. 3 is UDP/IP protocol stack module figures.
Fig. 4 is distance to parallel processing FPGA block diagrams.
Fig. 5 is orientation high-precision Sinc interpolation multiple-pulse parallel organization figures.
Fig. 6 is storage schematic diagram of the sampled data in sub-block RAM.
Specific implementation mode
The invention is described in further details below in conjunction with the accompanying drawings.
As shown in Figure 1, traditional synthetic aperture radar carries out single imaging within an aperture time, to target scene.
And video SAR needs to carry out the extraction for having overlapping to the data in the synthetic aperture time to ensure the fluency of video pictures,
Independent imaging is carried out to the data of each frame.And subsequently through FPGA boards speed up processing and pass through VGA (videos
Graphic array) port shown on the screen, you can see smooth video pictures.
Video SAR imaging systems are mainly made of four nucleus modules：Overlapping frame data extraction module (is drawn according to Duplication
Divide the addresses DDR3 SDRAM, carry out piecemeal to data reads by several times) (video SAR echo datas arrive data transmission transposition module
The transmission of fpga chip and the caching of data and transposition), sub-aperture distance is to the parallel processing module (multiple-pulse based on PCS
Parallel change of scale) and sub-aperture orientation parallel processing module (the parallel SINC interpolation processings of multiple-pulse).
Overlapping frame data extraction module is illustrated first.
IP (IP core) address at the host computer setting fpga chip end at the ends PC, by SAR echo datas by with
Too net is sent to fpga chip by row deposit DDR3 SDRAM (Double Data Rate synchronous DRAM).Sub-aperture is set
Length and Duplication, as shown in Fig. 2, being divided into following steps：
Step 1：Reading sub-aperture electrical path length column data is input to distance and does four to parallel processing module from DDR3 SDRAM
The processing of pulse in parallel, and by the data transposition handled deposit DDR3 SDRAM；
Step 2：Four row data are read from DDR3 SDRAM transposition and carry out parallel SINC interpolation processings, and waiting is disposed
And DDR3 SDRAM are written in result, and first frame image procossing finishes；
Step 3：The reading address of DDR3 SDRAM is subtracted into sub-aperture electrical path length and multiplies Duplication as new reading address, weight
Multiple step 1 and step 2, until the processing of all echo datas is completed.
According to above-mentioned steps, SAR echo data of the multiframe with overlapping can be handled in one second, be the reality of video SAR
When imaging lay the foundation.
Next data transmission transposition module is illustrated.
Tri-state Ethernet (Tri-Mode Ethernet MAC) IP kernel, the user datagram provided using Xilinx companies
Agreement receives buffering area and sends buffering area (TX_FIFO) to complete Ethernet and its data transmit-receive function.Using UDP (users
Datagram)/IP agreement is realized and the data of host communicate, the UDP/IP protocol stack modules of specific implementation are as shown in Figure 3.It passes through
AXI4Stream bus protocols interface is connect with TEMAC nuclear phases.
DDR SDRAM modules have used Xilinx companies to provide DDR3 memory interfaces (MIG) solution.The solution party
Case provides Memory Controller Hub and physical layer design, and user, which is based on the program, directly to grasp DDR3 sdram memories
Make, by orbit parameter storage to parameter register, satellite-borne SAR echo data is stored in DDR3 SDRAM.
SAR data amount is big, and algorithm processing module is related to the ranks operation of data, in distance to passing through after processing
DDR realizes the transposition of matrix.Using the direct-type fragmented storage method of high transposition efficiency, phase is stored in same a line of SDRAM
With the row data and column data of length, be slightly increased write data enter a new line number while be greatly reduced and read the line feed time of data
Number.
Next it adjusts the distance and is illustrated to multiple-pulse parallel processing module.
The module diagram of distance to processing is as shown in Figure 4.
Four pulses are read from DDR3 SDRAM (Double Data Rate synchronous DRAM) first, are input to each
For a distance into processing unit, operation of each distance to processing unit is divided into following steps：
Step 1：The distance of sub-aperture image processing is calculated to using the PFA (polar format algorithm) based on change of scale
Method is multiplied by QP function first：
In formula, c is the light velocity, and τ is the fast time, and k is chirp rate, δrIt is distance to the change of scale factor, RaFor antenna phase
Instantaneous distance of the center to scene center.
Step 2：Carry out Fourier transformation is done, multiplied by with filter function：
Wherein：fτIt is distance to sample frequency,
Step 3：It is multiplied by QP function：
Wherein, fcFor carrier frequency.
Step 4：Fourier transformation is carried out, motion compensation factor t=f is multiplied byc/(fc+fτ)·t
Wherein：T is the time, and λ is wavelength.
Above-mentioned steps are executed respectively to four pulses, Pulse by Pulse transposition writes back DDR3 SDRAM after being disposed, and completes one
Secondary distance saves for 1/4 time to processing compared to a pulse is only handled each time before, substantially increases processing effect
Rate.
When wherein doing FFT (Fourier transformation) processing in above-mentioned steps, FFT uses an IP (IP core) three times
It is handled in the way of time-multiplexed, saves great amount of hardware resources.
Orientation processing converts the correction of further remaining linear range walk using Keystone, i.e., by high-precision
SINC interpolation operations realize transformation：
T=fc/(fc+fτ)·t' (7)
Wherein, t' is the time variable after orientation transformation.
It is converted by the Keystone of orientation, the more resolution elements far from imaging area centers scatter point can be solved and walked
Dynamic problem, can meet that satellite-borne SAR is comprehensive, high-resolution requirement.
Fig. 5 is that multiple-pulse of the orientation interpolating unit based on FPGA implements block diagram parallel.SINC ROM0-7 are in figure
8 ROM (read-only memory) of SINC interpolation coefficients are stored, DATA Sub_RAM0-7 are store radar return data 8
RAM (random access memory), parallel organization are roughly the same to processing realization with distance.
Transposition reads four pulse datas first from DDR3 SDRAM, is separately input to each orientation processing unit
In, the process flow of single processing unit is as follows：
Step 1：Orientation pulse is read from DDR3 SDRAM, waits for that orientation processing unit refreshes (RAM reset juxtapositions
Zero) after, input sample point data is temporarily stored into during FIFO (First Input First Output) connects.Simultaneously by floating type sample point coordinate
It is converted into fixed-point number, takes out integer part and fractional part；
Step 2：The sample point data of input is write into a row according to every 8, as shown in fig. 6, being put into Sub_RAM0-7
Storage, RAM (random access memory) interpolation address using the integer part in step 1 as each data, in view of the presence of two
And above sample point coordinate integer part is identical and decimal is different, present invention combination real application data increases by one group of RAM
The case where avoiding being override with same integer part.Way as illustrated, 8 sampled points can be fallen at this around point to be inserted
On 8 different sub-block RAM, this makes it possible to take out 8 sampled points and corresponding SINC coefficients phase in the same clock cycle
Multiply.
Step 3：Design SINC function quantized intervals be 1/16, x-i ∈ (- 4,4], wherein：X is interpolation point coordinates, and i is
Point coordinates to be inserted, it is 16 that SINC coefficient tables, which are stored in 8 depth, in the ROM that width is 32.
Step 4：N number of point to be inserted continuously inputs, i.e., each clock cycle inputs a point to be inserted.Through certain
After pipelining delay, interpolation result continuously exports.
As shown in above-mentioned steps, orientation, which is handled, in FPGA uses the SINC interpolation methods based on piecemeal RAM groups, from
Transposition reads distance to the floating data after processing in DDR, and floating data is converted to fixed-point data, pinpoints echo data
Integer part stores echo data and fractional part as address ram, piecemeal, and the weighting of echo data is completed by addressing operation
Summation obtains SINC interpolation results.
Orientation, to being disposed, decouples gained and data later is bidimensional FFT and is imaged with distance.
Above-mentioned distance to after being disposed of orientation, realize the distance and bearing of two-dimensional signal to decoupling.
The validity further illustrated the present invention is compared below by measured data.
Build parallel and non-parallel processing system respectively on the monolithic Virtex7-XC7VX6907 chips of Xilinx companies
System, to data that size is 8192*8192 into row distance to processing, in the case where system frequency is 200MHz, non-parallel place
The reason time is 2.9305s, and the parallel processing time is 1.4652s.
Non- parallel processing resources utilization power is as shown in table 1.
Table 1
Parallel processing resources utilization power is as shown in table 2.
Table 2
To data that size is 4096*4096 into row distance to processing, in the case where system frequency is 200MHz, it is non-simultaneously
Row processing time is 0.1306s, and the parallel processing time is 0.0631s.
Non- parallel processing resources utilization power is as shown in table 3.
Table 3
Parallel processing resources utilization power is as shown in table 4.
Table 4
Based on above table as can be seen that when Resources on Chip is enough, can be realized in 1 second the PFA of 5 frames or more at
As processing, meet the requirement of video SAR real time imageries.
Based on system above, the present invention provides a kind of implementation method of the FPGA of video SAR high-speed processing technologies, including such as
Lower step：
Step 1, SAR raw radar datas and parameter profit are sent to fpga chip by host computer and Ethernet；
Step 2, by echo data to there is overlap mode to carry out frame extraction, frame per second is improved by the way that Duplication is arranged, and count
Calculate required parameter in each frame data PFA processing procedures；
In the step 2, in synthetic aperture, non-overlapping extraction is per frame VideoSAR data, it is desirable that radar be operated in compared with
High band, radar should at least be operated in THz frequency ranges, it is contemplated that the limitation of prior art condition, using carrying out frame in an overlapping arrangement
It extracts to improve frame per second, by echo data to there is overlap mode to carry out frame extraction, improves frame per second by the way that Duplication is arranged, and count
Calculate required parameter in each frame data PFA processing procedures.
Step 3, it is based on change of scale principle and realizes that simultaneously row distance improves distance to processing speed to multiple-pulse to processing；
In the step 3, step 2 calculating parameters obtained is stored in respectively in 4 RAM first, in distance to four arteries and veins
Parameter reading can be carried out at the same time when rushing parallel processing.Data are read respectively from DDR again, DDR triggerings can only once be read
The data of one working length run through progress Article 2 arteries and veins after first pulse so reading four pulses from DDR respectively
The reading of punching.A pulse is often read, is input to distance to processing module into row distance to processing.DDR read pulse when
Between can ignore substantially compared with distance is to the time of processing, according to above-mentioned steps may be implemented distance to 4 pulse in parallel
Time is shorten to non-parallel 1/4 by processing.
Step 4, by distance into the data transposition write-in DDR handled；
In the data transposition write-in DDR that parallel processing in step 3 is finished, radar data is realized using fragmented storage method
Ranks transposition operates, and the raw column data of equivalent is stored in same a line of SDRAM, is being slightly increased write operation line feed number
The line feed number for greatly reducing read operation simultaneously, to improve the efficiency of transposition.
Step 5, it is based on high-precision SINC interpolation and realizes orientation multiple-pulse parallel processing.
In the step 5, first simultaneously four orientation pulse SINC interpolation of parallel computation when input point frequency coordinate,
The data that step 3 middle-range descriscent is disposed Pulse by Pulse transposition from DDR is read, and four pulses, each arteries and veins are read in timesharing
Punching is read, and 64 double-precision floating point echo datas of SAR are just turned fixed point IP kernel by floating-point is converted to fixed-point data, then will determine
The integer part of point echo data stores echo data and fractional part, is completed back by addressing operation as address ram, piecemeal
The weighted sum of wave number evidence obtains SINC interpolation results.In the case of orientation interpolation algorithm highly-parallel, orientation processing
The speed that speed reads data with DDR transposition differs big to processing not as good as distance, so will handle speed by four road pulse in parallel
Degree is reduced to original 1/2.
It step 6, will be in the complete data deposit DDR2 of orientation multiple-pulse parallel processing.
The processing of orientation multiple-pulse just has begun output interpolation knot when tetra- pulse datas of DDR do not read completion
Fruit is completed at the same time data and is stored from the reading in DDR1 and the write-in of data in DDR2 so using binary channels DDR.
Above example is merely illustrative of the invention's technical idea, and protection scope of the present invention cannot be limited with this, every
According to technological thought proposed by the present invention, any change done on the basis of technical solution each falls within the scope of the present invention
Within.
Claims (5)
1. a kind of implementation method of the FPGA of video SAR high-speed processing technologies, which is characterized in that include the following steps：
Step 1, SAR raw radar datas and parameter are sent to fpga chip by host computer and Ethernet；
Step 2, to there is overlap mode to carry out frame extraction Duplication is arranged, and calculate each frame data PFA processing in echo data
Required parameter in the process；
Step 3, being based on change of scale principle realizes multiple-pulse and row distance to processing；
Step 4, by distance into the data transposition write-in DDR1 handled；
Step 5, it is based on high-precision SINC interpolation and realizes orientation multiple-pulse parallel processing；
It step 6, will be in the complete data deposit DDR2 of orientation multiple-pulse parallel processing.
2. the implementation method of the FPGA of video SAR high-speed processing technologies according to claim 1 a kind of, which is characterized in that
The detailed process of step 3 is as follows：
Step 2 calculating parameters obtained is stored in respectively in 4 RAM, then reads four pulses from DDR3SDRAM respectively, is run through
The reading of Article 2 pulse is carried out after first pulse；A pulse is often read, is input to distance to processing module into row distance
To processing.
3. the implementation method of the FPGA of video SAR high-speed processing technologies according to claim 1 a kind of, which is characterized in that
The detailed process of step 4 is as follows：
In the data transposition write-in DDR that parallel processing in step 3 is finished, the ranks of radar data are realized using fragmented storage method
Transposition operates, and the raw column data of equivalent is stored in same a line of SDRAM.
4. the implementation method of the FPGA of video SAR high-speed processing technologies according to claim 1 a kind of, it is characterised in that：
The detailed process of step 5 is as follows：First simultaneously four orientation pulse SINC interpolation of parallel computation when input point frequency coordinate,
The data that step 3 middle-range descriscent is disposed Pulse by Pulse transposition from DDR is read, and four pulses, each arteries and veins are read in timesharing
Punching is read, and 64 double-precision floating point echo datas of SAR are just turned fixed point IP kernel by floating-point is converted to fixed-point data, then will determine
The integer part of point echo data stores echo data and fractional part, is completed back by addressing operation as address ram, piecemeal
The weighted sum of wave number evidence obtains SINC interpolation results.
5. the implementation method of the FPGA of video SAR high-speed processing technologies according to claim 1 a kind of, it is characterised in that：
The detailed process of step 6 is as follows：Using binary channels DDR, it is completed at the same time data writing from the reading in DDR1 and data in DDR2
Enter storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810203581.7A CN108614266A (en) | 2018-03-13 | 2018-03-13 | A kind of implementation method of the FPGA of video SAR high-speed processing technologies |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810203581.7A CN108614266A (en) | 2018-03-13 | 2018-03-13 | A kind of implementation method of the FPGA of video SAR high-speed processing technologies |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108614266A true CN108614266A (en) | 2018-10-02 |
Family
ID=63658672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810203581.7A Pending CN108614266A (en) | 2018-03-13 | 2018-03-13 | A kind of implementation method of the FPGA of video SAR high-speed processing technologies |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108614266A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116353A (en) * | 2018-07-19 | 2019-01-01 | 中国科学院电子学研究所 | The method and FPGA system of stolt interpolation are realized with FPGA |
| CN110161468A (en) * | 2019-04-11 | 2019-08-23 | 上海卫星工程研究所 | Satellite-borne SAR transmission channel data are changed into as receiving channel function module design method |
| CN111257874A (en) * | 2020-01-15 | 2020-06-09 | 中国电子科技集团公司第十四研究所 | PFA FPGA parallel implementation method |
| CN113641625A (en) * | 2021-08-19 | 2021-11-12 | 电子科技大学 | Four-way parallel data processing transposition system based on FPGA |
| CN113740851A (en) * | 2021-09-07 | 2021-12-03 | 电子科技大学 | SAR imaging data processing system of time-sharing multiplexing single DDR |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104215962A (en) * | 2014-08-04 | 2014-12-17 | 北京理工大学 | Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method |
| CN104459693A (en) * | 2014-12-01 | 2015-03-25 | 西安电子科技大学 | Missile-borne SAR forward-squint imaging method based on GPU |
| US9261593B1 (en) * | 2013-03-13 | 2016-02-16 | Lockheed Martin Corporation | Higher order processing for synthetic aperture radar (SAR) |
| CN105866774A (en) * | 2016-03-23 | 2016-08-17 | 南京航空航天大学 | FPGA implementation method for polar coordinate format imaging algorithm of chirp signal |
| CN106896360A (en) * | 2017-04-21 | 2017-06-27 | 南京航空航天大学 | A kind of FPGA implementation method of SAR signal processing algorithms |
| CN107229051A (en) * | 2017-05-26 | 2017-10-03 | 西安电子科技大学 | Video SAR echo simulation Parallel Implementation methods based on GPU |
-
2018
- 2018-03-13 CN CN201810203581.7A patent/CN108614266A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9261593B1 (en) * | 2013-03-13 | 2016-02-16 | Lockheed Martin Corporation | Higher order processing for synthetic aperture radar (SAR) |
| CN104215962A (en) * | 2014-08-04 | 2014-12-17 | 北京理工大学 | Monolithic FPGA (field programmable gate array) based Chirp Scaling imaging method |
| CN104459693A (en) * | 2014-12-01 | 2015-03-25 | 西安电子科技大学 | Missile-borne SAR forward-squint imaging method based on GPU |
| CN105866774A (en) * | 2016-03-23 | 2016-08-17 | 南京航空航天大学 | FPGA implementation method for polar coordinate format imaging algorithm of chirp signal |
| CN106896360A (en) * | 2017-04-21 | 2017-06-27 | 南京航空航天大学 | A kind of FPGA implementation method of SAR signal processing algorithms |
| CN107229051A (en) * | 2017-05-26 | 2017-10-03 | 西安电子科技大学 | Video SAR echo simulation Parallel Implementation methods based on GPU |
Non-Patent Citations (2)
| Title |
|---|
| FENG ZUO ETC.: ""A Persistent Imaging Method for Video-SAR in Terahertz Band"", 《2017ACES》 * |
| 梁健等: ""天基视频SAR系统设计及成像算法研究"", 《中国空间科学技术》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109116353A (en) * | 2018-07-19 | 2019-01-01 | 中国科学院电子学研究所 | The method and FPGA system of stolt interpolation are realized with FPGA |
| CN110161468A (en) * | 2019-04-11 | 2019-08-23 | 上海卫星工程研究所 | Satellite-borne SAR transmission channel data are changed into as receiving channel function module design method |
| CN110161468B (en) * | 2019-04-11 | 2023-05-26 | 上海卫星工程研究所 | Method for designing satellite-borne SAR transmission channel data-to-imaging receiving channel functional module |
| CN111257874A (en) * | 2020-01-15 | 2020-06-09 | 中国电子科技集团公司第十四研究所 | PFA FPGA parallel implementation method |
| CN113641625A (en) * | 2021-08-19 | 2021-11-12 | 电子科技大学 | Four-way parallel data processing transposition system based on FPGA |
| CN113740851A (en) * | 2021-09-07 | 2021-12-03 | 电子科技大学 | SAR imaging data processing system of time-sharing multiplexing single DDR |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108614266A (en) | A kind of implementation method of the FPGA of video SAR high-speed processing technologies | |
| CN108120980A (en) | A kind of implementation method of the FPGA of satellite-borne SAR multi-modal imaging signal processing algorithm | |
| CN105866774A (en) | FPGA implementation method for polar coordinate format imaging algorithm of chirp signal | |
| CN106896360A (en) | A kind of FPGA implementation method of SAR signal processing algorithms | |
| US7511656B2 (en) | Spotlight synthetic aperture radar (SAR) system and method for generating a SAR map in real-time using a modified polar format algorithm (PFA) approach | |
| EP2145206B1 (en) | Spotlight synthetic aperture radar system using fpga and corresponding method | |
| CN105137428B (en) | Go the FPGA implementation method of the polar coordinates format image-forming algorithm of slope signal | |
| CN110542900A (en) | SAR imaging method and system | |
| CN102508251B (en) | Method for rapidly implementing sector conversion in multi-beam image sonar | |
| Madani et al. | Radatron: Accurate detection using multi-resolution cascaded mimo radar | |
| CN102298139A (en) | Two-dimensional windowing method of synthetic aperture radar (SAR) imaging system based on field programmable gate array (FPGA) | |
| CN102680945A (en) | Doppler modulation frequency estimation method based on field programmable gate array (FPGA) | |
| Wiehle et al. | Synthetic aperture radar image formation and processing on an MPSoC | |
| CN111257874A (en) | PFA FPGA parallel implementation method | |
| Zhu et al. | A miniaturized high resolution SAR processor using FPGA | |
| Lee et al. | Design and development of FPGA-based FFT Co-processor for Synthetic Aperture Radar (SAR) | |
| CN117129994B (en) | Improved backward projection imaging method based on phase compensation nuclear GNSS-SAR | |
| Ming-ming et al. | High-performance system design of SAR real-time signal processing | |
| Gu et al. | Multi-core DSP based parallel architecture for FMCW SAR real-time imaging | |
| CN106908789B (en) | A kind of SAR imaging method based on the fusion of spatial domain Support | |
| Wang et al. | Video SAR high-speed processing technology based on FPGA | |
| Xin et al. | A wide-field SAR polar format algorithm based on quadtree sub-image segmentation | |
| Li et al. | A novel approach for wide‐swath and high‐resolution SAR image generation from distributed small spaceborne SAR systems | |
| Sheng et al. | A fast raw data simulator for the stripmap SAR based on CUDA via GPU | |
| Li et al. | An FPGA-based real-time UAV SAR raw signal simulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20181002 |
|
| RJ01 | Rejection of invention patent application after publication |