CN106991025A - FVLA based on hardware softening - Google Patents
FVLA based on hardware softening Download PDFInfo
- Publication number
- CN106991025A CN106991025A CN201710257721.4A CN201710257721A CN106991025A CN 106991025 A CN106991025 A CN 106991025A CN 201710257721 A CN201710257721 A CN 201710257721A CN 106991025 A CN106991025 A CN 106991025A
- Authority
- CN
- China
- Prior art keywords
- module
- trigger
- sampling
- control
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/25—Testing of logic operation, e.g. by logic analysers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses the FVLA based on hardware softening, including probe, latch, burr detection module, clock selection module, trigger module, USB control modules, host computer, sampling module, storage control module, first queue module, random storage module, second queue module, probe, latch, sampling module, first queue module, storage control module are sequentially connected；Latch, burr detection module, clock selection module, storage control module are sequentially connected；Burr detection module, trigger module are connected with sampling module respectively；Trigger module is connected with USB control modules, and trigger module, USB control modules, random storage module are connected with storage control module respectively；Storage control module, second queue module, USB control modules, host computer are sequentially connected.The present invention utilizes the hardware capability software implementation of virtual instrument technique, and the cost for making instrument by the programmability of software is reduced；Light and flexible and data analysis and process convenience.
Description
Technical field
The present invention relates to logic analysis, and in particular to the FVLA based on hardware softening.
Background technology
Logic analyser is broadly divided into logic timing analyzer and the major class of logic state analyzer two.Logic timing analyzer
Using internal clocking as sampling clock, sampling clock is 5 to 10 times of system under test (SUT) clock, and each passage is represented with time diagram
Digital waveform sequential relationship, be mainly used in the hardware testing of system, detect the work schedule of system and various abnormal
Burr pulse；Logic state analyzer, as sampling clock, commonly uses binary representation detected signal using external clock
Logic state, error code can be found rapidly, be conducive to functional analysis and program is debugged.
Traditional logic analyzer is while possessing power, and prices are rather stiff, and price general charged is tens of thousands of or even several
More than 100000 RMB, which greatly limits the popularization degree of logic analyser, why expensive traditional logic analyzer price is, main
It is that hardware cost price is too high to want reason；Traditional logic analyzer needs to set complicated trigger condition, complex operation.
The content of the invention
The technical problems to be solved by the invention are the expensive complex operations of logic analyser, it is therefore intended that offer is based on
The FVLA of hardware softening, makes low, easy to operate logic analyser cost, light and flexible, Data Analysis Services side
Just.
The present invention is achieved through the following technical solutions：
FVLA based on hardware softening, it is characterised in that including probe, latch, burr detection module,
Clock selection module, trigger module, USB control modules, host computer, sampling module, storage control module, first queue module,
Random storage module, second queue module, the probe, latch, sampling module, first queue module, storage control module
It is sequentially connected；The latch, burr detection module, clock selection module, storage control module are sequentially connected；The burr inspection
Module, trigger module is surveyed to be connected with sampling module respectively；The trigger module is connected with USB control modules, the trigger module,
USB control modules, random storage module are connected with storage control module respectively；The storage control module, second queue module,
USB control modules, host computer are sequentially connected.
Trigger module is received after the sample command that host computer is transmitted by USB control modules, in the effect of sampling clock
Under measured data is sampled, the data of sampling are compared by trigger module with trigger condition, if meeting trigger condition,
Data in Queue module are placed on by the data collected according to triggering is preceding with triggering latter two mode by storage control
In random storage module, by storage control module by the data in random storage module after data are filled with the storage depth of setting
Host computer is sent to through usb bus to be shown, so that user analyzes the data collected.
Further, probe includes programmable digital potentiometer, drive circuit, high-speed comparator, delay network, it is described can
Program numbers potentiometer, drive circuit, high-speed comparator, delay network are sequentially connected.Probe is for connection to logic analyser
With unique device of system under test (SUT), function served as bridge is played.Logic analyser work when will to gather signal electrical level judging, that is, adopt
The signal of collection is compared with the threshold level set in advance by programmable digital potentiometer, if less than the thresholding electricity of the setting
It is flat then output level is low level " 0 " after high-speed comparator, otherwise for high level " 1 ".
Further, clock selection module includes programmable frequency divider, clock selector, XOR gate, described programmable point
Frequency device, clock selector, XOR gate are sequentially connected.Logic analyser is divided into two kinds of working conditions of timing analysis and state analysis.
Logic analyser uses internal clock during timing analysis, that is, selects by the clock of the time base circuit generation of itself；Patrolled during state analysis
Collect analyzer and use external clock, that is, select the clock of system under test (SUT).
Further, burr detection module is by the first d type flip flop, the second trigger, the first NAND gate, the second NAND gate group
Into first NAND gate and the second NAND gate are connected with the first trigger respectively, first trigger and the second trigger
Connection.Burr is that the phenomenon such as crosstalk, power supply coupling is caused between the warfare in digital circuit, signal, and it can cause electricity
Road run-time error, common burr is divided into two kinds of positive burr and negative sense burr, and burr is detected by logic timing analyzer,
General sample frequency is 5 to 10 times of system under test (SUT) clock frequency.
Further, host computer includes sampling control, stops sampling control, triggering mode control, and the sampling control is used
In sending sample command, the stopping sampling control is used to send stopping sample command, and the triggering mode control is used to switch
The selection of triggering mode.
The present invention compared with prior art, has the following advantages and advantages：
1st, the present invention using virtual instrument technique hardware capability software implementation, by the programmability of software make instrument into
Originally reduced, the price of general logic analyser belongs to for acceptable scope within thousands of yuans；
2nd, the present invention is easy to operate, and the operational controls set using host computer are according to user oneself mode set in advance
It is operated, enormously simplify operating procedure；
3rd, light and flexible of the present invention and data analysis and process convenience, can connect host computer and be counted, analyzed, handled,
Effectively solve ancillary equipment debugging problem.
Brief description of the drawings
Accompanying drawing described herein is used for providing further understanding the embodiment of the present invention, constitutes one of the application
Point, do not constitute the restriction to the embodiment of the present invention.In the accompanying drawings：
Fig. 1 is schematic structural view of the invention.
Embodiment
For the object, technical solutions and advantages of the present invention are more clearly understood, with reference to embodiment and accompanying drawing, to this
Invention is described in further detail, and exemplary embodiment and its explanation of the invention is only used for explaining the present invention, does not make
For limitation of the invention.
Embodiment
As shown in figure 1, the FVLA based on hardware softening, including probe, latch, burr detection module,
Clock selection module, trigger module, USB control modules, host computer, sampling module, storage control module, first queue module,
Random storage module, second queue module, the probe, latch, sampling module, first queue module, storage control module
It is sequentially connected；The latch, burr detection module, clock selection module, storage control module are sequentially connected；The burr inspection
Module, trigger module is surveyed to be connected with sampling module respectively；The trigger module is connected with USB control modules, the trigger module,
USB control modules, random storage module are connected with storage control module respectively；The storage control module, second queue module,
USB control modules, host computer are sequentially connected.
Probe includes programmable digital potentiometer, drive circuit, high-speed comparator, delay network, the programmable digital
Potentiometer, drive circuit, high-speed comparator, delay network are sequentially connected.Programmable digital potentiometer carries out clear first when working
Zero, the threshold level then set according to host computer produces corresponding pulse to complete the setting of threshold level, and thresholding is electric
It is flat to store, just it is zeroed out until host computer is configured next time.Delay network does not work to logic timing analyzer, because
The internal clocking of system is used for logic timing analyzer, the clock with system under test (SUT) is asynchronous, so data channel is either with or without prolonging
When on logic timing analyzer sample result do not have what influence.Delay network works to logic state analyzer, if
Logic state analyzer is correctly fetched must make to meet data into the data of instrument and the relation of synchronized sampling clock
Setup time and the index required by data hold time.Wherein data setup time refers to adopt than synchronous into the data of instrument
The time set up and kept in advance during sample clock transition, data hold time refers to the data into instrument in synchronized sampling clock
The stable time is kept after saltus step.Learn that data hold time is that logic state analyzer can correctly be fetched for 0 by checking
Necessary condition.Because instrument inherently has device delay, it and data hold time occur simultaneously, and signal in digital display circuit
Bound-time, device delay under the influence of from present status to stabilization after next state required for saltus step used in
Time is different.Only in the case where device delay is more than data hold time, the time delay of data can be increased, adjusted
Time delay can make the time delay of clock lane be equal to the time of data channel plus the holding time of latch, reach that data are protected
Hold the purpose that the time is 0.
Latch plays two effects after delay network, mainly, and an effect is that its sampling clock is by becoming
System clock after changing, testing data is write in latch, is realized and is sampled with system synchronization；Another effect is each of input
Row data can reach latch simultaneously, eliminate the false triggering phenomenon caused because device delay is different.
Clock selection module includes programmable frequency divider, clock selector, XOR gate, the programmable frequency divider, clock
Selector, XOR gate are sequentially connected.In timing analysis, clock frequency is determined by programmable frequency divider, is passed through
VerilogHDL programming realization programmable frequency divider modules.Fundamental clock is by programmable frequency divider, by the clock frequency of generation
It is sent to clock selector；Logic analyser is in state analysis, and clock frequency is external clock；User selects internal clock as needed
And external clock, the selection of interior external clock is specifically determined by clock selector, after sampling clock is determined, sampling clock is should determine that
Validity, validity controls by host computer.
Burr detection module is made up of the first d type flip flop, the second trigger, the first NAND gate, the second NAND gate, and described
One NAND gate and the second NAND gate are connected with the first trigger respectively, and first trigger is connected with the second trigger.Burr
Detection module has two mode of operations, i.e. sampling configuration and burr recognition mode.Under sampling configuration, two NAND gates are not acted as
With, and burr can not be detected, it is risen using d type flip flop characteristic data storage down-sampled in the presence of sampling clock
Come；Under burr recognition mode, two NAND gates will work, and the output end Q1 of the first trigger value is by D1, set S and multiple
Position R is determined, and S and R value is determined by output end Q2, NQ2 and input signal of second trigger, when S and R does not rise
Determined during effect by input signal is D1, in such a mode, not only coming out the Data Detection collected can also be by hair
Thorn is detected, and burr broadens in the presence of sampling clock, facilitates user to watch.In burr recognition mode, work as Q2
When past state is low level, the first NAND gate is started working, and the second NAND gate does not work, at this moment according to NAND gate characteristic, can be with
It is just that 1, i.e. Q1 are 1 to obtain S when only input signal is high level, otherwise S is 0, and Q1 value is in the presence of sampling clock
The value 0 of input signal, when there is burr, i.e., input signal is that 1, i.e. S are 1, Q1=1 and arrived until next sampling period
Shi Yizhi is 1, now detects burr and amplifies out, observes and analyzes for user；When Q2 past states are 1, that is, gather
Signal is 0, then Q1=0, otherwise R1=0.If there is negative sense burr, i.e., reverse input signal is 1, i.e. R=1, Q1=0, and directly
When being arrived to next sampling period, now burr is detected and amplifies out, observed and analyze for user.
Host computer includes sampling control, stops sampling control, triggering mode control, and the sampling control is used to send sampling
Order, the sampling control that stops is used to send stopping sample command, and the triggering mode control is used for handover trigger mode
Selection.
Trigger module includes triggering identification module, and triggering identification module is to recognize to trigger and produce triggering according to triggering requirement
Marking signal, its operation principle is that the sampled data stream of input signal is set in advance tactile with user in each triggering identification module
Clockwork spring part is compared, if meeting trigger condition produces trigger flag, trigger flag selecting module is selected by triggering mode
The trigger flag signal of respective modules is exported, trigger control circuit is started by Trig control signal.
Above-described embodiment, has been carried out further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail, should be understood that the embodiment that the foregoing is only the present invention, be not intended to limit the present invention
Protection domain, within the spirit and principles of the invention, any modification, equivalent substitution and improvements done etc. all should be included
Within protection scope of the present invention.
Claims (5)
1. the FVLA based on hardware softening, it is characterised in that including probe, latch, burr detection module, when
Clock selecting module, trigger module, USB control modules, host computer, sampling module, storage control module, first queue module, with
Machine memory module, second queue module, the probe, latch, sampling module, first queue module, storage control module according to
Secondary connection；The latch, burr detection module, clock selection module, storage control module are sequentially connected；The burr detection
Module, trigger module are connected with sampling module respectively；The trigger module is connected with USB control modules, the trigger module,
USB control modules, random storage module are connected with storage control module respectively；The storage control module, second queue module,
USB control modules, host computer are sequentially connected.
2. the FVLA according to claim 1 based on hardware softening, it is characterised in that the probe includes
Programmable digital potentiometer, drive circuit, high-speed comparator, delay network, the programmable digital potentiometer, drive circuit,
High-speed comparator, delay network are sequentially connected.
3. the FVLA according to claim 1 based on hardware softening, it is characterised in that the clock selecting
Module includes programmable frequency divider, clock selector, XOR gate, and the programmable frequency divider, clock selector, XOR gate are successively
Connection.
4. the FVLA according to claim 1 based on hardware softening, it is characterised in that the burr detection
Module is made up of the first d type flip flop, the second trigger, the first NAND gate, the second NAND gate, first NAND gate and second with
NOT gate is connected with the first trigger respectively, and first trigger is connected with the second trigger.
5. the FVLA according to claim 1 based on hardware softening, it is characterised in that the host computer bag
Include sampling control, stop sampling control, triggering mode control, the sampling control is used to send sample command, and the stopping is adopted
Sample control is used to send stopping sample command, and the triggering mode control is used for handover trigger way choice.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710257721.4A CN106991025A (en) | 2017-04-19 | 2017-04-19 | FVLA based on hardware softening |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710257721.4A CN106991025A (en) | 2017-04-19 | 2017-04-19 | FVLA based on hardware softening |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106991025A true CN106991025A (en) | 2017-07-28 |
Family
ID=59415249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710257721.4A Withdrawn CN106991025A (en) | 2017-04-19 | 2017-04-19 | FVLA based on hardware softening |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106991025A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108319200A (en) * | 2018-02-28 | 2018-07-24 | 西安电子科技大学 | A kind of portable internet logic analyser |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103592599A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | USB-based logic analyzer triggering device |
-
2017
- 2017-04-19 CN CN201710257721.4A patent/CN106991025A/en not_active Withdrawn
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103592599A (en) * | 2013-10-31 | 2014-02-19 | 江苏绿扬电子仪器集团有限公司 | USB-based logic analyzer triggering device |
Non-Patent Citations (2)
| Title |
|---|
| 孙振伟: "《基于Labview的虚拟逻辑分析仪设计》", 《实践探索》 * |
| 李爱华等: "《基于虚拟仪器概念的虚拟逻辑分析仪的设计》", 《计算机测量与控制》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108319200A (en) * | 2018-02-28 | 2018-07-24 | 西安电子科技大学 | A kind of portable internet logic analyser |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105093094B (en) | Electric reliability automatic detection device and detection method on chip | |
| CN103995764B (en) | A kind of logic analyser with serial bus protocol continuous trigger function | |
| CN102541707B (en) | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method | |
| CN103245871B (en) | A kind of wire harness tester and the wire harness method of testing based on this wire harness tester | |
| CN102662835A (en) | Program debugging method of embedded system and embedded system | |
| CN110515788A (en) | A kind of test device of data-interface | |
| CN103955419A (en) | Logic analyzer with serial bus protocol on-line real-time detection analysis function | |
| CN105334452A (en) | Testing system for boundary scan | |
| CN109033891B (en) | Equipment for security attack test of SPI interface chip and security attack test method thereof | |
| CN112349336B (en) | Memory testing device | |
| CN102855338B (en) | Field programmable gate array (FPGA) prototype verification device and method | |
| CN105334451A (en) | Boundary scanning and testing system | |
| CN106991025A (en) | FVLA based on hardware softening | |
| CN111520191A (en) | Testing device and testing method for digital coal mine safety monitoring system | |
| CN103592599A (en) | USB-based logic analyzer triggering device | |
| CN202404912U (en) | Neural network test module and test system of smart card chip memory | |
| CN106546850B (en) | A kind of SRU fault confirmation method and device based on detection thermal station | |
| CN103091572A (en) | Signal testing device | |
| CN110287073A (en) | A kind of test device and method for a variety of multiple asynchronous serial communication peripheral hardwares | |
| CN206960619U (en) | A kind of the time reference device and check system of the verification of primary cut-out test system | |
| CN202758047U (en) | Circuit for timely detecting time performance of signal relay of test equipment | |
| CN103165405A (en) | Mutli-dimensional variable code real-time generation method through general purpose interface bus (GPIB) interface | |
| CN101191816B (en) | Chip test system | |
| CN109522212A (en) | A kind of acquisition terminal software reliability safety half detection system in kind | |
| CN106487421A (en) | Power line carrier communication test system and its method of testing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20170728 |
|
| WW01 | Invention patent application withdrawn after publication |