CN106487421A - Power line carrier communication test system and its method of testing - Google Patents
Power line carrier communication test system and its method of testing Download PDFInfo
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Abstract
A kind of power line carrier communication test system and its method of testing, described test system includes：Transmitting terminal, is suitable to test data be processed to generate test data frame and to cache, and described test data frame is sent to described receiving terminal by the fixing delivery time in each timing transmission cycle default by electric lines of force；Described receiving terminal, is suitable to receive all data from described electric lines of force within i-th timing receipt cycle and cache；Described test data frame is obtained from all data receiving in time period after i-th timing receipt cycle, described test data frame is carried out be processed to determine whether to be properly received described test data frame and count successful receiving rate, and after completing described test data frame is processed, receive all data on described electric lines of force within the next timing receipt cycle and cache.Using described system and method, design and the test period of power-line carrier communication system can be efficiently reduced.
Description
Technical field
The present invention relates to the communications field, more particularly, to a kind of power line carrier communication test system and its test
Method.
Background technology
Power line communication (Power Line Communication, PLC) refers to by the use of electric lines of force as biography
A kind of communication technology of defeated media implementation data transfer.Widely available due to power infrastructures, and
Safe, reliable, efficient, the inexpensive technical advantage of power line communication, intelligent grid, smart home,
The thing thing such as intelligent building, intelligent lamp control interconnection emerging field has broad application prospects.
But, low-voltage power line is not the main flow channel being specifically used to transmit communication data, its topology
Structure and physical characteristics are all different from traditional communication transmission media.When carrying out signal transmission, channel is special
Property considerably complicated, load many, noise jamming is strong, fading channel is big.Meanwhile, related to power line channel
Major parameter such as impedance operator, interchannel noise, fading channel characteristic be not changeless, but
Over time, frequency ceaselessly changes.
Because power line channel is nonlinear time-varying channels, in the prior art, it is difficult to low-voltage power line
Communication channel is precisely modeled.Generally adopt relatively simple channel model to power line communication algorithm
Can be emulated, after emulation is passed through, be carried out circuit realiration.After circuit realiration, can be compiled by scene
Journey gate array (Field Programmable Gate Array, FPGA) is enterprising in actual low-voltage power line
The checking of row communication performance, and according to authentication result, the communication of algorithms and circuit are adjusted, last ability
Carry out design and the flow of chip.
However, during being verified, needing the communication of algorithms and circuit to be changed repeatedly and debugs,
Cause the proving time long, delay the project cycle.
Content of the invention
The problem that the present invention solves is how to reduce design and the test period of power-line carrier communication system.
For solving the above problems, the present invention provides a kind of power line carrier communication test system, including：
Transmitting terminal, is suitable to test data be processed to generate test data frame and to cache, default
Fixing delivery time in each timing transmission cycle, by described test data frame by electric lines of force send to
Receiving terminal；
Described receiving terminal, is suitable to receive all numbers from described electric lines of force within i-th timing receipt cycle
According to and cache；In time period after described i-th timing receipt cycle from all data receiving
Obtain described test data frame, described test data frame is carried out be processed to determine whether being properly received described
Test data frame simultaneously counts successful receiving rate, and after completing described test data frame is processed,
Receive all data on described electric lines of force in the next timing receipt cycle and cache；
It is equal with the described timing receipt cycle that described timing sends the cycle.
Optionally, described receiving terminal is further adapted for：When coming of receiving within described i-th timing receipt cycle
From in all data of described electric lines of force, when failing to obtain complete described test data frame, from described next
The position of frame synchronization field is obtained from all data of electric lines of force；Position acquisition according to described frame synchronization field
The phase place of the first timer of described transmitting terminal；According to the phase place of described first timer, to described reception
The phase place of the second timer at end is modified so that described receiving terminal connect within the described timing receipt cycle
Receive complete described test data frame；Described first timer is adapted to provide for the timing transmission cycle, described
Second timer is adapted to provide for the timing receipt cycle.
Optionally, described transmitting terminal includes：Transmitting terminal host computer and data storage dispensing device, wherein：
Described transmitting terminal host computer, is suitable to test data is processed to generate test data frame, and will
Described test data frame is sent to described data storage dispensing device by data transmission interface；
Described data storage dispensing device, is suitable to receive the described test number that described transmitting terminal host computer sends
According to frame and cache；Fixing delivery time in each timing transmission cycle default, by described test number
Sent to described receiving terminal by electric lines of force according to frame.
Optionally, described first timer is arranged in described data storage dispensing device, and described data
Storage dispensing device includes：Send control unit and the first data buffer storage unit, wherein：Described first
Intervalometer, is adapted to provide for the timing transmission cycle；Described first data buffer storage unit, is suitable to cache described survey
Examination Frame；Described transmission control unit, the fixation being suitable in each timing transmission cycle default is sent out
Send the moment, described test data frame is sent to described receiving terminal by electric lines of force.
Optionally, described data storage dispensing device is FPGA.
Optionally, described receiving terminal includes：Receiving terminal host computer and data receiver storage device, wherein：
Described data receiver storage device, is suitable to receive from described within described i-th timing receipt cycle
All data of electric lines of force simultaneously cache；Will be described in time period after described i-th timing receipt cycle
The all data receiving are sent to described receiving terminal host computer by data transmission interface；When detecting
State after the completion of receiving terminal host computer processes to described test data frame, connect within the next timing receipt cycle
Receive all data on electric lines of force and cache；
Described receiving terminal host computer, is suitable to obtain described test data from the described all data receiving
Frame, and described test data frame is carried out be processed to determine whether to be properly received described test data frame and unite
Meter successful receiving rate.
Optionally, described second timer is arranged in described data receiver storage device, and described data
Receiving/storing device includes：Reception control unit and the second data buffer storage unit, wherein：Described second
Intervalometer, is adapted to provide for the timing receipt cycle；Described second data buffer storage unit, is suitable to be buffered in described
The all data from described electric lines of force receiving in i-th timing receipt cycle；Described reception controls list
Unit, is suitable to when detect after the completion of described receiving terminal host computer processes to described test data frame, at next
The all data on described electric lines of force are received in the individual timing receipt cycle.
Optionally, described data receiver storage device is FPGA.
The embodiment of the present invention additionally provides a kind of power line carrier communication method of testing, using any of the above-described kind
Described power line carrier communication test system is tested, and described method of testing includes：
Transmitting terminal is processed to test data to generate test data and to cache, in each timing default
Fixing delivery time in the transmission cycle, described test data frame is sent to receiving terminal by electric lines of force；
Described receiving terminal received all data from described electric lines of force and delays i-th timing receipt cycle
Deposit, from all data receiving, in the time period after described i-th timing receipt cycle, obtain institute
State test data frame, described test data frame is carried out be processed to determine whether to be properly received described test number
According to frame and count successful receiving rate, and after completing described test data frame is processed, in the next one
Receive all data on electric lines of force in the timing receipt cycle and cache；Described timing send the cycle with described
The timing receipt cycle is equal.
Compared with prior art, technical scheme has advantages below：
Transmitting terminal is sent test data frame to receiving terminal by electric lines of force, and receiving terminal receives and is derived from electric lines of force
On all data, therefrom extract test data frame to determine whether to be properly received test data frame, and
The successful receiving rate of statistical test Frame.Due in the transmission of real electric lines of force enterprising row data with connect
Receive to be tested, therefore during the communication of algorithms is verified, power line communication need not be set up
Channel model, such that it is able to avoid because cannot Accurate Model and lead to algorithm and circuit are changed repeatedly
Checking, leads to the problem that the project cycle is longer.
Further, receiving terminal passes through all data extraction frame synchronization fields that detection receives on electric lines of force,
The phase place of the dead reckoning first timer according to frame synchronization field, and according to the phase place of first timer to
The phase place of two intervalometers is adjusted so that receiving terminal received completely within the timing receipt cycle afterwards
Described test data frame, complete such that it is able to avoid cannot receiving one within a timing receipt cycle
The problem of whole test data frame.
Brief description
Fig. 1 is the structural representation of one of embodiment of the present invention power line carrier communication test system；
Fig. 2 is the structural representation of one of embodiment of the present invention test data frame；
Fig. 3 is the structural representation of another kind of power line carrier communication test system in the embodiment of the present invention；
Fig. 4 is the working timing figure of one of embodiment of the present invention power line carrier communication test system；
Fig. 5 is the working timing figure of one of embodiment of the present invention power line carrier communication test system；
Fig. 6 is the sequential chart of one of embodiment of the present invention timing receipt period modulation.
Specific embodiment
Conventionally, as power line channel is nonlinear time-varying channels, therefore, it is difficult to low pressure
Power line communication channel is precisely modeled.During algorithm design and circuit realiration, generally require
Reserved certain parameter surplus, in the stage verified by FPGA, according to the reality of power line channel
Situation is adjusted to the communication of algorithms and circuit.However, some problems may by adjusting parameter Lai
Solve, need to carry out larger change to the communication of algorithms or circuit thereby increases and it is possible to need repeatedly to change and test,
Cause the proving time long, delay the Project-developing cycle.
In the present invention, transmitting terminal is sent test data frame to receiving terminal by electric lines of force, receives termination
Receive all data on electric lines of force, therefrom extract test data frame to determine whether to be properly received survey
Examination Frame, and the successful receiving rate of statistical test Frame.Due in the enterprising line number of real electric lines of force
According to send and receive and tested, therefore during the communication of algorithms is verified, need not build
Vertical power line communication channel model, such that it is able to avoid because cannot Accurate Model and lead to algorithm and electricity
Checking is changed on road repeatedly, leads to the problem that the project cycle is longer.
Understandable for enabling the above-mentioned purpose of the embodiment of the present invention, feature and advantage to become apparent from, tie below
Close accompanying drawing the specific embodiment of the present invention is described in detail.
With reference to Fig. 1, give one of embodiment of the present invention power line carrier communication test system 10,
Including：Transmitting terminal 101 and receiving terminal 102, wherein：
Described transmitting terminal 101, is suitable to test data be processed to generate test data frame and to cache,
Fixing delivery time in each timing transmission cycle default, described test data frame is passed through electric lines of force
Send to described receiving terminal 102；
Described receiving terminal 102, is suitable to receive the institute from described electric lines of force within i-th timing receipt cycle
There is data and cache, in the time period after i-th timing receipt cycle from all data receiving
Obtain described test data frame；Described test data frame is carried out be processed to determine whether being properly received described
Test data frame simultaneously counts successful receiving rate；After completing described test data frame is processed, under
Receive all data on electric lines of force in one timing receipt cycle and cache, timing sends cycle and timing
The reception cycle is equal.
With reference to Fig. 2, give the structural representation of one of embodiment of the present invention test data frame.One
Test data frame can include frame synchronization field, valid data and CRC check domain, wherein, frame synchronization field
It is arranged on the frame header position of test data frame, CRC check domain is arranged on the postamble position of test data frame,
Valid data are arranged between frame synchronization field and CRC check domain.
In embodiments of the present invention, valid data can include encoded and modulation after test data；
Frame synchronization field can be used to carry out frame synchronization to valid data, and is used for being transmitted holding determining with receiving terminal
When device phase place synchronization；Receiving terminal can judge by CRC check domain that the test data frame receiving is
No mistake, with the successful receiving rate of statistical test Frame.
With reference to Fig. 3, give the structure of one of embodiment of the present invention power line carrier communication test system
Schematic diagram.
In embodiments of the present invention, transmitting terminal can include transmitting terminal host computer 301 and data storage is sent out
Send device 302, wherein, transmitting terminal host computer 301 and data storage dispensing device 302 can pass through data
Coffret is communicated.When verifying to communication of algorithms program, in transmitting terminal host computer 301
Communication of algorithms Program Generating test data.Transmitting terminal host computer 301 carries out CRC to sent test data
After verification, coding and modulation etc. are processed, generate test data frame, and sent by data transmission interface
To data storage dispensing device 302.
Data storage dispensing device 302, can be first by the test receiving after receiving test data frame
Data frame buffer memory.Fixing delivery time in each timing transmission cycle default, data storage sends
Test data frame is sent to the data receiver storage device of receiving terminal by device 302 by electric lines of force 305
304.
In embodiments of the present invention, the fixing delivery time in the timing transmission cycle can be that timing sends week
The initial time of phase or the cut-off time in timing transmission cycle, can also be the timing transmission cycle
In any instant.
In an embodiment of the present invention, data storage dispensing device 302 includes the first data buffer storage unit
3023rd, control unit 3022 and first timer 3021 are sent, wherein：First timer 3021 is fitted
Send the cycle in providing timing；First data buffer storage unit 3023 is used for caching transmitting terminal host computer 301
The test data frame sending；Send control unit 3022, the fixation in each timing transmission cycle default
Delivery time, test data frame is sent to receiving terminal by electric lines of force 305.
Transmitting terminal host computer 301 can be PC, and data storage dispensing device 302 can be and PC
The hardware circuit coupling, this hardware circuit can realize the function that data storage and timing send.Hardware electricity
Road can be arm processor, or is FPGA etc..In an embodiment of the present invention, data storage sends
Device is FPGA.Data transfer between transmitting terminal host computer 301 and data storage dispensing device 302 connects
Mouth can be UART interface or USB interface or other kinds of communication interface.
Receiving terminal can include receiving terminal host computer 303 and data receiver storage device 304, data receiver
Storage device 304 can be coupled by data transmission interface with receiving terminal host computer 303.Data receiver is deposited
Storage device 304 can be coupled with the data storage dispensing device 302 of transmitting terminal by electric lines of force 305, with
Receiving data stores the test data frame that dispensing device is sent by electric lines of force 305.
Because receiving terminal and may not know the moment that transmitting terminal sends test data frame in advance, only know and send out
Each timing transmission cycle of sending end all can send a test data frame, and timing sends cycle and timing
The reception cycle is equal, and therefore, data receiver storage device 304 can connect within i-th timing receipt cycle
Receive all data on the electric lines of force 305, and by all data buffer storages receiving.
Next cycle after i-th timing receipt cycle, i.e. the i+1 timing receipt cycle, number
The all data is activations being received according to storage i-th timing receipt cycle of reception device 304 are to receiving terminal
Position machine 303.Receiving terminal host computer 303 is subsequently processed to all data receiving, and therefrom extracts
Test data frame, and test data frame is processed, to judge whether successfully receiving test data frame,
Thus obtaining the successful receiving rate of test data frame.
When receiving terminal host computer 303 carries out data processing, data receiver storage device 304 can not connect
Receive the data on electric lines of force 305, until after receiving terminal host computer 303 completes data processing, in the next one
In the timing receipt cycle, data receiver storage device 304 receives all data on electric lines of force 305 again.
In an embodiment of the present invention, data receiver storage device 304 includes：Reception control unit 3042,
Second timer 3041 and the second data buffer storage unit 3043, wherein：Second data buffer storage unit 3043,
It is suitable to cache all data from electric lines of force receiving in i-th timing receipt cycle；Second timer
3041 are adapted to provide for the timing receipt cycle；Reception control unit 3042, is suitable to upper when receiving terminal is detected
After the completion of machine 303 is to test data frame process, receives within the next timing receipt cycle and be derived from electric lines of force
All data on 305.
Receiving terminal host computer 303 can be PC, and data receiver storage device 304 can be and PC
The hardware circuit coupling, this hardware circuit can realize data storage and the function of timing receipt, hardware electricity
Road can be arm processor, or is FPGA etc..In an embodiment of the present invention, data receiver storage
Device is FPGA.Data transfer between receiving terminal host computer 303 and data receiver storage device 304 connects
Mouth can be UART interface or USB interface or other kinds of communication interface.
Workflow to the power line carrier communication test system providing in the above embodiment of the present invention below
It is described in detail.
With transmitting terminal host computer as PC, data storage dispensing device is the work to transmitting terminal as a example FPGA
Illustrate as flow process.
Communication of algorithms program still to be tested is run on transmitting terminal PC.Transmitting terminal PC is to the communication of algorithms
After the test data of Program Generating carries out the process such as CRC check, coding and modulation, generate test data
Frame is simultaneously sent to transmitting terminal FPGA by data transmission interface.
When the start of transmitting terminal PC runs, the first timer of transmitting terminal FPGA starts timing.When connecing
When the start of receiving end PC runs, the second timer of transmitting terminal FPGA starts timing.First timer
Timing cycle be 2s, that is, timing send the cycle be 2s, every 2s first timer counting reset and again
Start timing.The fixing delivery time that timing sends the cycle is that each timing sends the end cycle moment.
For example, the fixing delivery time that timing sends the cycle is the time slot counting down to when 10000 of first timer
Point.
Transmitting terminal FPGA passes through the test data frame that data transmission interface receiving end/sending end PC sends, and
Test data frame is saved in the first data buffer storage unit.Tie when each timing transmission cycle is detected
Shu Shi, that is, when when being counted as 10000 of first timer is detected, sends control unit by the first data
Test data frame in buffer unit is sent to receiving terminal by electric lines of force.
Understand from above-mentioned transmission process, transmitting terminal PC is only responsible for generating test data frame and sending to transmission
End FPGA.Transmitting terminal FPGA, when each timing sends end cycle, test data frame is passed through electricity
The line of force sends to receiving terminal, and that is, transmitting terminal FPGA all sent to receiving terminal within each timing transmission cycle
One test data frame.
With receiving terminal host computer as PC, data receiver storage device is the work to receiving terminal as a example FPGA
Illustrate as flow process.The timing receipt cycle is equal with the timing transmission cycle, is 2s.
Receiving terminal FPGA is in the i-th -1 timing receipt end cycle, namely i-th timing receipt cycle
During beginning, all data on electric lines of force are received by reception control unit, and be buffered in the second number
According in buffer unit.In the i+1 timing receipt cycle, receiving terminal PC passes through data transmission interface from the
The all data on electric lines of force are read in two data buffer storage units.
Receiving terminal PC is processed to reading all data on electric lines of force, therefrom extracts
Test data frame, synchronizes, demodulates to the test data frame extracting, decoding and CRC check etc.
Operation, according to the result of CRC check, the success of discriminating test data frame receipt or failure, and is come with this
The successful receiving rate of statistical test Frame.
When receiving terminal PC carries out data processing, receiving terminal FPGA does not receive on electric lines of force
Data.After receiving terminal PC completes the operation to test data frame, reception control unit is next fixed
When receive the cycle and receive all data on the electric lines of force.For example, within the i-th+3 timing receipt cycles
Receiving terminal PC completes the operation to test data frame, then connect when starting in the i-th+4 timing receipt cycles
Receive all data on electric lines of force.
With reference to sequential chart to the power line carrier communication test system providing in the above embodiment of the present invention
Test process illustrate, with reference to Fig. 4.
Transmitting terminal PC is in t0Moment generates test data frame and sends to transmitting terminal FPGA.Send and control
Unit sends the finish time in cycle in each timing：t1、t2、t3、t4、t5、t6Moment, by test data
Frame is sent to receiving terminal FPGA by electric lines of force, that is, send control unit respectively in t1、t2、t3、t4、t5、
t6Moment all sends test data frame by electric lines of force, as shown in the corresponding dash area of transmitting terminal in Fig. 4.
t1～t2、t2～t3、t3～t4、t4～t5、t5～t6Duration interval be a timing transmission cycle.
The timing receipt cycle of receiving terminal FPGA is equal with the timing transmission cycle of transmitting terminal FPGA, the
One intervalometer and second timer homophase, the timing receipt cycle is followed successively by t1～t2、t2～t3、t3～t4、t4～t5、
t5～t6.
In t1～t2In the moment, reception control unit receives all data on electric lines of force, and will receive
The all data buffer storages on electric lines of force；In t2～t4In the moment, receiving terminal PC is from the second data buffer storage
T is read in unit1～t2In moment, the data of caching, therefrom extracts test data frame, and to test data
Frame carries out being processed to determine whether to be properly received test data frame, and the reception success of statistical test Frame
Rate.Receiving terminal PC is in t2～t4Aforesaid operations are completed in moment.In t2～t4Moment, reception control unit
Do not receive the data on electric lines of force.
In next timing receipt cycle, i.e. t4～t5In the moment, reception control unit receives on electric lines of force
All data.By that analogy, reception control unit carries out a secondary data every two timing receipt cycles
Receive；Receiving terminal PC is every two timing receipt cycles, all on electric lines of force to receiving
Data is processed, the successful receiving rate of statistical test Frame.
As can be seen here, transmitting terminal is sent test data frame to receiving terminal by electric lines of force, and receiving terminal receives
All data on electric lines of force, and therefrom extract test data frame to determine whether to be properly received survey
Examination Frame, and the successful receiving rate of statistical test Frame.Due in the enterprising line number of real electric lines of force
According to send and receive and tested, therefore during the communication of algorithms is verified, need not build
Vertical power line communication channel model, such that it is able to avoid because cannot Accurate Model and lead to algorithm and electricity
Checking is changed on road repeatedly, leads to the problem that the project cycle is longer.
As can be known from Fig. 4, the of the phase place of the first timer of transmitting terminal FPGA and receiving terminal FPGA
The phase of two intervalometers.However, in actual applications, due to transmitting terminal FPGA and receiving terminal FPGA
Work independently from each other, the phase place of the first timer of transmitting terminal FPGA is fixed with the second of receiving terminal FPGA
When device phase place may stagger, as shown in Figure 5.In timing receipt cycle t21～t22In, receiving terminal FPGA
Receive two incomplete test data frames.Because the timing transmission cycle is equal with the timing receipt cycle,
Now, within arbitrary timing receipt cycle afterwards, receiving terminal FPGA cannot receive complete survey
Examination Frame, leads to receiving terminal PC to judge that all of test data frame is the situation generation of mistake, from
And test result cannot be obtained.
For avoiding the generation of the problems referred to above, in embodiments of the present invention, can be by adjusting receiving terminal second
The method of the phase place of intervalometer is solving the above problems.
As can be known from Fig. 2, test data frame includes frame synchronization field.Therefore, when receiving terminal receive send out
During first test data frame that sending end sends, you can know the phase place of first timer and fixed to second
When device phase place correspondingly adjusted, such that it is able to avoid all cannot connecing in the timing receipt cycle in office
The situation receiving complete test data frame occurs.
With reference to Fig. 6, give the sequential chart of one of embodiment of the present invention timing receipt period modulation.Send out
First timing of sending end sends the cycle for t1～t2, first timing receipt cycle is t21～t22, from Fig. 6
Understand, the test data frame that in first timing receipt cycle, reception control unit receives not is one
Complete test data frame.
(t in time period after first timing receipt cycle22～t23), receiving terminal PC does not dock
The test data frame receiving is parsed, but all numbers receiving within first timing receipt cycle
According to middle lookup frame synchronization field, go out the phase place of first timer according to the dead reckoning of frame synchronization field, then right
The phase place of second timer is modified.The phase place of amended second timer and the phase of first timer
Dislocation opens certain angle so that a test completing can be received within a timing receipt cycle
Frame.
In t23Next timing receipt cycle t afterwards24～t25, institute on electric lines of force for the receiving terminal reception
There is data, the phase place due to second timer will be in t22～t23Carry out corresponding modification, therefore afterwards
The timing receipt cycle in all include complete survey in all data from electric lines of force that receive of receiving terminal
Examination Frame.
As can be seen here, receiving terminal passes through all data extraction frame synchronization fields that detection receives on electric lines of force,
The phase place of the dead reckoning first timer according to frame synchronization field, and according to the phase place of first timer to
The phase place of two intervalometers is adjusted so that receiving terminal can receive within the timing receipt cycle afterwards
Complete described test data frame, such that it is able to avoid to receive one within a timing receipt cycle
The problem of individual complete test data frame.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (9)
1. a kind of power line carrier communication test system is it is characterised in that include：
Transmitting terminal, is suitable to test data be processed to generate test data frame and to cache, default each
Fixing delivery time in the timing transmission cycle, described test data frame is sent to reception by electric lines of force
End；
Described receiving terminal, be suitable within i-th timing receipt cycle receive from described electric lines of force all data simultaneously
Caching；Obtain from all data receiving in time period after described i-th timing receipt cycle
Described test data frame, carries out to described test data frame being processed to determine whether to be properly received described test
Frame simultaneously counts successful receiving rate, and after completing described test data frame is processed, at next
Receive all data on described electric lines of force in the individual timing receipt cycle and cache；
It is equal with the described timing receipt cycle that described timing sends the cycle.
2. power line carrier communication test system as claimed in claim 1 is it is characterised in that described receiving terminal
It is further adapted for：
When in all data from described electric lines of force receiving within described i-th timing receipt cycle, fail
When obtaining complete described test data frame, obtain frame synchronization from all data of electric lines of force from described
The position in domain；
The phase place of the first timer of transmitting terminal described in position acquisition according to described frame synchronization field；
According to the phase place of described first timer, the phase place of the second timer of described receiving terminal is modified,
Described receiving terminal is made to receive complete described test data frame within the timing receipt cycle afterwards；
Described first timer is adapted to provide for the timing transmission cycle, and described second timer is adapted to provide for timing receipt
Cycle.
3. power line carrier communication test system as claimed in claim 2 is it is characterised in that described transmitting terminal
Including：Transmitting terminal host computer and data storage dispensing device, wherein：
Described transmitting terminal host computer, is suitable to test data is processed to generate test data frame, and will be described
Test data frame is sent to described data storage dispensing device by data transmission interface；
Described data storage dispensing device, is suitable to receive the described test data frame that described transmitting terminal host computer sends
And cache；Fixing delivery time in each timing transmission cycle default, by described test data frame
Sent to described receiving terminal by electric lines of force.
4. power line carrier communication test system as claimed in claim 3 is it is characterised in that described first is fixed
When device be arranged in described data storage dispensing device, and described data storage dispensing device includes：Send
Control unit and the first data buffer storage unit, wherein：
Described first timer, is adapted to provide for the timing transmission cycle；
Described first data buffer storage unit, is suitable to cache described test data frame；
Described transmission control unit, is suitable to the fixing delivery time in each timing transmission cycle default, will
Described test data frame is sent to described receiving terminal by electric lines of force.
5. power line carrier communication test system as claimed in claim 4 is it is characterised in that described data is deposited
Storage dispensing device is FPGA.
6. power line carrier communication test system as claimed in claim 2 is it is characterised in that described receiving terminal
Including：Receiving terminal host computer and data receiver storage device, wherein：
Described data receiver storage device, is suitable to receive from described electric power within described i-th timing receipt cycle
All data of line simultaneously cache；By described reception in time period after described i-th timing receipt cycle
To all data sent to described receiving terminal host computer by data transmission interface；Connect described in detect
After the completion of receiving end host computer is processed to described test data frame, receive within the next timing receipt cycle
All data from electric lines of force simultaneously cache；
Described receiving terminal host computer, is suitable to obtain described test data frame from the described all data receiving,
And described test data frame carried out be processed to determine whether being properly received with described test data frame counting connect
Harvest power.
7. power line carrier communication test system as claimed in claim 6 is it is characterised in that described second is fixed
When device be arranged in described data receiver storage device, and described data receiver storage device includes：Receive
Control unit and the second data buffer storage unit, wherein：
Described second timer, is adapted to provide for the timing receipt cycle；
Described second data buffer storage unit, is suitable to be buffered in being derived from of receiving in described i-th timing receipt cycle
All data of described electric lines of force；
Described reception control unit, is suitable to described test data frame be processed when described receiving terminal host computer is detected
After the completion of, receive all data on described electric lines of force within the next timing receipt cycle.
8. power line carrier communication test system as claimed in claim 7 is it is characterised in that described data connects
Harvesting saving is set to FPGA.
9. a kind of power line carrier communication method of testing is it is characterised in that adopt such as any one of claim 1～8
Described power line carrier communication test system is tested, and described method of testing includes：
Transmitting terminal is processed to test data to generate test data and to cache, and sends in each timing default
Fixing delivery time in cycle, described test data frame is sent to receiving terminal by electric lines of force；
Described receiving terminal received all data from described electric lines of force and caches i-th timing receipt cycle,
Described survey is obtained from all data receiving in time period after described i-th timing receipt cycle
Examination Frame, carries out to described test data frame being processed to determine whether to be properly received described test data frame
And count successful receiving rate, and after completing described test data frame is processed, in next timing
Receive all data on described electric lines of force in the reception cycle and cache；Described timing send the cycle with described
The timing receipt cycle is equal.
Priority Applications (1)
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| CN109391223A (en) * | 2017-08-02 | 2019-02-26 | 丰郅(上海)新能源科技有限公司 | It can the method for the photovoltaic generating system of sending and receiving data and its sending and receiving data at times |
| CN110260967A (en) * | 2019-07-23 | 2019-09-20 | 厦门大学 | A kind of high-volume weighing electronic scale that open source data-interface is provided |
| CN115357067A (en) * | 2022-08-26 | 2022-11-18 | 上海磐启微电子有限公司 | Full-automatic batch test system for high and low temperature performance of wireless image transmission product |
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| CN110260967A (en) * | 2019-07-23 | 2019-09-20 | 厦门大学 | A kind of high-volume weighing electronic scale that open source data-interface is provided |
| CN115357067A (en) * | 2022-08-26 | 2022-11-18 | 上海磐启微电子有限公司 | Full-automatic batch test system for high and low temperature performance of wireless image transmission product |
| CN115357067B (en) * | 2022-08-26 | 2024-05-03 | 上海磐启微电子有限公司 | Full-automatic batch test system for high-low temperature performance of wireless image transmission product |
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