CN104539383A - Real-time pulse signal power capturing device and implement method thereof - Google Patents

Abstract

The invention discloses a device for capturing pulse signal power in real time, comprising a radio frequency receiving module, an industrial computer control module, a digital intermediate frequency module connected to the radio frequency receiving module, a local oscillator module, a reference module and an EISA bus communicating with each module The uplink signal of the mobile terminal is mixed twice to a fixed intermediate frequency in the RF receiving module, and then sent to the FPGA through the A/D converter, and the FPGA is controlled by software to realize the real-time capture of the pulse signal power index test. It also discloses a method for realizing real-time capture of pulse signal power. The terminal under test, the terminal comprehensive tester and the device are connected through a power splitter. After the signaling link is established, the terminal under test receives the TPC command sent by the comprehensive tester. Afterwards, the power of the uplink service timeslot changes according to the preset settings. The device starts frame synchronization and determines the moment of signal power adjustment according to the power threshold algorithm, captures and calculates the power value and saves it in the dual-port RAM, and the main control software reads the data.

Description

Real-time capture pulse signal power device and its realization method

technical field

The invention relates to the technical field of mobile communication terminal indicator testing, in particular to a device for capturing pulse signal power in real time and an implementation method thereof.

Background technique

At present, mobile communication terminal test instruments generally test the terminal uplink transmission signal power (signaling/non-signaling mode) according to 3GPP TS34.120/2/3 or TS 36.521-1 and other conformance specifications. For the "radio frequency conformance" terminal test instrument, develop the test case "TPC (Transmit Power Control, terminal uplink transmission power control)" of the application scenario. In the signaling mode, the synchronization signal is provided by the baseband (physical layer); in the non-signaling mode (or without external synchronization signal) When performing "TPC" test on the terminal, if only relying on "power level" trigger to obtain the synchronization signal, it can work normally when the signal is large, but when the signal is small (the signal-to-noise ratio is poor), it will cause false triggering. Sync signal error. Therefore, devices that rely on external synchronous signals to capture pulse signals have poor flexibility and scope of application. In addition, foreign vector signal analyzers generally do not provide power detection functions with real-time automatic capture "graph mode", and can only randomly capture pulse signals by increasing the scan time, but this solution is limited by data storage capacity and cannot flexibly capture any At the same time, the randomly captured graphic display is not convenient for testers to observe the signal and analyze the terminal performance indicators.

Therefore, there is an urgent need to provide a novel device with an adaptive automatic synchronization function and its implementation method to solve the above problems.

Contents of the invention

The technical problem to be solved by the present invention is to provide a device for capturing pulse signal power in real time, which can realize fast and real-time detection of TPC index of mobile terminal without relying on external wireless frame synchronization signal.

In order to solve the above technical problems, a technical solution adopted by the present invention is to provide a real-time capture pulse signal power device, including a radio frequency receiving module, an industrial computer control module, a digital intermediate frequency module connected to the radio frequency receiving module, and a local oscillator module , a reference module, and an EISA bus that communicates with each module. The radio frequency receiving module includes a receiving attenuator, a first local oscillator mixer, a first intermediate frequency bandpass filter, a second local oscillator mixer, and a second The intermediate frequency bandpass filter, the local oscillator module is composed of a phase-locked loop, and its output is connected to the first local oscillator mixer of the radio frequency receiving module. The reference module includes a crystal oscillator and a phase-locked loop connected to the crystal oscillator. The crystal oscillator is connected to the local oscillator module respectively. , the digital intermediate frequency module is connected, the output terminal of the reference module is connected with the second local oscillator mixer of the radio frequency receiving module, the digital intermediate frequency module includes a clock distributor, a data acquisition module connected in sequence, an FPGA, an EISA bus interface, and a clock distributor respectively Connect with data acquisition module and FPGA.

In a preferred embodiment of the present invention, the data acquisition module of the digital intermediate frequency module is connected with the second intermediate frequency bandpass filter of the radio frequency receiving module, and the data acquisition module includes an amplifier connected in sequence, an anti-aliasing filter, an A/ D converter, the FPGA includes a digital down-conversion module, an extraction module, a filter, an effective value detection module, a capture pulse edge module and a power peak search module respectively connected to the output end of the effective value detection module, and a frame synchronization timer. The start capture module, the real-time power storage module, the dual-port RAM, the TPC trigger module and the control logic module connected to the input end of the start capture module, wherein the output ends of the power peak search module and the capture pulse edge module are respectively connected with the frame synchronization timer, The input end of the EISA bus interface is connected to the dual-port RAM, the output end is connected to the TPC trigger module and the control logic module, and the clock distributor is respectively connected to the A/D converter of the data acquisition module and the DCM of the FPGA. The digital intermediate frequency module is the core component of the real-time capture pulse signal power device, which mainly establishes adaptive frame synchronization for the mobile terminal under test, calculates signal power in real time, and captures TPC power variation curves.

In a preferred embodiment of the present invention, the phase-locked loop is composed of a voltage-controlled oscillator, a loop filter, and a phase detector connected end to end.

In a preferred embodiment of the present invention, the crystal oscillator of the reference module is respectively connected with the phase detector of the local oscillator module and the clock distributor of the digital intermediate frequency module. The crystal oscillator provides a 100MHz clock signal for the local oscillator module and a 122.88MHz clock signal for the digital intermediate frequency module.

In a preferred embodiment of the present invention, the industrial computer control module includes a main control module, an interface module, a display module, an operating system, and a switching power supply. The industrial computer control module is the core control center of the real-time capture pulse signal power device, and performs initialization setting, data interaction and software control for each module through the EISA bus.

In order to solve the above technical problems, another technical solution adopted by the present invention is to provide a method for realizing real-time capture of pulse signal power, comprising the following steps:

(1) Use a power divider to connect the terminal comprehensive tester, the terminal under test, and the real-time capture pulse signal power device to each other through a radio frequency cable, and all equipment starts to be powered on and completes initialization settings;

(2) The terminal under test first initiates signaling interaction to the terminal comprehensive tester, and establishes a signaling link;

(3) The terminal comprehensive tester sends a TPC command to maintain the maximum output power to the terminal under test, so that the uplink service time slot power of the terminal under test is always kept constant and in the maximum power state;

(4) The real-time capture pulse signal power device starts the frame synchronization function, completes the time reference synchronization with the signal of the terminal under test, and waits for the power change of the terminal under test;

(5) The terminal comprehensive tester sends the TPC command whose power is adjusted according to the preset step amount to the terminal under test, so that the power of the uplink service time slot of the terminal under test is reduced from the maximum power to The minimum power, and then back to the maximum power, is a complete closed-loop power control process;

(6) The FPGA of the real-time capture pulse signal power device judges the moment of signal power adjustment according to the power threshold algorithm, starts the capture pulse edge module and calculates the power in real time, and saves the final calculated value in the dual-port RAM;

(7) When the closed-loop power control process of the terminal under test ends, the FPGA automatically sets the completion flag, notifies the main control software of the industrial computer control module to read the data in the dual-port RAM, and displays the power of the terminal under test with a graphical interface process of change.

In a preferred embodiment of the present invention, in step (5), the preset step amount is 1dB or 2dB or 3dB.

In a preferred embodiment of the present invention, in step (6), the power threshold algorithm shows the signal power change track curve of the current value for the terminal under test and the signal power change track curve after FPGA delay to maintain correlation, The FPGA internally calculates the optimal power range reduction value and the algorithm for triggering the capture module.

The beneficial effects of the present invention are: the real-time capture pulse signal power device of the present invention has reasonable structure, simple design principle, easy expansion, low cost, highly integrated functions, automatically extracts frame synchronization, and realizes fast and real-time detection of mobile terminal TPC indicators, suitable for It is used to detect the pulse time slot power of terminal transmission signals such as TD-LTE-A/TD-LTE/TD-SCDMA/GSM including time division multiplexing; the method for realizing real-time capture of pulse signals is simpler than the traditional test method software control process , the test efficiency is high, and the requirements for testers are also greatly reduced.

Description of drawings

Fig. 1 is a structural block diagram of a preferred embodiment of the device for capturing pulse signal power in real time according to the present invention.

Fig. 2 is a functional block diagram of the digital intermediate frequency module.

Fig. 3 is a software flow chart of the real-time capture pulse signal power device.

Fig. 4 is a diagram of the usage state of the real-time capture pulse signal power device.

Fig. 5 is a flowchart of a method for realizing real-time capture of pulse signal power.

Fig. 6 is a schematic diagram of the power threshold algorithm.

Fig. 7 is a test waveform diagram of the closed-loop power control (TPC) of the terminal under test.

Detailed ways

The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, so as to define the protection scope of the present invention more clearly.

Please refer to Fig. 1, the embodiment of the present invention comprises:

A device for capturing pulse signal power in real time, comprising a radio frequency receiving module, an industrial computer control module, a digital intermediate frequency module connected to the radio frequency receiving module, a local oscillator module, a reference module and an EISA bus communicating with each module. The radio frequency receiving module includes a receiving attenuator, a first local oscillator mixer, a first intermediate frequency bandpass filter, a second local oscillator mixer, and a second intermediate frequency bandpass filter connected in sequence. The local oscillator module is composed of a phase-locked loop, and its output terminal is connected to the first local oscillator mixer of the radio frequency receiving module. The reference module includes a crystal oscillator and a phase-locked loop connected to the crystal oscillator. The crystal oscillator is respectively connected to the local oscillator module and the digital intermediate frequency module. The output terminal of the reference module is connected to the second local oscillator mixer of the radio frequency receiving module. The digital intermediate frequency module includes a clock distributor, a sequentially connected data acquisition module, FPGA, and an EISA bus interface, and the clock distributor is connected to the data acquisition module and the FPGA respectively.

The phase-locked loop of the local oscillator module is the same as that of the reference module, and consists of a voltage-controlled oscillator, a loop filter, and a phase detector connected end to end. The crystal oscillator of the reference module is connected with the phase detector of the local oscillator module and the clock distributor of the digital intermediate frequency module respectively, and the crystal oscillator provides the clock signal of 10MHz for the phase detector of the reference module and the clock signal of 100MHz for the local oscillator module respectively. Provide 122.88MHz clock signal for the digital intermediate frequency module. The voltage-controlled oscillator of the local oscillator module inputs a 400MHz-6GHz high-frequency carrier to the first local oscillator mixer of the RF receiving module, and the voltage-controlled oscillator of the reference module inputs 1GHz to the second local oscillator mixer of the RF receiving module low frequency carrier. The receiving attenuator of the radio frequency receiving module receives the radio frequency signal of the terminal under test, and enters the first local oscillator mixer with the high-frequency carrier wave emitted by the local oscillator module, and then outputs a mixed frequency signal of 846.4MHz, which passes through the first intermediate frequency bandpass After filtering by the filter, the low-frequency carrier transmitted by the reference module enters the second local oscillator mixer, and then outputs an intermediate frequency signal of 153.6MHz, which is filtered by the second intermediate frequency bandpass filter and sent to the data acquisition module of the digital intermediate frequency module .

In conjunction with Fig. 2, the data acquisition module of the digital intermediate frequency module includes sequentially connected amplifiers, anti-aliasing filters, and A/D converters, and the FPGA includes sequentially connected digital down-conversion modules, extraction modules, filters, and effective value detection Module, capture pulse edge module and power peak search module respectively connected to the output terminal of the RMS detection module, frame synchronization timer, start capture module, real-time power storage module, dual-port RAM, TPC trigger connected to the input terminal of the start capture module modules and control logic modules. Among them, the output terminals of the power peak search module and the capture pulse edge module are respectively connected with the frame synchronization timer, the input terminal of the EISA bus interface is connected with the dual-port RAM, the output terminal is connected with the TPC trigger module and the control logic module, and the clock distributor is respectively connected with the The A/D converter of the data acquisition module and the DCM of the FPGA are connected. The digital intermediate frequency module is the core component of the real-time capture pulse signal power device, which mainly establishes adaptive frame synchronization for the mobile terminal under test, calculates signal power in real time, and captures TPC power variation curves. The FPGA is the core component of the digital intermediate frequency module. The output signal of the radio frequency receiving module is amplified, filtered, and converted from analog to digital and then transmitted to the FPGA for processing. The VHDL top-down design is adopted inside the FPGA to realize digital down-conversion, digital extraction, digital Filtering, effective value (RMS) detection, power peak search, capture pulse edge, frame synchronization, TPC trigger, real-time power capture and storage, logic control. Among them, digital down-conversion, digital extraction, digital filtering, effective value detection, power peak search and capture pulse edge are pipeline operations, and the data is constantly refreshed in real time, waiting for the software to send instructions to start the frame synchronization process. According to the capture pulse edge ( The signal trigger time) resets the internal timer at the arrival time, and realizes the synchronization process of any periodic pulse. After initializing the preset TPC template, wait for the software instruction (matching with the terminal comprehensive tester), accurately locate the position of the pulse time slot according to the internal timer, capture the effective pulse and perform root mean square (integration) processing on it, and convert the processed power in real time Save it to the dual-port RAM, and notify the main control software to read the data in due course.

The industrial computer control module is composed of main control software, hardware industrial computer, bus main board, etc., including a main control module, an interface module, a display module, an operating system, and a switching power supply. The industrial computer control module is the core control center of the real-time capture pulse signal power device, and performs initialization setting, data interaction and software control for each module through the EISA bus. The radio frequency receiving module, local oscillator module, reference module and digital intermediate frequency module all need the industrial computer control module software initialization to configure parameters through the EISA bus. The data signal flow direction of the whole real-time capture pulse signal power device is the terminal under test, radio frequency receiving module, digital intermediate frequency module, industrial computer control module, and the control signal flow direction is industrial computer control module, radio frequency receiving module and local oscillator module, reference module and Digital IF module.

The main control software flow chart of the real-time capture pulse signal power device is shown in Figure 3, which mainly completes hardware control, information processing, interactive processing, man-machine interface and other contents. According to the standard modular design method, it mainly includes the following parts:

(1) Hardware initialization: the software operation of power-on initialization of the hardware.

(2) DDS/FPGA initialization: complete the initialization configuration of multiple DDS (direct digital frequency synthesis) and FPGA internal sub-modules through the call of the main control software when starting up.

(3) Hardware module self-inspection: the self-inspection software and the instrument hardware self-inspection circuit complete the self-inspection of the main hardware modules of the device together, and report the self-inspection result in real time. The calibration software includes three parts: power-on calibration, user calibration and device self-calibration, which is an important measure for the device to achieve stable indicators. Through the calibration of the hardware module, it can achieve the best working condition.

(4) Module initial control: According to the test target, the parameter control of the hardware circuit state is completed, which mainly includes instrument keyboard control and module control, specifically including:

Synthetic LO control: It mainly completes the frequency control of the synthetic LO, and sends control commands to generate the correct LO frequency according to the air interface access frequency of terminals in different modes to ensure the correctness of RF reception;

RF receiving control: complete the power and frequency control of the RF channel, channel switch control, etc.;

Digital intermediate frequency control: mainly complete the control of high-speed A/D converter and FPGA digital processing, etc.;

Real-time analysis control: complete the parameter control of FPGA's real-time frame synchronization, timer and TPC template;

The module control is mainly the control of the FPGA by the main control software, and the real-time detection and storage of the real-time capture pulse signal power device is completely completed by the hardware FPGA. The software sub-flow in the module control comprises: at first main control software clears all sign bits, starts the frame synchronous timer of FPGA, and carries out trigger delay configuration to TPC trigger module, guarantees that the terminal under test is in various steps (1dB , 2dB or 3dB), the position of the change point of the TPC signal from the maximum value to the beginning of the decrease is always kept fixed, which truly shows the whole process of the power change of the terminal under test, and then the TPC command is sent, and the TPC test process begins. When the main control software detects the completion flag bit, it means that a closed-loop power control process ends, that is, the test data in the dual-port RAM is read.

(5) Data acquisition and processing, interface read and write control, and measurement result display: the three are the man-machine interface part, which completes the display processing of the whole machine, measurement interaction processing, and provides comprehensive help information.

When in use, please refer to Figure 4, the device for capturing the pulse signal power in real time is located between the terminal under test and the radio frequency mobile terminal comprehensive tester, and the active splitter is interconnected through a radio frequency cable, that is, the terminal under test and the terminal comprehensive tester establish signaling The loop captures the pulse signal power in real time. The device is in the monitoring and detection position, and the uplink transmission signal of the terminal under test is output to the device through the power divider. The device does not need an external trigger signal, and can detect, capture and store uplink service signals of a mobile terminal (such as a mobile phone) in real time.

The real-time capture pulse signal power device has reasonable structure, simple design principle, easy expansion, low cost, highly integrated functions, automatic extraction of frame synchronization, and fast real-time detection of TPC indicators of mobile terminals, and is suitable for TD-LTE including time division multiplexing - Detection of pulse time slot power of terminal transmission signals such as A/TD-LTE/TD-SCDMA/GSM.

Real-time capture of pulse signal power can be achieved by utilizing the device for capturing pulse signal power in real time. The method for realizing real-time capture of pulse signal power is described in detail below in conjunction with FIGS. 5 and 6 , which includes the following steps:

(1) Use a power divider to connect the terminal comprehensive tester, the terminal under test, and the real-time capture pulse signal power device to each other through a radio frequency cable, and all equipment starts to be powered on and completes initialization settings;

(2) The terminal under test first initiates signaling interactions such as call and registration to the terminal comprehensive tester, and establishes a signaling link;

(3) The terminal comprehensive tester sends a TPC command to maintain the maximum output power to the terminal under test, so that the uplink service time slot power of the terminal under test is always kept constant and in the maximum power state;

(4) The main control software of the real-time capture pulse signal power device first clears the various flag bits of the FPGA and starts the frame synchronization function, and then the FPGA will automatically identify the real uplink time slot power signal (automatically distinguish noise or interference signal), and perform power Peak search and start the frame synchronization timer to complete the time reference synchronization between the device and the terminal signal under test. The synchronization signal is a periodic signal (5ms in TD-SCDMA mode, 10ms in TD-LTE/TD-LTE-Advanced mode), which can be used as a synchronization trigger signal for the closed-loop power control of the terminal under test, waiting for the power of the terminal under test Variety;

(5) The terminal comprehensive tester sends the TPC command whose power is adjusted according to the preset step amount to the terminal under test, so that the power of the uplink service time slot of the terminal under test starts from the maximum power (such as +39dBm) to the minimum power (such as -80dBm), followed by reverse adjustment, and then back to the maximum power according to the same step amount, and finally maintain the maximum power state, which is a complete closed-loop power control process;

(6) The FPGA of the real-time capture pulse signal power device accurately determines the moment of signal power adjustment according to the power threshold algorithm, immediately starts the capture pulse edge module and calculates the power in real time, and saves the final calculated value (the output of the RMS detection module) to the dual port in RAM;

(7) When the closed-loop power control process of the terminal under test ends, the FPGA automatically sets the completion flag, notifies the main control software of the industrial computer control module to read the data in the dual-port RAM, and the main control software performs logarithmic mapping on the data, Realize the conversion from linear value to dB value, and configure the trigger delay of the TPC trigger module at the same time, and finally display the data in a graphical interface to show the process of the power change of the terminal under test.

In step (5), the preset step amount is 1dB or 2dB or 3dB. Taking 1dB as an example, please refer to Figure 5. This figure takes the common TPC test process in the terminal comprehensive tester as an example, describes the real-time power changes of the tested terminal in 1dB steps, and shows the operation steps of the internal functional modules of the FPGA. It includes: pre-synchronization of the uplink time slots, starting the internal timer after the synchronization is successful, and starts real-time monitoring of the power of the uplink time slots at this time, judges whether to start the storage function according to the preset trigger delay configuration, and saves the power of the uplink time slots in real time. After the closed-loop power control process is over, the data is sent to the main control software in real time through the dual-port RAM, and the main control software reads the test power sequence and displays the output power value.

In step (6), the power threshold algorithm is explained in detail in conjunction with Fig. 6: under the signal power curve when the terminal under test changes with a step of 1dB, there are two curves, the first one showing the current value The signal power change track curve (as shown in Figure 6, A), the second is the signal power change track curve of the historical moment value (as shown in Figure 6, B), that is, in terms of time, it is "the current value of "Signal change track power curve" is obtained through the trigger delay configuration of the TPC trigger module. When the preset step amount of the terminal comprehensive tester is different, in order to ensure that the change point of the TPC signal from the maximum value to the beginning of the decrease is always maintained The position is fixed, and it truly shows the whole process of the power change of the terminal under test, and the configured delay time will be different; in terms of amplitude, it is the "signal change track power curve of the current value" after being scaled down (the fixed-point number is shifted to the right by 2 bits, etc. The effective power is reduced by 6dB, which is obtained by testing and calculating the best power amplitude reduction value inside the FPGA); similarly, the two curves before and after achieve the correlation in the amplitude value (the signal power change track of the current moment value When the curve increases/decreases, the signal power change trajectory curve of the historical moment value will also increase/decrease). Therefore, the two curves have an intersection point in time (as shown in C in Figure 6). At this time, it can be judged by using the comparison circuit inside the FPGA chip, that is, we define this intersection point as the signal power change track of the current moment value The trigger signal when the curve starts to decrease and falls below the curve of the signal power change trace of the historical moment value. The trigger signal realizes automatic correlation with the input signal, and at the same time, the signal is also used to instruct the start-up capture module to start working.

Taking a complete TPC test process as an example to describe the method for realizing real-time capture of pulse signal power, please refer to Figure 7. In the figure, a group of pulse signals are signals sent by the terminal uplink. When the terminal comprehensive tester sends After the TPC power maintains the maximum command, the device can detect the periodic pulse signal power as shown in a in Figure 7 in real time, and obtain a straight power change trajectory after RMS detection (as shown in b in Figure 7 At this time, when the terminal comprehensive tester sends the TPC power adjustment command (the power decreases first and then increases) to the terminal under test, the terminal under test responds immediately and at the same time according to the agreed step (1dB or 2dB or ) to adjust the power value of the transmitted uplink signal. Similarly, the device can still monitor the change of the pulse in real time, and update the drawn power change track curve in real time. Based on the parallel working principle of FPGA, after the input pulse power signal passes through the D flip-flop inside the FPGA chip, the pulse signal and its power change trajectory curve are delayed for a period of time at the same time. The time t (data delay) can be determined by the main control software through the TPC trigger module. configure. The moment when the signal power starts to decrease is judged by the FPGA power threshold algorithm. At this time, activate the start-up capture module, save the value of the delayed power RMS value change track curve (as shown in c in Figure 7) to the dual-port RAM, and wait for the pulse After the power changes to the maximum (the closed-loop power control ends at this time), notify the main control software to read the test data.

The method for realizing the real-time capture of the pulse signal is simple compared with the traditional test mode software control process, and can realize fast real-time detection of the TPC index of the mobile terminal without relying on the external wireless frame synchronization signal, the test efficiency is high, and the requirements for the testers are also limited. Great reduction.

The above is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related technologies fields, all of which are equally included in the scope of patent protection of the present invention.

Claims (8)

1. a real-time capture pulse signal power device, comprising a radio frequency receiving module, an industrial computer control module, is characterized in that, also includes a digital intermediate frequency module, a local oscillator module, a reference module and an interaction with each module respectively connected to the radio frequency receiving module The EISA bus for communication, the radio frequency receiving module includes a receiving attenuator, a first local oscillator mixer, a first intermediate frequency band-pass filter, a second local oscillator mixer, a second intermediate frequency band-pass filter, and a local oscillator The module is composed of a phase-locked loop, whose output is connected to the first local oscillator mixer of the RF receiving module. The reference module includes a crystal oscillator and a phase-locked loop connected to the crystal oscillator. The crystal oscillator is connected to the local oscillator module and the digital intermediate frequency module respectively. The reference module The output end of the radio frequency receiving module is connected with the second local oscillator mixer, and the digital intermediate frequency module includes a clock distributor, a data acquisition module connected in sequence, an FPGA, and an EISA bus interface, and the clock distributor is connected with the data acquisition module and the FPGA respectively. 2. real-time capture pulse signal power device according to claim 1, is characterized in that, the data acquisition module of described digital intermediate frequency module is connected with the second intermediate frequency band-pass filter of radio frequency receiving module, and data acquisition module comprises sequentially connected The amplifier, the anti-aliasing filter, the A/D converter, and the FPGA include a digital down-conversion module, an extraction module, a filter, an effective value detection module, a capture pulse edge module connected to the output end of the effective value detection module, and Power peak search module, frame synchronization timer, start capture module, real-time power storage module, dual-port RAM, TPC trigger module and control logic module connected to the input end of start capture module, wherein the power peak search module and capture pulse edge module The output ends are respectively connected to the frame synchronization timer, the input end of the EISA bus interface is connected to the dual-port RAM, the output end is connected to the TPC trigger module and the control logic module, and the clock distributor is respectively connected to the A/D converter of the data acquisition module, FPGA connected to the DCM. 3. The device for capturing pulse signal power in real time according to claim 1, wherein the phase-locked loop is composed of a voltage-controlled oscillator, a loop filter, and a phase detector connected end to end. 4. The device for capturing pulse signal power in real time according to claim 1, wherein the crystal oscillator of the reference module is connected to the phase detector of the local oscillator module and the clock distributor of the digital intermediate frequency module respectively. 5. The power device for capturing pulse signals in real time according to claim 1, wherein the control module of the industrial computer includes a main control module, an interface module, a display module, an operating system, and a switching power supply. 6. based on the method for capturing the pulse signal power in real time of the described real-time capture pulse signal power device of claim 1, comprising the following steps: (1) Use a power divider to connect the terminal comprehensive tester, the terminal under test, and the real-time capture pulse signal power device to each other through a radio frequency cable, and all equipment starts to be powered on and completes initialization settings; (2) The terminal under test first initiates signaling interaction to the terminal comprehensive tester, and establishes a signaling link; (3) The terminal comprehensive tester sends a TPC command to maintain the maximum output power to the terminal under test, so that the uplink service time slot power of the terminal under test is always kept constant and in the maximum power state; (4) The real-time capture pulse signal power device starts the frame synchronization function, completes the time reference synchronization with the signal of the terminal under test, and waits for the power change of the terminal under test; (5) The terminal comprehensive tester sends the TPC command whose power is adjusted according to the preset step amount to the terminal under test, so that the power of the uplink service time slot of the terminal under test is reduced from the maximum power to The minimum power, and then back to the maximum power, is a complete closed-loop power control process; (6) The FPGA of the real-time capture pulse signal power device judges the moment of signal power adjustment according to the power threshold algorithm, starts the capture pulse edge module and calculates the power in real time, and saves the final calculated value in the dual-port RAM; (7) When the closed-loop power control process of the terminal under test ends, the FPGA automatically sets the completion flag, notifies the main control software of the industrial computer control module to read the data in the dual-port RAM, and displays the power of the terminal under test with a graphical interface process of change. 7. The method for realizing real-time capture of pulse signal power according to claim 6, characterized in that, in step (5), the preset step amount is 1dB or 2dB or 3dB. 8. the method for realizing real-time capture of pulse signal power according to claim 6 is characterized in that, in step (6), the power threshold algorithm shows the signal power change track curve of the current value for the terminal under test and the FPGA delay time In order to maintain the correlation of the final signal power change trajectory curve, the FPGA internally calculates the optimal power amplitude reduction value and the algorithm for triggering the triggering time of the capture module.