CN104539383A - Real-time pulse signal power capturing device and implement method thereof - Google Patents
Real-time pulse signal power capturing device and implement method thereof Download PDFInfo
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Abstract
The invention discloses a real-time pulse signal power capturing device which comprises a radio frequency receiving module, an industrial personal computer control module, a digital intermediate-frequency module, a local oscillator module, a reference module and an EISA bus, wherein the digital intermediate-frequency module, the local oscillator module and the reference module are connected with the radio frequency receiving module, and the EISA bus is in communication with the modules. An uplink signal of a mobile terminal is converted into fixed intermediate frequency through twice of frequency mixing in the radio frequency receiving module and then transmitted to an FPGA through an A/D converter, and the FPGA is controlled through software to achieve real-time pulse signal power capturing index testing. The invention further discloses a real-time pulse signal power capturing method. A tested terminal, a terminal comprehensive measuring device and the real-time pulse signal power capturing device are connected through a power divider, and after a signaling link is built, the tested terminal receives a TPC command sent by the comprehensive measuring device so that uplink service time slot power can change according to preliminary settings. Start frames of the real-time pulse signal power capturing device are synchronized, signal power adjusting moment is judged according to a power threshold algorithm, a power value is captured, calculated and stored in a double-port RAM, and data are read through master control software.
Description
Technical field
The present invention relates to mobile communication terminal index test technical field, particularly relate to one and catch pulse signal power device and its implementation in real time.
Background technology
At present, mobile communication terminal test instrumentation is tested according to the conformity specification such as 3GPP TS34.120/2/3 or TS 36.521-1 terminal uplink transmit signal power (signaling/non-signaling pattern) test is general.For " RF consistency " terminal test instrument, the test case " TPC (Transmit Power Control; terminal uplink transmitting power controls) " of Application and Development scene, under signaling mode, synchronizing signal is provided by base band (physical layer); Under non-signaling pattern (or without outer synchronous signal) to terminal carry out " TPC " test time, if only rely on " power level " to trigger obtain synchronizing signal, can be working properly during large-signal, but during small-signal, (poor signal to noise) can false triggering cause synchronizing signal to be made mistakes.Therefore, dependence outer synchronous signal carries out the device that pulse signal is caught, and flexibility and the scope of application are all poor.In addition, external VSA does not generally provide the power detection having and automatically catch " figure ray mode " in real time, pulse signal can only be caught at random sweep time by strengthening, but this scheme is limited by data storage capacity restriction can not catch random time length signals flexibly, figure display also inconvenient tester's observation signal and the analysing terminal performance index of simultaneously catching at random.
Therefore need badly and provide a kind of novel device with self adaptation automatic synchronizing function and its implementation to solve the problems referred to above.
Summary of the invention
Technical problem to be solved by this invention is to provide one and catches pulse signal power device in real time, can not rely on external wireless frame synchronizing signal and realizes detecting in real time fast mobile terminal TPC index.
For solving the problems of the technologies described above, the technical scheme that the present invention adopts is: provide one to catch pulse signal power device in real time, comprise Receiver Module, industrial computer control module, the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and the eisa bus intercomed mutually with each module, Receiver Module comprises the receiving attenuation device be connected successively, first self oscillating mixer, first if bandpas filter, second self oscillating mixer, second if bandpas filter, local oscillator module is made up of phase-locked loop, and its output connects the first self oscillating mixer of Receiver Module, and referrer module comprises crystal oscillator, the phase-locked loop be connected with crystal oscillator, crystal oscillator respectively with local oscillator module, data intermediate frequency module is connected, and the output of referrer module is connected with the second self oscillating mixer of Receiver Module, and data intermediate frequency module comprises clock distributor, the data acquisition module be connected successively, FPGA, eisa bus interface, clock distributor respectively with data acquisition module, FPGA is connected.
In a preferred embodiment of the present invention, the data acquisition module of described data intermediate frequency module is connected with the second if bandpas filter of Receiver Module, data acquisition module comprises the amplifier connected successively, frequency overlapped-resistable filter, A/D converter, FPGA comprises the Digital Down Converter Module be connected successively, abstraction module, filter, effective value detection module, what be connected with effective value detection module output respectively catches pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, the TPC trigger module be connected with startup trapping module input and control logic module, wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, clock distributor respectively with the A/D converter of data acquisition module, the DCM of FPGA is connected.Described data intermediate frequency module is described core component of catching pulse signal power device in real time, is mainly tested mobile terminal and sets up adaptive frame synchronization, in real time calculating signal power and catch TPC changed power curve.
In a preferred embodiment of the present invention, described phase-locked loop is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.
In a preferred embodiment of the present invention, the crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively.Crystal oscillator is respectively local oscillator module and provides the clock signal of 100MHz, provides the clock signal of 122.88MHz for data intermediate frequency module.
In a preferred embodiment of the present invention, described industrial computer control module comprises main control module, interface module, display module, operating system, Switching Power Supply.Described industrial computer control module is the core control axis of catching pulse signal power device in real time, carries out Initialize installation, data interaction and software control by eisa bus to each module.
For solving the problems of the technologies described above, another technical solution used in the present invention is: provide a kind of method realizing catching in real time pulse signal power, comprise the following steps:
(1) utilize power splitter by terminal comprehensive test instrument, measured terminal, catch pulse signal power device in real time and be interconnected by radio frequency cable, all devices starts to be energized and completes Initialize installation;
(2) first measured terminal initiates Signalling exchange to terminal comprehensive test instrument, and sets up signaling link;
(3) terminal comprehensive test instrument sends to measured terminal and keeps the maximum TPC command of power output, makes the uplink service time slot power of measured terminal remain constant and is maximum power state;
(4) catch pulse signal power device in real time and start frame synchronization function, complete synchronous with the time reference of measured terminal signal, wait for the changed power of measured terminal;
(5) terminal comprehensive test instrument to measured terminal transmitted power according to pre-set stepping-in amount adjustment TPC command, make the uplink service time slot power of measured terminal start respectively to be reduced to minimum power from maximum power, to go up to maximum power again with the stepping-in amount in TPC command, be once complete close-loop power control process;
(6) in the moment that the FPGA catching pulse signal power device in real time adjusts according to power threshold algorithm decision signal power, start and catch pulse along module also real-time rated output, final calculated value is saved in dual port RAM;
(7) at the end of the close-loop power control process of measured terminal, FPGA Lookup protocol complement mark position, the main control software of notice industrial computer control module reads the data in dual port RAM, and with the process of graphic interface display measured terminal changed power.
In a preferred embodiment of the present invention, in step (5), the stepping-in amount pre-set is 1dB or 2dB or 3dB.
In a preferred embodiment of the present invention, in step (6), power threshold algorithm be the signal power variations geometric locus of measured terminal display currency with signal power variations geometric locus after FPGA time delay for keep correlation, FPGA internal calculation goes out the algorithm of the trigger instants of best power amplitude decreasing value and startup trapping module.
The invention has the beneficial effects as follows: of the present inventionly catch that pulse signal power device is rational in infrastructure in real time, design principle is simple, be easy to expansion, with low cost, function height is integrated, automatic extraction frame synchronization, realize detecting in real time fast mobile terminal TPC index, be applicable to the detection comprising the terminal transmission signal pulse time slot powers such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM; The method that pulse signal is caught in described realization is in real time simple relative to traditional test mode software control flow process, and testing efficiency is high, also has substantial degradation to the requirement of tester simultaneously.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the present invention catches pulse signal power device one preferred embodiment in real time.
Fig. 2 is the theory diagram of described data intermediate frequency module.
Fig. 3 is described software flow pattern of catching pulse signal power device in real time.
Fig. 4 is the described using state figure catching pulse signal power device in real time.
Fig. 5 is the method flow diagram realizing catching in real time pulse signal power.
Fig. 6 is the schematic diagram of described power threshold algorithm.
Fig. 7 is measured terminal close-loop power control (TPC) test waveform figure.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described in detail, can be easier to make advantages and features of the invention be readily appreciated by one skilled in the art, thus more explicit defining is made to protection scope of the present invention.
Refer to Fig. 1, the embodiment of the present invention comprises:
One catches pulse signal power device in real time, the eisa bus comprising Receiver Module, industrial computer control module, the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and intercom mutually with each module.Receiver Module comprises the receiving attenuation device, the first self oscillating mixer, the first if bandpas filter, the second self oscillating mixer, the second if bandpas filter that are connected successively.Local oscillator module is made up of phase-locked loop, and its output connects the first self oscillating mixer of Receiver Module.The phase-locked loop that referrer module comprises crystal oscillator, is connected with crystal oscillator, crystal oscillator is connected with local oscillator module, data intermediate frequency module respectively, and the output of referrer module is connected with the second self oscillating mixer of Receiver Module.Data acquisition module, FPGA, eisa bus interface that data intermediate frequency module comprises clock distributor, is connected successively, clock distributor is connected with data acquisition module, FPGA respectively.
Described local oscillator module forms identical with the phase-locked loop of referrer module, is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.The crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively, the clock signal that the phase discriminator that crystal oscillator is respectively referrer module provides the clock signal of 10MHz, provides the clock signal of 100MHz, provides 122.88MHz for data intermediate frequency module for local oscillator module.The voltage-controlled vibrator of local oscillator module is to the high frequency carrier of first self oscillating mixer input 400MHz ~ 6GHz of Receiver Module, and the voltage-controlled vibrator of referrer module is to the low frequency carrier signal of the second self oscillating mixer input 1GHz of Receiver Module.The receiving attenuation device of described Receiver Module receives the radiofrequency signal of measured terminal, the high frequency carrier launched with local oscillator module enters the first self oscillating mixer, export the mixed frequency signal of 846.4MHz subsequently, after the filtering of the first if bandpas filter, the low frequency carrier signal launched with referrer module enters the second self oscillating mixer, export the intermediate-freuqncy signal of 153.6MHz subsequently, after the filtering of the second if bandpas filter, send into the data acquisition module of data intermediate frequency module.
Composition graphs 2, the data acquisition module of described data intermediate frequency module comprises the amplifier, frequency overlapped-resistable filter, the A/D converter that connect successively, FPGA comprise be connected successively Digital Down Converter Module, abstraction module, filter, effective value detection module, is connected with effective value detection module output respectively catch pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, the TPC trigger module be connected with startup trapping module input and control logic module.Wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, and clock distributor is connected with the A/D converter of data acquisition module, the DCM of FPGA respectively.Described data intermediate frequency module is described core component of catching pulse signal power device in real time, is mainly tested mobile terminal and sets up adaptive frame synchronization, in real time calculating signal power and catch TPC changed power curve.And FPGA is the core component of described data intermediate frequency module, Receiver Module output signal transfers to FPGA process after amplifications, filtering, analog-to-digital conversion, adopt in FPGA inside that VHDL top-down design realizes Digital Down Convert, digital decimation, digital filtering, effective value (RMS) detection, power peak are searched for, catch pulse edge, frame synchronization, TPC triggering, realtime power catch with store, logic control.Wherein, Digital Down Convert, digital decimation, digital filtering, effective value detection, power peak search and catch pulse along being pile line operation, data are ceaselessly refreshing in real time, wait for that software sends instruction and starts frame synchronization process process, to arrive moment reset timer internal along (signal trigger instants) according to catching pulse, realizing any period impulsive synchronization process.Software instruction (mating with terminal comprehensive test instrument) is waited for after the preset TPC template of initialization, according to the accurate position pulse time slot position of timer internal, catch effective impulse and root mean square (integration) process is carried out to it, power after process is saved in dual port RAM in real time, and notifies that main control software reads data in good time.
Described industrial computer control module is made up of main control software, hardware industrial computer, bus mainboard etc., comprises main control module, interface module, display module, operating system, Switching Power Supply.Described industrial computer control module is the core control axis of catching pulse signal power device in real time, carries out Initialize installation, data interaction and software control by eisa bus to each module.Receiver Module, local oscillator module, referrer module and data intermediate frequency module all need industrial computer control module software initialization by eisa bus configuration parameter.Whole data-signal of catching pulse signal power device in real time flows to and is followed successively by measured terminal, Receiver Module, data intermediate frequency module, industrial computer control module, and control signal flows to as industrial computer control module, Receiver Module and local oscillator module, referrer module and data intermediate frequency module.
Described main control software flow chart of catching pulse signal power device in real time as shown in Figure 3, mainly completes the contents such as hardware controls, information processing, interaction process, man-machine interface.By the modular design method of standard, mainly comprise following several part:
(1) hardware initialization: the software operation of the power-up initializing of hardware.
(2) DDS/FPGA initialization: the calling by main control software when starting shooting, completes the initial configuration to the inner each submodule of multiple DDS (direct digital synthesis technique) and FPGA.
(3) hardware module self-inspection: the self-inspection of self-inspection software complete twin installation main hardware module together with instrument hardware self-checking circuit, and real-time report self-detection result.Calibration software comprises start calibration, user's calibration and device self calibration three parts, is the very important measures that device realizes stability index, by the calibration to hardware module, makes it to reach optimum Working.
(4) module initially controls: complete the state modulator to hardware circuit state according to test target, and it mainly comprises, and instrumental keyboard controls, module controls, and concrete comprises:
Synthesis local oscillator controls: the FREQUENCY CONTROL mainly completing synthesis local oscillator, and eat dishes without rice or wine to access frequency according to different mode terminal, sending controling instruction produces correct local frequency, ensures the correctness of radio frequency reception;
Radio frequency reception controls: the power and the FREQUENCY CONTROL that complete radio-frequency channel, channel switch control etc.;
Digital intermediate frequency controls: mainly complete the control of high-speed a/d converter and FPGA digital processing etc.;
Real-time analysis controls: the state modulator completing the realtime frame synchronization to FPGA, timer and TPC template;
Wherein module controls is mainly the control of main control software to FPGA, and described real-time detection and storing of catching pulse signal power device is in real time completed by hardware FPGA completely.Software sub-process in described module controls comprises: first main control software removes all flag bits, start the frame synchronization timing device of FPGA, and trigger delay configuration is carried out to TPC trigger module, ensure that measured terminal is in various stepping-in amount (1dB, 2dB or 3dB) situation, TPC signal from keep maximum to reduce time change point remain that position is fixed, the overall process of true representation measured terminal changed power, then send TPC instruction, TPC test process starts.When main control software detects complement mark position, represent a close-loop power control process and terminate, namely read the test data in dual port RAM.
(5) data acquisition and procession, interface Read-write Catrol, measurement result display: three is man-machine interface portion, completes the Graphics Processing of complete machine, measures interaction process, provides perfect help information.
During use, refer to Fig. 4, described pulse signal power device of catching in real time is between measured terminal and radio frequency mobile terminal comprehensive test instrument, interconnected by radio frequency cable with power splitter, namely measured terminal and terminal comprehensive test instrument are set up signaling loop and are caught pulse signal power device in real time and be in and monitor and detection position, and measured terminal is up to transmit and export this device to through power splitter.This device does not need outer triggering signal, can detect in real time, catch and memory mobile terminal (such as mobile phone) uplink service signal.
Describedly catch that pulse signal power device is rational in infrastructure in real time, design principle is simple, be easy to expansion, with low cost, function height is integrated, automatic extraction frame synchronization, realize detecting in real time fast mobile terminal TPC index, be applicable to the detection comprising the terminal transmission signal pulse time slot powers such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM.
Utilize described pulse signal power device of catching in real time can realize catching pulse signal power in real time, be described in detail the method realizing catching in real time pulse signal power below in conjunction with Fig. 5 and Fig. 6, it comprises the following steps:
(1) utilize power splitter by terminal comprehensive test instrument, measured terminal, catch pulse signal power device in real time and be interconnected by radio frequency cable, all devices starts to be energized and completes Initialize installation;
(2) measured terminal first make a call to terminal comprehensive test instrument, the Signalling exchange such as registration, and set up signaling link;
(3) terminal comprehensive test instrument sends to measured terminal and keeps the maximum TPC command of power output, makes the uplink service time slot power of measured terminal remain constant and is maximum power state;
(4) first the main control software of catching pulse signal power device is in real time removed the various flag bit of FPGA and starts frame synchronization function, FPGA will the real ascending time slot power signal of automatic discrimination (automatic distinguishing noise or interference signal) afterwards, carry out power peak search and start frame synchronization timing device, complete cost apparatus is synchronous with the time reference of measured terminal signal.This synchronizing signal is cyclical signal (under TD-SCDMA pattern for be 10ms under 5ms, TD-LTE/TD-LTE-Advanced pattern), can be used as the synchronous triggering signal of measured terminal close-loop power control, waits for the changed power of measured terminal;
(5) terminal comprehensive test instrument to measured terminal transmitted power according to pre-set stepping-in amount adjustment TPC command, the uplink service time slot power of measured terminal is made to start respectively to be reduced to minimum power (as-80dBm) from maximum power (as+39dBm) with the stepping-in amount in TPC command, and then oppositely adjust, go up again to maximum power according to identical stepping-in amount, finally keep maximum power state, be once complete close-loop power control process;
(6) FPGA of pulse signal power device is caught in real time according to the moment of the accurate decision signal power adjustment of power threshold algorithm, start immediately and catch pulse along module also real-time rated output, final calculated value (output of effective value detection module) is saved in dual port RAM;
(7) at the end of the close-loop power control process of measured terminal, FPGA Lookup protocol complement mark position, the main control software of notice industrial computer control module reads the data in dual port RAM, main control software carries out logarithmic mapping data, realize the conversion of linear value to dB value, carry out trigger delay configuration to TPC trigger module, data are with the process of graphic interface display measured terminal changed power the most at last simultaneously.
In step (5), described in the stepping-in amount that pre-sets be 1dB or 2dB or 3dB.For 1dB, refer to Fig. 5, this figure is for TPC testing process common in terminal comprehensive test instrument, measured terminal is described with the power real-time change situation of 1dB stepping-in amount, show the operating procedure of FPGA inner function module, it comprises: ascending time slot is synchronous in advance, timer internal is started after synchronous success, now start Real-Time Monitoring ascending time slot power, whether the trigger delay configuration determination according to pre-setting starts memory function, and preserve ascending time slot power in real time, by dual port RAM, data are sent in real time to main control software after this time close-loop power control process terminates, main control software reads measured power sequence and display translation performance number.
In step (6), described power threshold algorithm composition graphs 6 is explained in detail: below the signal power curve when measured terminal changes with the stepping-in amount of 1dB, there are two curves, Article 1, for showing the signal power variations geometric locus (as shown in A in Fig. 6) of currency, the signal power variations geometric locus (as shown in B in Fig. 6) that Article 2 was worth for the historical juncture, namely say in the time, its " signal intensity track power curve of currency " obtains through the Time delay configuration of TPC trigger module, when the stepping-in amount that terminal comprehensive test instrument pre-sets is different, for ensure TPC signal from keep maximum to reduce time change point remain that position is fixed, the overall process of true representation measured terminal changed power, the delay time of configuration can be different, in amplitude, it is " the signal intensity track power curve of currency ", and (fixed-point number moves to right 2bit through scaled, equivalent power reduces 6dB, and this numerical value is the best power amplitude decreasing value gone out through test and FPGA internal calculation) obtain, in like manner two, front and back curve achieves the correlation (when the signal power variations geometric locus of current time value raises/reduces, the signal power variations geometric locus of historical juncture value also and then can raise/reduce) on amplification value.Therefore, article two, curve just creates intersection point (as shown in C in Fig. 6) in time, now, utilize the comparison circuit of fpga chip inside just can differentiate, namely we define this intersection point is that the signal power variations geometric locus of current time value starts to reduce, and triggering signal time below the signal power variations geometric locus dropping to historical juncture value.This triggering signal achieves auto-associating input signal, simultaneously this signal be also used to indicate start trapping module start working.
For once complete TPC test process, the method that pulse signal power is caught in described realization is in real time described, refer to Fig. 7, in figure, set of pulses signal is the signal that terminal uplink sends, after terminal comprehensive test instrument sends TPC power maintenance maximization order to measured terminal, this device can detect the periodic pulse signal power as shown in a in Fig. 7 in real time, draws a straight changed power trajectory (as shown in b in Fig. 7) after RMS detection; Now, after terminal comprehensive test instrument makes (power first diminishes and becomes large afterwards) to the adjustment of measured terminal transmission TPC power, measured terminal makes an immediate response simultaneously according to the upward signal performance number size of stepping-in amount (1dB or 2dB or 3dB) the adjustment transmission of agreement in advance, in like manner, this device still can real-time monitor the change of this pulse, simultaneously the changed power geometric locus drawn of real-time update.Based on the concurrent working principle of FPGA, input pulse power signal is after the inner d type flip flop of fpga chip, pulse signal and its changed power geometric locus postpone a period of time simultaneously, and this time t (data delay) can be configured by TPC trigger module by main control software.Judge that signal power starts the moment of reducing by FPGA power threshold algorithm, now activate and start trapping module, power RMS value variation track curve (as shown in c in Fig. 7) numerical value after postponing is saved in dual port RAM, wait for pulse power change to maximization after (now close-loop power control terminates), notice main control software read away this test data.
The method that pulse signal is caught in described realization is in real time simple relative to traditional test mode software control flow process, do not rely on external wireless frame synchronizing signal can realize detecting in real time fast mobile terminal TPC index, testing efficiency is high, also has substantial degradation to the requirement of tester simultaneously.
The foregoing is only embodiments of the invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (8)
1. catch pulse signal power device in real time for one kind, comprise Receiver Module, industrial computer control module, it is characterized in that, also comprise the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and the eisa bus intercomed mutually with each module, Receiver Module comprises the receiving attenuation device be connected successively, first self oscillating mixer, first if bandpas filter, second self oscillating mixer, second if bandpas filter, local oscillator module is made up of phase-locked loop, its output connects the first self oscillating mixer of Receiver Module, referrer module comprises crystal oscillator, the phase-locked loop be connected with crystal oscillator, crystal oscillator respectively with local oscillator module, data intermediate frequency module is connected, the output of referrer module is connected with the second self oscillating mixer of Receiver Module, data intermediate frequency module comprises clock distributor, the data acquisition module be connected successively, FPGA, eisa bus interface, clock distributor respectively with data acquisition module, FPGA is connected.
2. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, the data acquisition module of described data intermediate frequency module is connected with the second if bandpas filter of Receiver Module, and data acquisition module comprises the amplifier connected successively, frequency overlapped-resistable filter, A/D converter, FPGA comprises the Digital Down Converter Module be connected successively, abstraction module, filter, effective value detection module, what be connected with effective value detection module output respectively catches pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, with start the TPC trigger module and control logic module that trapping module input is connected, wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, clock distributor respectively with the A/D converter of data acquisition module, the DCM of FPGA is connected.
3. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, described phase-locked loop is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.
4. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, the crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively.
5. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, described industrial computer control module comprises main control module, interface module, display module, operating system, Switching Power Supply.
6. catch the method for pulse signal power based on the realization of catching pulse signal power device described in claim 1 in real time in real time, comprise the following steps:
(1) utilize power splitter by terminal comprehensive test instrument, measured terminal, catch pulse signal power device in real time and be interconnected by radio frequency cable, all devices starts to be energized and completes Initialize installation;
(2) first measured terminal initiates Signalling exchange to terminal comprehensive test instrument, and sets up signaling link;
(3) terminal comprehensive test instrument sends to measured terminal and keeps the maximum TPC command of power output, makes the uplink service time slot power of measured terminal remain constant and is maximum power state;
(4) catch pulse signal power device in real time and start frame synchronization function, complete synchronous with the time reference of measured terminal signal, wait for the changed power of measured terminal;
(5) terminal comprehensive test instrument to measured terminal transmitted power according to pre-set stepping-in amount adjustment TPC command, make the uplink service time slot power of measured terminal start respectively to be reduced to minimum power from maximum power, to go up to maximum power again with the stepping-in amount in TPC command, be once complete close-loop power control process;
(6) in the moment that the FPGA catching pulse signal power device in real time adjusts according to power threshold algorithm decision signal power, start and catch pulse along module also real-time rated output, final calculated value is saved in dual port RAM;
(7) at the end of the close-loop power control process of measured terminal, FPGA Lookup protocol complement mark position, the main control software of notice industrial computer control module reads the data in dual port RAM, and with the process of graphic interface display measured terminal changed power.
7. the method for pulse signal power is caught in realization according to claim 6 in real time, it is characterized in that, in step (5), the stepping-in amount pre-set is 1dB or 2dB or 3dB.
8. the method for pulse signal power is caught in realization according to claim 6 in real time, it is characterized in that, in step (6), power threshold algorithm be the signal power variations geometric locus of measured terminal display currency with signal power variations geometric locus after FPGA time delay for keep correlation, FPGA internal calculation goes out the algorithm of the trigger instants of best power amplitude decreasing value and startup trapping module.
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| CN106375031A (en) * | 2016-08-29 | 2017-02-01 | 广东欧珀移动通信有限公司 | Radio-frequency channel detection method and mobile terminal |
| CN109633579A (en) * | 2018-12-11 | 2019-04-16 | 上海无线电设备研究所 | A kind of fixed intermediate frequency receiving channel calibration signal production method and generation circuit |
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| CN109633579A (en) * | 2018-12-11 | 2019-04-16 | 上海无线电设备研究所 | A kind of fixed intermediate frequency receiving channel calibration signal production method and generation circuit |
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