CN104539383B - Real-time pulse signal power capturing device and implement method thereof - Google Patents
Real-time pulse signal power capturing device and implement method thereof Download PDFInfo
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- CN104539383B CN104539383B CN201410850426.6A CN201410850426A CN104539383B CN 104539383 B CN104539383 B CN 104539383B CN 201410850426 A CN201410850426 A CN 201410850426A CN 104539383 B CN104539383 B CN 104539383B
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Abstract
The invention discloses a real-time pulse signal power capturing device which comprises a radio frequency receiving module, an industrial personal computer control module, a digital intermediate-frequency module, a local oscillator module, a reference module and an EISA bus, wherein the digital intermediate-frequency module, the local oscillator module and the reference module are connected with the radio frequency receiving module, and the EISA bus is in communication with the modules. An uplink signal of a mobile terminal is converted into fixed intermediate frequency through twice of frequency mixing in the radio frequency receiving module and then transmitted to an FPGA through an A/D converter, and the FPGA is controlled through software to achieve real-time pulse signal power capturing index testing. The invention further discloses a real-time pulse signal power capturing method. A tested terminal, a terminal comprehensive measuring device and the real-time pulse signal power capturing device are connected through a power divider, and after a signaling link is built, the tested terminal receives a TPC command sent by the comprehensive measuring device so that uplink service time slot power can change according to preliminary settings. Start frames of the real-time pulse signal power capturing device are synchronized, signal power adjusting moment is judged according to a power threshold algorithm, a power value is captured, calculated and stored in a double-port RAM, and data are read through master control software.
Description
Technical field
The present invention relates to mobile communication terminal index test technical field, more particularly to a kind of capture pulse signal in real time
Power device and its implementation.
Background technology
At present, mobile communication terminal test instrumentation is tested terminal uplink transmission signal power (signaling/non-signaling pattern)
It is general to be tested according to conformity specifications such as 3GPP TS34.120/2/3 or TS 36.521-1.For " RF consistency " eventually
End test instrumentation, test case " TPC (Transmit Power Control, the terminal uplink transmission power of development and application scene
Control) ", synchronizing signal is provided by base band (physical layer) under signaling mode；(or without outer synchronous signal) is right under non-signaling pattern
When terminal carries out " TPC " test, if relying only on " power level " triggering obtains synchronizing signal, can work just during big signal
Often, but during small-signal (poor signal to noise) can false triggering cause synchronizing signal to malfunction.Therefore, horizontal pulse is entered by outer synchronous signal
The device of signal capture, flexibility and the scope of application it is all poor.Additionally, external VSA is not typically provided with real
When automatic capture " figure line pattern " power detection, can only by increase sweep time capture pulse signal, but this at random
The scheme of kind is limited by data storage capacity restriction can not flexibly capture random time length signals, while the figure of random capture shows
Show also inconvenient tester's observation signal and analysing terminal performance indications.
Therefore need a kind of new device with self adaptation automatic synchronizing function of offer and its implementation badly to solve
The problems referred to above.
The content of the invention
The technical problem to be solved is to provide a kind of capture pulse signal power device in real time, can be independent of
Realize to the quick real-time detection of mobile terminal TPC indexs in external wireless frame synchronizing signal.
To solve above-mentioned technical problem, one aspect of the present invention is：A kind of pulse letter of capture in real time is provided
Number power device, including Receiver Module, industrial computer control module, the digital intermediate frequency that is connected with Receiver Module respectively
Module, local oscillator module, referrer module and the eisa bus being in communication with each other with each module, Receiver Module includes being sequentially connected
Receiving attenuation device, the first self oscillating mixer, the first if bandpas filter, the second self oscillating mixer, the second intermediate frequency band logical filter
Ripple device, local oscillator module is made up of phaselocked loop, and its output end connects the first self oscillating mixer of Receiver Module, referrer module bag
The phaselocked loop of crystal oscillator and crystal oscillator connection is included, crystal oscillator is connected respectively with local oscillator module, data intermediate frequency module, the output of referrer module
End is connected with the second self oscillating mixer of Receiver Module, the number that data intermediate frequency module includes clock distributor, is sequentially connected
According to acquisition module, FPGA, eisa bus interface, clock distributor is connected respectively with data acquisition module, FPGA.
In a preferred embodiment of the present invention, the data acquisition module and Receiver Module of the data intermediate frequency module
The second if bandpas filter be connected, data acquisition module include be sequentially connected amplifier, frequency overlapped-resistable filter, A/D turn
Parallel operation, FPGA include be sequentially connected Digital Down Converter Module, abstraction module, wave filter, virtual value detection module, respectively with have
The capture pulse of valid value detection module output end connection is caught along module and power peak search module, frame synchronization timing device, startup
Obtain module, realtime power memory module, dual port RAM and start the TPC trigger modules that are connected of trapping module input and control to patrol
Module is collected, wherein power peak search module is connected respectively along the output end of module with capture pulse with frame synchronization timing device,
The input of eisa bus interface is connected with dual port RAM, output end is connected with TPC trigger modules and control logic module, clock
Distributor A/D converter respectively with data acquisition module, the DCM of FPGA are connected.The data intermediate frequency module is described real-time
The core component of capture pulse signal power device, predominantly tested mobile terminal set up adaptive frame synchronization, calculate letter in real time
Number power simultaneously captures TPC changed power curves.
In a preferred embodiment of the present invention, the phaselocked loop by end to end voltage controlled oscillator, loop filter,
Phase discriminator is constituted.
In a preferred embodiment of the present invention, the crystal oscillator of referrer module phase discriminator, number respectively with local oscillator module
The clock distributor of word ifd module is connected.Crystal oscillator be respectively local oscillator module the clock signal of 100MHz is provided, for digital intermediate frequency
Module provides the clock signal of 122.88MHz.
In a preferred embodiment of the present invention, the industrial computer control module includes main control module, interface module, display
Module, operating system, Switching Power Supply.The industrial computer control module is to capture the core control of pulse signal power device in real time
Maincenter, by eisa bus the control of Initialize installation, data interaction and software is carried out to each module.
To solve above-mentioned technical problem, another technical solution used in the present invention is：A kind of realization capture in real time is provided
The method of pulse signal power, comprises the following steps：
(1) terminal comprehensive test instrument, measured terminal, real-time capture pulse signal power device are passed through into radio frequency electrical using power splitter
Cable is connected with each other, and all devices are initially powered up and complete Initialize installation；
(2) measured terminal initiates Signalling exchange to terminal comprehensive test instrument first, and sets up signaling link；
(3) terminal comprehensive test instrument sends the TPC command for keeping power output maximum to measured terminal, makes the up of measured terminal
Business time-slot power remains constant and for maximum power state；
(4) in real time capture pulse signal power device starts frame synchronization function, completes the time base with measured terminal signal
It is plesiochronous, wait the changed power of measured terminal；
(5) terminal comprehensive test instrument to measured terminal transmit power according to pre-set stepping-in amount adjustment TPC command, make by
Survey terminal uplink service time slot power with the stepping-in amount in TPC command start respectively from peak power be reduced to minimum power,
Go up again to peak power, as once complete close-loop power control process；
(6) in real time the FPGA of capture pulse signal power device according to power threshold algorithm judge signal power adjustment when
Carve, pulse is along module and calculates power in real time to start capture, and final calculated value is saved in dual port RAM；
(7) at the end of the close-loop power control process of measured terminal, FPGA is provided with flag bit automatically, notifies industry control
The main control software of machine control module reads the data in dual port RAM, and shows measured terminal changed power with graphic interface
Process.
In a preferred embodiment of the present invention, in step (5), the stepping-in amount for pre-setting is 1dB or 2dB or 3dB.
In a preferred embodiment of the present invention, in step (6), power threshold algorithm is that measured terminal shows currency
Signal power variations geometric locus and the signal power variations geometric locus after FPGA time delays for keep correlation, FPGA
Internal calculation goes out best power amplitude reduction value and starts the algorithm of the triggering moment of trapping module.
The invention has the beneficial effects as follows：Real-time capture pulse signal power device of the present invention is rational in infrastructure, design is former
Reason is simple, be easy to extension, with low cost, function is highly integrated, automatically extract frame synchronization, realize it is fast to mobile terminal TPC indexs
Fast real-time detection, it is adaptable to comprising the terminal transmission signal pulse such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM
The detection of time slot power；The method for realizing capture pulse signal in real time is relative to the letter of traditional test mode software control flow
Single, testing efficiency is high, while the requirement to tester also has substantial degradation.
Description of the drawings
Fig. 1 is the structured flowchart of the power device of capture pulse signal in real time of the invention preferred embodiment.
Fig. 2 is the theory diagram of the data intermediate frequency module.
Fig. 3 is the software flow pattern of the real-time capture pulse signal power device.
Fig. 4 is the use state figure of the real-time capture pulse signal power device.
Fig. 5 is the method flow diagram for realizing capture pulse signal power in real time.
Fig. 6 is the schematic diagram of the power threshold algorithm.
Fig. 7 is measured terminal close-loop power control (TPC) test waveform figure.
Specific embodiment
Presently preferred embodiments of the present invention is described in detail below in conjunction with the accompanying drawings, so that advantages and features of the invention energy
It is easier to be readily appreciated by one skilled in the art, apparent clearly defines so as to make to protection scope of the present invention.
Fig. 1 is referred to, the embodiment of the present invention includes：
A kind of capture pulse signal power device in real time, including Receiver Module, industrial computer control module, respectively with penetrate
Data intermediate frequency module that frequency receiver module is connected, local oscillator module, referrer module and total with the EISA that each module is in communication with each other
Line.Receiving attenuation device that Receiver Module includes being sequentially connected, the first self oscillating mixer, the first if bandpas filter, the
Two self oscillating mixers, the second if bandpas filter.Local oscillator module is made up of phaselocked loop, wave filter and voltage controlled oscillator, voltage-controlled
The output end of oscillator connects the first self oscillating mixer of Receiver Module.The lock that referrer module is connected by crystal oscillator and crystal oscillator
Xiang Huan, wave filter and voltage controlled oscillator composition, crystal oscillator is connected respectively with local oscillator module, data intermediate frequency module, voltage controlled oscillator
Output end is connected with the second self oscillating mixer of Receiver Module.Data intermediate frequency module includes clock distributor, is sequentially connected
Data acquisition module, FPGA, eisa bus interface, clock distributor is connected respectively with data acquisition module, FPGA.
The local oscillator module is identical with the phaselocked loop composition of referrer module, is filtered by end to end voltage controlled oscillator, loop
Ripple device, phase discriminator composition.The crystal oscillator of referrer module phase discriminator, the clock point of data intermediate frequency module respectively with local oscillator module
Orchestration is connected, and crystal oscillator is respectively the phase discriminator of referrer module and provides the clock signal of 10MHz, provides 100MHz's for local oscillator module
Clock signal, the clock signal that 122.88MHz is provided for data intermediate frequency module.The voltage-controlled vibrator of local oscillator module is to radio frequency reception
First self oscillating mixer of module is input into the high frequency carrier of 400MHz～6GHz, and the voltage-controlled vibrator of referrer module is to radio frequency reception
Second self oscillating mixer of module is input into the low frequency carrier signal of 1GHz.The receiving attenuation device of the Receiver Module receives tested end
The radiofrequency signal at end, with the high frequency carrier of local oscillator module transmitting the first self oscillating mixer is entered, and subsequently output 846.4MHz's is mixed
Frequency signal, it is mixed into the second local oscillator with the low frequency carrier signal of referrer module transmitting after the filtering of the first if bandpas filter
Frequency device, subsequently the intermediate-freuqncy signal of output 153.6MHz, sends into digital intermediate frequency mould after the filtering of the second if bandpas filter
The data acquisition module of block.
With reference to Fig. 2, the data acquisition module of the data intermediate frequency module includes the amplifier, the anti-aliasing filter that are sequentially connected
Device, A/D converter, FPGA include be sequentially connected Digital Down Converter Module, abstraction module, wave filter, virtual value detection module,
The capture pulse being connected with virtual value detection module output end respectively is along module and power peak search module, frame synchronization timing
The TPC trigger modes that device, startup trapping module, realtime power memory module, dual port RAM and startup trapping module input are connected
Block and control logic module.Wherein power peak search module with capture pulse along module output end respectively with frame synchronization timing
Device connects, and the input of eisa bus interface is connected with dual port RAM, output end and TPC trigger modules and control logic module phase
Even, clock distributor A/D converter respectively with data acquisition module, the DCM of FPGA are connected.The data intermediate frequency module is institute
State the core component of in real time capture pulse signal power device, predominantly tested mobile terminal sets up adaptive frame synchronization, in real time
Calculate signal power and capture TPC changed power curves.And FPGA is the core component of the data intermediate frequency module, radio frequency reception
Module output signal is amplified, filtering, transmit to FPGA processs after analog-to-digital conversion, adopts that VHDL is top-down to be set inside FPGA
Meter realizes Digital Down Convert, digital decimation, digital filtering, virtual value (RMS) detection, power peak search, capture pulse edge, frame
Synchronous, TPC triggerings, realtime power capture and storage, logic control.Wherein, Digital Down Convert, digital decimation, digital filtering, have
Valid value detection, power peak search and capture pulse edge are pile line operation, and data are ceaselessly refreshing in real time, wait software to send out
Instruction is sent to start frame synchronization process process, according to capture pulse along (signal triggering moment) arrival moment reset timer internal,
Realize to any period impulsive synchronization process.Initialize and wait after preset TPC templates software instruction (matching with terminal comprehensive test instrument),
Pulse slot position is accurately positioned according to timer internal, effective impulse is captured and root mean square (integration) process is carried out to it,
Power after process is preserved into dual port RAM in real time, and notifies that main control software reads data in good time.
The industrial computer control module is made up of main control software, hardware industrial computer, bus mainboard etc., including main control module,
Interface module, display module, operating system, Switching Power Supply.The industrial computer control module is capture pulse signal power in real time
The core control axis of device, by eisa bus the control of Initialize installation, data interaction and software is carried out to each module.Radio frequency
Receiver module, local oscillator module, referrer module and data intermediate frequency module are required for industrial computer control module software initialization to pass through
Eisa bus configuration parameter.The data-signal flow direction of the whole pulse signal power device of capture in real time is followed successively by measured terminal, penetrates
Frequency receiver module, data intermediate frequency module, industrial computer control module, control signal flow direction is industrial computer control module, radio frequency reception
Module and local oscillator module, referrer module and data intermediate frequency module.
The main control software flow chart of the real-time capture pulse signal power device is as shown in figure 3, mainly complete hardware control
The contents such as system, information processing, interaction process, man-machine interface.It is main to include following several portions by the modular design method of standard
Point：
(1) hardware initialization：The software operation of the power-up initializing of hardware.
(2) DDS/FPGA initialization：The calling by main control software in start, completes to multiple DDS (Direct Digital frequencies
Rate synthesizes) and FPGA inside each submodule initial configuration.
(3) hardware module self-inspection：Self-inspection software complete twin installation main hardware module together with instrument hardware self-checking circuit
Self-inspection, and real-time report self-detection result.Calibration software includes start calibration, user's calibration and three parts of device self calibration,
It is critically important measure that device realizes stability index, by the calibration to hardware module, makes up to optimum Working.
(4) module is initially controlled：State modulator to hardware circuit state is completed according to test target, it mainly includes instrument
Device Keyboard Control, module control, specifically include：
Synthesis local oscillator control：The FREQUENCY CONTROL for synthesizing local oscillator is mainly completed, is eated dishes without rice or wine to access frequency according to different mode terminal,
Send control instruction and produce correct local frequency, it is ensured that the correctness of radio frequency reception；
Radio frequency reception is controlled：Complete the power and FREQUENCY CONTROL of radio-frequency channel, channel switch control etc.；
Digital intermediate frequency is controlled：Mainly complete control and FPGA digital processings of high-speed a/d converter etc.；
Real-time analysis and Control：Complete the state modulator of the realtime frame synchronization to FPGA, timer and TPC templates；
Wherein module control predominantly control of the main control software to FPGA, and the real-time capture pulse signal power device
Real-time detection and storage completed by hardware FPGA completely.Software sub-process in the module control includes：Master control first is soft
Part removes all flag bits, starts the frame synchronization timing device of FPGA, and carries out trigger delay configuration to TPC trigger modules, it is ensured that
In the case of various stepping-in amount (1dB, 2dB or 3dB), TPC signals are from holding maximum to the change started when reducing for measured terminal
Change point and remain that position is fixed, then the overall process of true representation measured terminal changed power sends TPC instruction, TPC tests
Process starts.When main control software detects complement mark position, represent a close-loop power control process and terminate, that is, read twoport
Test data in RAM.
(5) data acquisition and procession, interface Read-write Catrol, measurement result show：Three is man-machine interface portion, completes whole
The display processing of machine, measures interaction process, provides perfect help information.
When using, Fig. 4 is referred to, the real-time capture pulse signal power device is located at measured terminal and radio frequency movement is whole
Between the comprehensive test instrument of end, interconnected by radio-frequency cable with power splitter, i.e., measured terminal and terminal comprehensive test instrument set up signaling loop and reality
When capture pulse signal power device in monitoring and test position, the up transmission signal Jing power splitter of measured terminal is exported to this
Device.This device does not need outer triggering signal, can be with industry on real-time detection, capture and memory mobile terminal (such as mobile phone)
Business signal.
Pulse signal power device is rational in infrastructure, design principle simple for the real-time capture, be easy to extension, it is with low cost,
Function is highly integrated, automatically extracts frame synchronization, realizes to the quick real-time detection of mobile terminal TPC indexs, it is adaptable to comprising the time-division
The detection of the terminal transmission signal pulse time slot power such as TD-LTE-A/TD-LTE/TD-SCDMA/GSM of multiplexing.
Can realize capturing pulse signal power in real time using the real-time capture pulse signal power device, with reference to
Fig. 5 and Fig. 6 is described in detail to the method for realizing real-time capture pulse signal power, and it is comprised the following steps：
(1) terminal comprehensive test instrument, measured terminal, real-time capture pulse signal power device are passed through into radio frequency electrical using power splitter
Cable is connected with each other, and all devices are initially powered up and complete Initialize installation；
(2) measured terminal initiates the Signalling exchanges such as calling, registration to terminal comprehensive test instrument first, and sets up signaling link；
(3) terminal comprehensive test instrument sends the TPC command for keeping power output maximum to measured terminal, makes the up of measured terminal
Business time-slot power remains constant and for maximum power state；
(4) in real time the main control software of capture pulse signal power device removes first the various flag bits of FPGA and to start frame same
Step function, afterwards FPGA will the real ascending time slot power signal of automatic discrimination (automatic distinguishing noise or interference signal), enter
Row power peak is searched for and starts frame synchronization timing device, and complete cost apparatus are synchronous with the time reference of measured terminal signal.This is same
Step signal is cyclical signal (to be 10ms under 5ms, TD-LTE/TD-LTE-Advanced pattern under TD-SCDMA pattern), can
As the synchronous triggering signal of measured terminal close-loop power control, the changed power of measured terminal is waited；
(5) terminal comprehensive test instrument to measured terminal transmit power according to pre-set stepping-in amount adjustment TPC command, make by
The uplink service time slot power for surveying terminal starts respectively from peak power (such as+39dBm) to be reduced to the stepping-in amount in TPC command
Minimum power (such as -80dBm), and then reversely adjusts, and gos up again to peak power according to identical stepping-in amount, finally keeps most
High-power state, as once complete close-loop power control process；
(6) in real time the FPGA of capture pulse signal power device accurately judges that signal power is adjusted according to power threshold algorithm
Moment, capture pulse is started immediately along module and power is calculated in real time, final calculated value (virtual value detection module it is defeated
Go out) it is saved in dual port RAM；
(7) at the end of the close-loop power control process of measured terminal, FPGA is provided with flag bit automatically, notifies industry control
The main control software of machine control module reads the data in dual port RAM, and main control software carries out logarithmic mapping, realizes linear value data
To the conversion of dB values, while carrying out trigger delay configuration to TPC trigger modules, most at last data show tested with graphic interface
The process of terminal power change.
In step (5), the stepping-in amount for pre-setting is 1dB or 2dB or 3dB.By taking 1dB as an example, Fig. 5 is referred to,
By taking TPC testing process common in terminal comprehensive test instrument as an example, description measured terminal is with the power real-time change of 1dB stepping-in amount for the figure
Situation, shows the operating procedure of FPGA inner function modules, and it includes：In starting after synchronous in advance, the synchronous success of ascending time slot
Whether portion's timer, now starts real-time monitoring ascending time slot power, started according to the trigger delay configuration determination for pre-setting
Store function, and ascending time slot power is preserved in real time, by dual port RAM data reality after this time close-loop power control process terminates
When be sent out to main control software, main control software reads measured power sequence and display output performance number.
In step (6), the power threshold algorithm is explained in detail with reference to Fig. 6：In measured terminal with the stepping of 1dB
, there are two curves signal power curve lower section during amount change, and first signal power variations track to show currency is bent
Line (as shown in A in Fig. 6), Article 2 is the signal power variations geometric locus (as shown in B in Fig. 6) of historical juncture value, that is, exist
Time aspect says, it be " the signal intensity track power curve of currency " through TPC trigger modules Time delay configure and
Obtain, be to ensure TPC signals from keeping maximum to starting to reduce when stepping-in amount that terminal comprehensive test instrument pre-sets is different
When change point remain that position is fixed, the overall process of true representation measured terminal changed power, the delay time meeting of configuration
It is different；In terms of amplitude, it is " the signal intensity track power curve of currency " (fixed-point number is moved to right through scaled
2bit, equivalent power reduces 6dB, and this numerical value is the best power amplitude reduction value gone out through test and FPGA internal calculations) and
Obtain；Two curves realize correlation (the signal power variations track of current time value on amplification value before and after in the same manner
During curve raise/lower, the signal power variations geometric locus of historical juncture value can also follow raise/lower).Therefore, two
Curve just generates in time intersection point (as shown in C in Fig. 6), now, just can be with using the comparison circuit inside fpga chip
Differentiate, i.e., we define the signal power variations geometric locus that this intersection point is current time value and start to reduce, and when dropping to history
Trigger during the signal power variations geometric locus lower section that quarter is worth.The trigger realizes auto-associating input signal,
Simultaneously the signal is also used for indicating that starting trapping module starts working.
The method for realizing capture pulse signal power in real time is described by taking once complete TPC test process as an example,
Fig. 7 is referred to, set of pulses signal is the signal that terminal uplink sends in figure, when terminal comprehensive test instrument sends TPC to measured terminal
Power keep maximize order after, this device can with real-time detection to the periodically pulsing signal power as shown in a in Fig. 7,
A straight changed power trajectory is drawn Jing after RMS detections (as shown in b in Fig. 7)；Now, when terminal comprehensive test instrument is to tested
Terminal sends the adjustment of TPC power and makes after (power first diminishes and becomes big afterwards), and measured terminal makes an immediate response simultaneously according to prior agreement
The upward signal performance number size that stepping-in amount (1dB or 2dB or 3dB) adjustment sends, in the same manner, this device still can be with real-time monitoring
To the change of the pulse, while the changed power geometric locus that real-time update is drawn.Based on the concurrent working principle of FPGA, input
After the d type flip flop of fpga chip inside, pulse signal and its changed power geometric locus postpone pulsed power signal simultaneously
For a period of time, time t (data delay) can be configured by main control software by TPC trigger modules.By FPGA power-thresholds
Value-based algorithm judges that signal power starts the moment for reducing, and now activation starts trapping module, and the power RMS value after delay is become
Change geometric locus (as shown in c in Fig. 7) numerical value to be saved in dual port RAM, wait pulse power to change to after maximization (now
Close-loop power control terminates), notify that main control software is read to walk this test data.
The method for realizing capture pulse signal in real time is simple relative to traditional test mode software control flow, disobeys
Rely and be capable of achieving to the quick real-time detection of mobile terminal TPC indexs in external wireless frame synchronizing signal, testing efficiency is high, while right
The requirement of tester also has substantial degradation.
Embodiments of the invention are the foregoing is only, the scope of the claims of the present invention is not thereby limited, it is every using this
Equivalent structure or equivalent flow conversion that bright specification and accompanying drawing content are made, or directly or indirectly it is used in other related skills
Art field, is included within the scope of the present invention.
Claims (8)
1. a kind of to capture pulse signal power device, including Receiver Module, industrial computer control module in real time, its feature exists
In, also including the data intermediate frequency module, local oscillator module, referrer module being connected with Receiver Module respectively and with each module
The eisa bus being in communication with each other, Receiver Module is including in the receiving attenuation device, the first self oscillating mixer being sequentially connected, first
Band-pass filter, the second self oscillating mixer, the second if bandpas filter, local oscillator module is by phaselocked loop, wave filter and voltage-controlled
Oscillator is constituted, and the output end of voltage controlled oscillator connects the first self oscillating mixer of Receiver Module, referrer module by crystal oscillator,
The phaselocked loop that is connected with crystal oscillator, wave filter and voltage controlled oscillator composition, crystal oscillator respectively with local oscillator module, data intermediate frequency module phase
Even, the output end of voltage controlled oscillator is connected with the second self oscillating mixer of Receiver Module, and data intermediate frequency module includes clock
Distributor, the data acquisition module being sequentially connected, FPGA, eisa bus interface, clock distributor respectively with data acquisition module,
FPGA is connected.
2. it is according to claim 1 it is real-time capture pulse signal power device, it is characterised in that the data intermediate frequency module
Data acquisition module be connected with the second if bandpas filter of Receiver Module, data acquisition module include be sequentially connected
Amplifier, frequency overlapped-resistable filter, A/D converter, FPGA includes the Digital Down Converter Module, abstraction module, the filter that are sequentially connected
Ripple device, virtual value detection module, the capture pulse being connected with virtual value detection module output end respectively are along module and power peak
Search module, frame synchronization timing device, startup trapping module, realtime power memory module, dual port RAM and startup trapping module are defeated
Enter the connected TPC trigger modules in end and control logic module, wherein power peak search module with capture pulse along the defeated of module
Go out end be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output end and TPC are triggered
Module and control logic module are connected, and clock distributor A/D converter respectively with data acquisition module, the DCM of FPGA are connected.
3. it is according to claim 1 it is real-time capture pulse signal power device, it is characterised in that the phaselocked loop by head and the tail
Connected voltage controlled oscillator, loop filter, phase discriminator composition.
4. it is according to claim 1 it is real-time capture pulse signal power device, it is characterised in that the crystalline substance of the referrer module
Shake phase discriminator respectively with local oscillator module, the clock distributor of data intermediate frequency module is connected.
5. real-time capture pulse signal power device according to claim 1, it is characterised in that the industrial computer controls mould
Block includes main control module, interface module, display module, operating system, Switching Power Supply.
6. based on the side for realizing capture pulse signal power in real time for capturing pulse signal power device described in claim 1 in real time
Method, comprises the following steps：
(1) terminal comprehensive test instrument, measured terminal, real-time capture pulse signal power device are passed through into radio-frequency cable phase using power splitter
Connect, all devices are initially powered up and complete Initialize installation；
(2) measured terminal initiates Signalling exchange to terminal comprehensive test instrument first, and sets up signaling link；
(3) terminal comprehensive test instrument sends the TPC command for keeping power output maximum to measured terminal, makes the uplink service of measured terminal
Time slot power remains constant and for maximum power state；
(4) in real time capture pulse signal power device starts frame synchronization function, completes same with the time reference of measured terminal signal
Step, waits the changed power of measured terminal；
(5) terminal comprehensive test instrument makes tested end to measured terminal transmit power according to the TPC command of the stepping-in amount adjustment for pre-setting
The uplink service time slot power at end is started to be reduced to minimum power from peak power respectively, is returned again with the stepping-in amount in TPC command
Rise to peak power, as once complete close-loop power control process；
(6) in real time the FPGA of capture pulse signal power device judges the moment of signal power adjustment according to power threshold algorithm,
Pulse is along module and calculates power in real time to start capture, and final calculated value is saved in dual port RAM；
(7) at the end of the close-loop power control process of measured terminal, FPGA is provided with flag bit automatically, notifies industrial computer control
The main control software of molding block reads the data in dual port RAM, and the process for showing measured terminal changed power with graphic interface.
7. it is according to claim 6 to realize the real-time method for capturing pulse signal power, it is characterised in that in step (5)
In, the stepping-in amount for pre-setting is 1dB or 2dB or 3dB.
8. it is according to claim 6 to realize the real-time method for capturing pulse signal power, it is characterised in that in step (6)
In, power threshold algorithm is the signal power variations geometric locus and the letter after FPGA time delays that measured terminal shows currency
Number changed power geometric locus goes out best power amplitude reduction value and starts trapping module to keep correlation, FPGA internal calculations
Triggering moment algorithm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410850426.6A CN104539383B (en) | 2014-12-30 | 2014-12-30 | Real-time pulse signal power capturing device and implement method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410850426.6A CN104539383B (en) | 2014-12-30 | 2014-12-30 | Real-time pulse signal power capturing device and implement method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104539383A CN104539383A (en) | 2015-04-22 |
| CN104539383B true CN104539383B (en) | 2017-05-10 |
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| CN105095129B (en) * | 2015-07-24 | 2018-01-30 | 中国兵器工业集团第二一四研究所苏州研发中心 | A kind of hard-wired real-time catching method of multi-path timer event |
| CN105262504B (en) * | 2015-11-11 | 2018-02-16 | 中国电子科技集团公司第四十一研究所 | The time and frequency measurement circuit and method of a kind of wide interval frequency hopping signal |
| CN105554298A (en) * | 2016-01-08 | 2016-05-04 | 上海创远仪器技术股份有限公司 | Remote control system and control method for vector signal source based on mobile terminal |
| CN106375031B (en) * | 2016-08-29 | 2019-05-28 | Oppo广东移动通信有限公司 | The detection method and mobile terminal of radio-frequency channel |
| CN109633579B (en) * | 2018-12-11 | 2020-11-03 | 上海无线电设备研究所 | Method and circuit for generating calibration signal of fixed intermediate frequency receiving channel |
| CN110850217B (en) * | 2019-11-28 | 2021-08-17 | 中电科仪器仪表有限公司 | Signal receiving channel state self-detection device and method |
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