CN210626562U

CN210626562U - System for improving effective sampling bandwidth under condition of not improving sampling rate

Info

Publication number: CN210626562U
Application number: CN201921372681.9U
Authority: CN
Inventors: 高青; 莫舸舸; 张笑语; 韩兵; 吴欣华
Original assignee: Chengdu Huari Communication Technology Co ltd
Current assignee: Chengdu Huari Communication Technology Co.,Ltd.
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2020-05-26
Anticipated expiration: 2029-08-22

Abstract

The utility model discloses a system for improve effective sampling bandwidth under the condition of not improving the sampling rate, including radio frequency module and FPGA, still include zero intermediate frequency AD chip, the input of zero intermediate frequency AD chip is connected the output of radio frequency module, the output of zero intermediate frequency AD chip are connected FPGA's input, zero intermediate frequency AD chip are used for obtaining baseband I way digital signal and baseband Q way digital signal after the radio frequency analog signal sampling of radio frequency module input and analog-to-digital conversion, and will baseband I way digital signal and baseband Q way digital signal input FPGA respectively. The utility model discloses an use zero intermediate frequency AD sampling technique, improve effective sampling bandwidth under the condition that does not improve the sampling rate, solved among the prior art and improved the sampling bandwidth and need synchronous AD chip lectotype difficulty, with high costs and the high problem of FPGA requirement that improves the sampling rate and bring from this.

Description

System for improving effective sampling bandwidth under condition of not improving sampling rate

Technical Field

The utility model relates to a radio communication and radio frequency spectrum detect technical field, specific saying so, a system that improves effective sampling bandwidth under the sampling rate condition is not improved.

Background

In the field of radio communications and spectrum monitoring, fast frequency sweeps are generally required to monitor changes in the corresponding radio band signal, and the most straightforward way to increase the speed of the frequency sweep is to increase the bandwidth of the frequency sweep. The bandwidth of the frequency sweep is improved, the sampling rate needs to be synchronously improved, after the sampling rate is improved, the model selection of the AD chip becomes difficult, the cost of the AD chip can be improved, higher-speed signal processing needs to be carried out, the processing capacity of the FPGA and the programming level of the FPGA have higher requirements, and the cost of the FPGA chip can be improved. There is no scheme for increasing the effective sampling bandwidth without increasing the sampling rate in the prior art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a system for improve effective sampling bandwidth under the condition of not improving the sampling rate for improve the sampling bandwidth among the solution prior art and need synchronous AD chip lectotype difficulty, with high costs and the high problem of requiring to FPGA that improves the sampling rate and bring from this.

The utility model discloses a following technical scheme solves above-mentioned problem:

the utility model provides a system for improve effective sampling bandwidth under the condition of not improving the sampling rate, includes radio frequency module and FPGA, still includes zero intermediate frequency AD chip, the input of zero intermediate frequency AD chip is connected the output of radio frequency module, the output of zero intermediate frequency AD chip is connected FPGA's input, zero intermediate frequency AD chip are used for obtaining baseband I way digital signal and baseband Q way digital signal after the radio frequency analog signal sampling of radio frequency module input and analog-to-digital conversion, and will baseband I way digital signal and baseband Q way digital signal input FPGA respectively.

Further, the zero intermediate frequency AD chip includes a voltage-controlled oscillator, a first mixer, a second mixer, a first analog-to-digital conversion unit, and a second analog-to-digital conversion unit, where the first mixer receives the radio-frequency analog signal output by the radio-frequency module and the first output signal of the voltage-controlled oscillator and outputs a baseband I-path analog signal to the first analog-to-digital conversion unit, the second mixer receives the radio-frequency analog signal output by the radio-frequency module and the second output signal of the voltage-controlled oscillator and outputs a baseband Q-path analog signal to the second analog-to-digital conversion unit, and output ends of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit are respectively connected to two signal input ends of the FPGA.

Further, the zero intermediate frequency AD chip may employ the following chips:

ADRV9008/ADRV9009/AD9361/AD9371。

compared with the prior art, the utility model, following advantage and beneficial effect have:

the utility model discloses an use zero intermediate frequency AD sampling technique, improve effective sampling bandwidth under the condition that does not improve the sampling rate, solved among the prior art and improved the sampling bandwidth and need synchronous AD chip lectotype difficulty, with high costs and the high problem of FPGA requirement that improves the sampling rate and bring from this.

Drawings

FIG. 1 is a schematic diagram of real number sampling in the prior art;

FIG. 2 is a schematic block diagram of the present invention;

FIG. 3 is a schematic circuit diagram of the present invention;

FIG. 4 is a waveform diagram of a signal;

FIG. 5 is a prior art spectrogram illustrating real sampling of the signal of FIG. 4, wherein the negative half-spectrum is a mirror image of the positive half-spectrum;

fig. 6 is a spectral diagram of a zero intermediate frequency AD sampling of the signal of fig. 4.

Detailed Description

The present invention will be described in further detail with reference to examples, but the present invention is not limited thereto.

Example 1:

real sampling in the prior art is shown in fig. 1, which is to perform analog-to-digital conversion on an intermediate frequency analog signal of a radio frequency module in an AD chip to obtain an intermediate frequency digital signal, then perform frequency mixing with a Numerically Controlled Oscillator (NCO) in an input FPGA signal to obtain a baseband I-path digital signal and a baseband Q-path digital signal, and perform signal processing respectively. In this case, if the bandwidth of the scan needs to be increased and the sampling rate needs to be increased synchronously, after the sampling rate is increased, not only the model selection of the AD chip becomes difficult and the cost of the AD chip increases, but also higher-speed signal processing needs to be performed, which has higher requirements on the processing capability of the FPGA and the programming level of the FPGA, and the cost of the FPGA also increases.

Combine as shown in fig. 2, this scheme provides a system for improving effective sampling bandwidth under the condition of not improving the sampling rate, including radio frequency module and FPGA, still include zero intermediate frequency AD chip, the input of zero intermediate frequency AD chip is connected radio frequency module's output, zero intermediate frequency AD chip's output is connected FPGA's input, zero intermediate frequency AD chip are used for obtaining baseband I way digital signal and baseband Q way digital signal after the radio frequency analog signal sampling and the analog-to-digital conversion that the radio frequency module was input, and will baseband I way digital signal and baseband Q way digital signal input FPGA respectively.

And after the radio frequency analog signal obtained by the radio frequency module is sent to a zero intermediate frequency AD chip for sampling, two paths of digital signal data of the baseband I, Q are sent to the FPGA for digital signal processing. Because the I, Q signals are sampled at the same time, the number of sampling points obtained in the same sampling rate and time is twice of the real number sampling. By the mode, when the sampling rate is NHz, the FPGA can obtain the digital signal with the effective bandwidth being NHz for signal processing, and the effective bandwidth is doubled under the condition that the sampling rate is not changed.

Example 2:

on the basis of embodiment 1, as shown in fig. 2 and fig. 3, the zero intermediate frequency AD chip includes a voltage-controlled oscillator, a first mixer, a second mixer, a first analog-to-digital conversion unit, and a second analog-to-digital conversion unit, where the first mixer receives a radio frequency analog signal output by the radio frequency module and a first output signal of the voltage-controlled oscillator and outputs a baseband I-path analog signal to the first analog-to-digital conversion unit, the second mixer receives a radio frequency analog signal output by the radio frequency module and a second output signal of the voltage-controlled oscillator and outputs a baseband Q-path analog signal to the second analog-to-digital conversion unit, and output ends of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit are respectively connected to two signal input ends of the FPGA.

In the zero intermediate frequency AD chip, firstly, radio frequency analog signals are respectively mixed with signals generated by a voltage-controlled oscillator to obtain baseband I-path analog signals and baseband Q-path analog signals, then, the baseband I-path analog signals and the baseband Q-path digital signals are respectively subjected to analog-to-digital conversion to obtain baseband I-path digital signals and baseband Q-path digital signals, and the baseband I-path digital signals and baseband Q-path digital signals are input into a signal processing circuit of the FPGA, so that the effective sampling bandwidth can be increased without increasing the sampling rate, the model selection difficulty and cost of the AD chip are reduced, and the cost of.

Further, the zero intermediate frequency AD chip adopts chip ADRV9008 or chip ADRV 9009.

For example, when a signal is received in radio monitoring, the waveform itself is shown in fig. 4, since real sampling is adopted in the prior art, the sampling rate is NHz, since real sampling lacks half-spectrum information, and the negative half-spectrum is a duplicate of the positive half-spectrum, the effective bandwidth that can be sampled in this way is only N/2Hz, and when the bandwidth of the signal is greater than N/2Hz, the obtained spectrum generates aliasing, as shown in fig. 5.

And the sampling rate is NHz in the zero intermediate frequency AD sampling mode, and since the sampling mode can acquire I, Q paths of real signals, and the negative half spectrum of the real signals also has the spectrum information of the original signal, the effective bandwidth of the sampling mode is NHz, which is 2 times of the effective bandwidth that can be acquired by the real sampling mode, and the effective sampling bandwidth is increased by one time, as shown in fig. 6.

Although the present invention has been described herein with reference to the illustrated embodiments thereof, which are merely preferred embodiments of the present invention, it is to be understood that the present invention is not limited thereto, and that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure.

Claims

1. The utility model provides a system for improve effective sampling bandwidth under the condition of not improving the sampling rate, includes radio frequency module and FPGA, its characterized in that still includes zero intermediate frequency AD chip, the input of zero intermediate frequency AD chip is connected the output of radio frequency module, the output of zero intermediate frequency AD chip is connected FPGA's input, zero intermediate frequency AD chip are used for obtaining baseband I way digital signal and baseband Q way digital signal after the radio frequency analog signal sampling and the analog-to-digital conversion that the radio frequency module was input, and will baseband I way digital signal and baseband Q way digital signal input FPGA respectively.

2. The system according to claim 1, wherein the zero-if AD chip includes a voltage-controlled oscillator, a first mixer, a second mixer, a first analog-to-digital conversion unit, and a second analog-to-digital conversion unit, the first mixer receives the rf analog signal output by the rf module and the first output signal of the voltage-controlled oscillator and outputs a baseband I analog signal to the first analog-to-digital conversion unit, the second mixer receives the rf analog signal output by the rf module and the second output signal of the voltage-controlled oscillator and outputs a baseband Q analog signal to the second analog-to-digital conversion unit, and output terminals of the first analog-to-digital conversion unit and the second analog-to-digital conversion unit are respectively connected to two signal input terminals of the FPGA.

3. The system for increasing the effective sampling bandwidth without increasing the sampling rate of claim 1, wherein the zero intermediate frequency AD chip employs a chip ADRV9008 or a chip ADRV 9009.