CN112953470A - Four-channel 12GSaps arbitrary waveform generation module and waveform generation method - Google Patents
Four-channel 12GSaps arbitrary waveform generation module and waveform generation method Download PDFInfo
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Abstract
The invention provides a four-channel 12GSaps arbitrary waveform generation module and a waveform generation method, which comprise a signal input/output interface, an input/output signal matching link, an analog-to-digital conversion circuit region, an FPGA, a QDR-IV region, a PXIe interface, a system time system circuit region, a JTAG interface connector assembly and a configuration circuit thereof, and a multi-channel power supply conversion circuit. After the module is assembled, the module can be inserted into a universal function slot of a standard 3U PXIe case, and high-speed communication can be carried out with the FPGA through 12V power supply work of a case backboard and a PXIe controller of the case. The highest digital-to-analog conversion rate of each output channel in the module is 12GSPS, and the four output channels can be combined and configured at will to generate analog signals. The module can receive control information of an external controller, complete algorithm processing in the FPGA, complete digital-to-analog conversion of the processed data and send the processed data out, and generate any analog signal.
Description
Technical Field
The invention belongs to the research field of electronic measuring instruments, and particularly relates to a four-channel 12GSaps arbitrary waveform generation module and a waveform generation method.
Background
The arbitrary waveform generator is used as an electronic measuring instrument and widely applied to various fields of complex radars, communication countermeasures and electronic warfare, wherein a core component is an arbitrary waveform generating module. The core of the arbitrary waveform generation module is a direct digital synthesis technology. The core principle is that quantized waveform data is stored in a waveform lookup table, a digital waveform is output by converting an arbitrary lookup table address, and the digital waveform obtains an analog signal through a digital-to-analog converter.
For radio frequency signals in an X wave band (8-12 GHz), the conventional method is to obtain intermediate frequency signals through a low-speed DAC, and then frequency-convert the intermediate frequency signals to a target frequency point through a frequency mixing link. The radio frequency signal thus obtained is limited to the local oscillator conversion range of the mixing chain. When a multi-channel signal is generated, multi-channel frequency conversion link matching is needed to be realized. Thus, the design of the multi-channel arbitrary waveform generator is not only complicated, but also high in cost.
Disclosure of Invention
The invention aims to provide a four-channel 12GSaps arbitrary waveform generation module and a waveform generation method, which can reduce the cost and complexity of equipment.
In order to achieve the purpose, the invention adopts the technical scheme that:
the invention provides a four-channel 12GSaps arbitrary waveform generation module, which comprises:
the signal input/output interface is used for receiving a sampling clock signal and sending an analog signal after impedance conversion;
the input and output signal matching link is used for performing impedance conversion on the sampling clock signal received by the signal input and output interface and performing impedance conversion on the analog signal obtained by conversion in the digital-to-analog conversion circuit region;
the FPGA is used for configuring the digital-to-analog conversion circuit region according to the requirements of JESD204B and carrying out interpolation, filtering and IQ modulation processing on the received digital signals;
the PXIe interface is used for receiving an external control signal, a clock synchronization signal and an external digital signal with the speed reaching 40Gbps by the FPGA;
the QDR-IV area is used for caching the digital signals received by the FPGA;
the digital-to-analog conversion circuit region is used for receiving the digital signals processed by the FPGA, decoding the received digital signals and then converting the digital signals into analog signals;
the system time system circuit region is used for providing a reference working clock for each part of the four-channel 12GSaps arbitrary waveform generation module;
and the multi-channel power supply conversion circuit is used for supplying power to each component of the four-channel 12GSaps arbitrary waveform generation module.
The signal input and output interface comprises 4 paths of analog signal output interfaces and 2 paths of clock input interfaces; the input and output signal matching link comprises corresponding impedance transformation circuits of 4 analog signal output interfaces and corresponding impedance transformation circuits of 2 clock input interfaces.
The digital-to-analog conversion circuit region is provided with 4 output channels of analog signals, the highest digital-to-analog conversion rate of each output channel is 12GSPS, and the four output channels can be combined and configured at will to generate the analog signals.
The system also comprises a JTAG interface connector and a configuration circuit thereof, which are used for carrying out online debugging on the four-channel 12GSaps arbitrary waveform generation module.
The four-channel 12GSaps arbitrary waveform generation module has the appearance size of a standard 3U structure, can be inserted into a universal function slot of a standard 3U PXIe case, works by supplying power through a case backboard 12V, and is in high-speed communication with the FPGA at the rate of 40Gbps after a PXIe controller of the case is connected with a PXIe interface through a PXIe bus of the case backboard.
The multi-channel power supply conversion circuit comprises 4 switching power supplies and a corresponding 16-path DC-DC conversion circuit.
The invention provides a waveform generation method of a four-channel 12GSaps arbitrary waveform generation module, which comprises the following steps:
1) receiving a sampling clock signal through a signal input and output interface;
2) the received clock signal completes impedance conversion through the input and output signal matching link;
3) the FPGA configures the digital-to-analog conversion circuit region according to the requirements of the JESD204B protocol;
4) the FPGA receives an external control signal and a clock synchronization signal through a PXIe interface;
5) the FPGA receives an external digital signal with the speed reaching 40Gbps through a PXIe interface;
6) the QDR-IV6 area buffers digital signals received by the FPGA;
7) after interpolation, filtering and IQ modulation processing of the digital signals in the FPGA, transmitting the digital signals to a digital-to-analog conversion circuit region through a digital link with the speed reaching 120Gbps between the digital-to-analog conversion circuit region and the FPGA;
8) the digital-to-analog conversion circuit region decodes the received digital signals and then completes the conversion from the digital signals to analog signals;
9) the analog signal obtained by conversion is subjected to impedance conversion through the input and output signal matching link, and then is sent out through the signal input and output interface to generate any signal.
Compared with the prior art, the invention has the beneficial effects that:
aiming at the problems that the conventional multi-channel arbitrary waveform generator is complex in implementation mode and high in overall equipment cost, the invention provides a better four-channel 12GSaps arbitrary waveform generation module and a waveform generation method. The four-channel 12GSaps arbitrary waveform generation module is mainly oriented to application requirements of a complex radar signal simulator, communication countermeasure, electronic warfare and the like, and is suitable for an arbitrary waveform generator in an X wave band. The four-channel 12GSaps arbitrary waveform generating module and the waveform generating method of the invention benefit from the multi-channel frequency synthesis technical mode, and a frequency conversion link is not needed for a multi-channel X-waveband arbitrary waveform generator, thereby greatly simplifying the multi-channel arbitrary waveform implementation mode and reducing the cost of equipment.
Drawings
FIG. 1 is a top level diagram of a four-channel 12GSaps arbitrary waveform generation module PCB provided by the present invention;
FIG. 2 is a bottom view of a PCB of the four-channel 12GSaps arbitrary waveform generation module provided by the present invention;
FIG. 3 is a diagram of a four-channel 12GSaps arbitrary waveform generation module according to the present invention;
FIG. 4 is a schematic diagram of interpolation filtering in the present invention;
FIG. 5 is a schematic diagram of IQ modulation according to the present invention;
wherein: the system comprises a signal input/output interface (SMA)1, an input/output signal matching link 2, a digital-to-analog conversion circuit region 3, a system time system circuit region 4, an FPGA5, a QDR-IV region 6, a multi-channel power conversion circuit 7, a baffle mounting positioning hole 8, a JTAG interface connector assembly and a configuration circuit thereof 9, a PXIe interface (PXIe connector region) 10, a module cold plate mounting hole 11 and a four-channel 12GSaps arbitrary waveform generation module PCB 12.
Detailed Description
The invention is further illustrated by the following examples, which are intended to be illustrative only and not to be limiting of the scope of the invention, and various equivalent modifications of the invention will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application.
Referring to fig. 1-3, the present invention provides a four-channel 12GSaps arbitrary waveform generation module for directly generating analog signals in the 12GHz range, comprising:
a signal input/output interface 1 for receiving a sampling clock signal; and is used for sending the analog signal after impedance conversion; the signal input and output interface 1 specifically comprises 4 paths of analog signal output interfaces and 2 paths of clock input interfaces;
the input and output signal matching link 2 is used for performing impedance conversion on the sampling clock signal received by the signal input and output interface 1; and is used for performing impedance conversion on the analog signal converted in the digital-to-analog conversion circuit region 3; the input/output signal matching link 2 specifically comprises a corresponding impedance conversion circuit of 4 paths of analog signal output interfaces and a corresponding impedance conversion circuit of 2 paths of clock input interfaces;
the FPGA5 (comprising a 28-pair SERDES interface with the speed reaching 16 Gbps) is used for configuring the digital-to-analog conversion circuit region 3 according to the requirements of a JESD204B protocol and carrying out interpolation, filtering and IQ modulation processing on the received digital signals; the PXIe interface 10 is used for receiving an external control signal, a clock synchronization signal and an external digital signal with the speed of 40Gbps by the FPGA 5; that is, the rate of communication of the FPGA5 through the PXIe interface 10 is 40 Gbps.
A QDR-IV area 6 (QDR-IV HP SRAM with the capacity of 144-Mbit) for caching the digital signals received by the FPGA 5;
the digital-to-analog conversion circuit region 3 is used for receiving the digital signals processed by the FPGA5, decoding the received digital signals and then converting the digital signals into analog signals; the digital-to-analog conversion circuit region 3 adopts 2 DA chips with two channels and high sampling rate, namely 4 output channels of analog signals are arranged in the digital-to-analog conversion circuit region 3, the highest digital-to-analog conversion rate of each output channel is 12GSPS, and the four output channels can be combined and configured at will to generate analog signals;
the system time system circuit region 4 is used for providing a reference working clock for each part of the four-channel 12GSaps arbitrary waveform generation module; the JTAG interface connector and the configuration circuit 9 thereof are used for carrying out online debugging on the four-channel 12GSaps arbitrary waveform generation module; the multi-channel power supply conversion circuit 7 is used for supplying power to each component of the four-channel 12GSaps arbitrary waveform generation module; the power supply in the invention is a 2-level power supply, wherein a multi-channel power supply conversion circuit 7 (comprising 4 switching power supplies and corresponding 16-path DC-DC conversion circuits) is a 1-level power supply and is used for full-page power supply; the 8 linear power supplies are 2-stage power supplies and are used for supplying power to the digital-to-analog conversion circuit region 3.
The invention provides a four-channel 12GSaps arbitrary waveform generation module, which has a standard 3U structure in the external dimension and mainly comprises a signal input/output interface (SMA)1, an input/output signal matching link 2(4 paths of analog signal output interfaces and corresponding impedance conversion circuits, 2 paths of clock input interfaces and corresponding impedance conversion circuits), a JTAG interface connector assembly and a configuration circuit 9 thereof, a1 path of PXIe high-speed communication interface circuit (PXIe connector area 10), a digital-to-analog conversion circuit area 3(2 DA chips with double channels and high sampling rate), 1 high-performance FPGA control chip (FPGA 5), 1 high-performance cache chip QDR-IV (QDR-IV area 6), a multi-channel power supply conversion circuit 7(4 switching power supplies and corresponding 16 paths of DC-DC conversion circuits), 8 linear power supplies (a secondary power supply for supplying power to the digital-to-analog conversion circuit area 3), and a power supply (a power supply for supplying power to the digital-, 1 high-performance multi-path clock output circuit (system time system circuit region 4). After the whole four-channel 12GSaps arbitrary waveform generation module is assembled, the four-channel arbitrary waveform generation module can be inserted into a universal function slot position of a standard 3U PXIe case, and can be used for communication with the FPGA5 at the rate of 40Gbps after 12V power supply work is carried out through a case backboard, and a PXIe controller of the case is connected with a PXIe interface 10 through a PXIe bus of the case backboard. The highest digital-to-analog conversion rate of each output channel of the four-channel 12GSaps arbitrary waveform generation module is 12GSPS, and the four output channels can be combined and configured arbitrarily to generate analog signals. The four-channel 12GSaps arbitrary waveform generation module can simultaneously receive control information of an external controller, completes interpolation, filtering and IQ modulation processing on digital signals in the FPGA5, completes digital-to-analog conversion on the processed data and sends out the processed data to generate arbitrary signals.
The invention discloses a waveform generation method of a four-channel 12GSaps arbitrary waveform generation module, which comprises the following steps:
1) receiving a sampling clock signal through a signal input and output interface 1;
2) the received clock signal is matched with the link 2 through the input and output signals to complete impedance conversion;
3) the FPGA5 configures the digital-to-analog conversion circuit region 3 according to the requirements of the JESD204B protocol;
4) the FPGA5 receives an external control signal and a clock synchronization signal through a PXIe interface 10;
5) the FPGA5 receives an external digital signal with the speed up to 40Gbps through the PXIe interface 10;
6) the QDR-IV6 area 6 buffers the digital signals received by the FPGA 5;
7) after the interpolation, filtering and IQ modulation processing of the digital signal in the FPGA5 is finished, the digital signal is transmitted to the digital-to-analog conversion circuit region 3 through a digital link between the digital-to-analog conversion circuit region 3 and the FPGA5, wherein the speed of the digital link reaches 120 Gbps;
8) the digital-to-analog conversion circuit region 3 decodes the received high-speed digital signal and then completes the conversion from the digital signal to the analog signal;
9) the analog signal obtained by conversion is subjected to impedance conversion through the input/output signal matching link 2, and then is transmitted through the signal input/output interface 1, so that any signal is generated.
The interpolation in step 7) refers to performing data interpolation algorithm processing, and specifically includes the following steps:
integer-multiple interpolation means that (I-1) zero values are inserted between two original sampling points of original sampling sequence x (n), so as to obtain a new sequence x after interpolationl(m)：
The interpolated signal spectrum is:
XI(ejω)＝X(ejωI)
the spectrum of the interpolated signal is the spectrum obtained by compressing the original sequence by the factor of I. At this time XI(ejω) Not only containing X (e)j ω) And also an image component with a frequency greater than pi/I, in order to get from XI(ejω) In order to recover the original spectrum, the interpolated signal has to be low-pass filtered (filter bandwidth pi/I). The interpolation filtering principle is shown in fig. 4 (spectrogram before and after interpolation, I ═ 2).
IQ modulation in step 7) is shown in fig. 5, specifically as follows:
the IQ signal input to the baseband can be expressed as the following equation.
I(n)＝a(n)cosθ(n)
Q(n)＝a(n)sinθ(n)
The IQ modulation is shown below:
S(n)＝I(n)cos(won)-Q(n)sin(won)
＝a(n)cosθ(n)cos(won)-a(n)sinθ(n)sin(won)
＝a(n)cos(won+θ(n))
the chips are realized by adopting commercially available chips, wherein the FPGA chip adopts a chip with the model number of XCKU060FFVA1156, the QDR-IV chip adopts a chip with the model number of CY7C4141KV13-667FCXC, and the DA chip adopts a chip with the model number of AD 9173.
To facilitate understanding of the present invention, a specific example of the analog signal generation module of the four-channel 12GSaps arbitrary waveform generation module of the present invention is given below to further explain the present invention.
A radar comprehensive detector needs to generate a radar test signal in an X wave band. Traditionally, mixing is used to generate an intermediate frequency signal in the 1GHz range from the lower DA rate, and then converting the intermediate frequency signal into the X-band range by mixing. A plurality of mixing channels are required to be arranged for the plurality of transmitting channels, and by using the module, signals in an X-band range can be directly generated without a mixing link, and 4 independent channels can be randomly arranged. This reduces the size of the system, improves the portability of the system, and reduces the overall cost.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention, and all simple modifications, changes and equivalent structural changes made to the above embodiment according to the technical spirit of the present invention still fall within the protection scope of the technical solution of the present invention.
Claims (7)
1. A four-channel 12GSaps arbitrary waveform generation module, comprising:
the signal input/output interface (1) is used for receiving a sampling clock signal and sending an analog signal after impedance conversion;
the input and output signal matching link (2) is used for performing impedance conversion on the sampling clock signal received by the signal input and output interface (1) and performing impedance conversion on the analog signal obtained by conversion in the digital-to-analog conversion circuit area (3);
the FPGA (5) is used for configuring the digital-to-analog conversion circuit region (3) according to the requirements of the JESD204B and carrying out interpolation, filtering and IQ modulation processing on the received digital signals;
the PXIe interface (10) is used for receiving an external control signal, a clock synchronization signal and an external digital signal with the speed reaching 40Gbps by the FPGA (5);
the QDR-IV area (6) is used for caching the digital signals received by the FPGA (5);
the digital-to-analog conversion circuit region (3) is used for receiving the digital signals processed by the FPGA (5), decoding the received digital signals and then converting the digital signals into analog signals;
the system time system circuit area (4) is used for providing a reference working clock for each part of the four-channel 12GSaps arbitrary waveform generation module;
and the multi-channel power supply conversion circuit (7) is used for supplying power to each component of the four-channel 12GSaps arbitrary waveform generation module.
2. The four-channel 12GSaps arbitrary waveform generation module of claim 1, wherein: the signal input and output interface (1) comprises 4 paths of analog signal output interfaces and 2 paths of clock input interfaces; the input and output signal matching link (2) comprises 4 impedance transformation circuits corresponding to the analog signal output interfaces and 2 impedance transformation circuits corresponding to the clock input interfaces.
3. The four-channel 12GSaps arbitrary waveform generation module of claim 2, wherein: the digital-to-analog conversion circuit region (3) is provided with 4 output channels of analog signals, the highest digital-to-analog conversion rate of each output channel is 12GSPS, and the four output channels can be combined and configured at will to generate the analog signals.
4. The four-channel 12GSaps arbitrary waveform generation module of claim 1, wherein: the system also comprises a JTAG interface connector and a configuration circuit (9) thereof, which are used for carrying out online debugging on the four-channel 12GSaps arbitrary waveform generation module.
5. The four-channel 12GSaps arbitrary waveform generation module of claim 1, wherein: the four-channel 12GSaps arbitrary waveform generation module has the appearance size of a standard 3U structure, can be inserted into a universal function slot of a standard 3U PXIe case, works by supplying power through a case backboard 12V, and is connected with a PXIe controller of the case through a PXIe bus of the case backboard and a PXIe interface (10) and then carries out high-speed communication with the FPGA (5) at the speed of 40 Gbps.
6. The four-channel 12GSaps arbitrary waveform generation module of claim 1, wherein: the multi-channel power supply conversion circuit (7) comprises 4 switching power supplies and corresponding 16-path DC-DC conversion circuits.
7. The method of generating waveforms in the four-channel 12GSaps arbitrary waveform generation module of any one of claims 1-6, comprising the steps of:
1) receiving a sampling clock signal through a signal input and output interface (1);
2) the received clock signal completes impedance conversion through the input and output signal matching link (2);
3) the FPGA (5) configures the digital-to-analog conversion circuit region (3) according to the requirements of the JESD204B protocol;
4) the FPGA (5) receives an external control signal and a clock synchronization signal through a PXIe interface (10);
5) the FPGA (5) receives an external digital signal with the speed up to 40Gbps through a PXIe interface (10);
6) the QDR-IV6 area (6) buffers the digital signals received by the FPGA (5);
7) after interpolation, filtering and IQ modulation processing of the digital signals in the FPGA (5), the digital signals are transmitted to the digital-to-analog conversion circuit area (3) through a digital link between the digital-to-analog conversion circuit area (3) and the FPGA (5) with the speed of 120 Gbps;
8) the digital-to-analog conversion circuit region (3) decodes the received digital signal and then completes the conversion from the digital signal to the analog signal;
9) the analog signals obtained by conversion are subjected to impedance conversion through the input and output signal matching link (2) and then are sent out through the signal input and output interface (1) to generate any signals.
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| Publication number | Priority date | Publication date | Assignee | Title |
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