KR101740713B1 - SDR receiver for radar testing - Google Patents

Abstract

The present invention relates to an SDR receiver, and more particularly, to an SDR receiver for radar testing capable of processing high-speed data. An embodiment of the present invention includes an A / D converter for sampling an input RF signal to generate an I differential signal of two channels and a Q differential signal of two channels, which are parallel low-voltage differential signals, and outputting the signals as a total of four channels; An FPGA for reducing and outputting data amounts of the I differential signal and the Q differential signal, respectively; And a USB controller for uploading an output signal of the FPGA to a computer.

Description

{SDR receiver for radar testing}

The present invention relates to an SDR receiver, and more particularly, to an SDR receiver for radar testing capable of processing high-speed data.

With the miniaturization of hardware and the relaxation of radio wave deregulation, the data utilization field is spreading not only in various industries such as medical / bio, vehicle / transportation, facility security, but also in daily life.

Radar is an integrated system of hardware platform and software processor consisting of antenna, transmitter, receiver, and signal processor, and it can be time consuming and costly because it has to go through new design and development stage according to application field.

Conventional radar systems use a common approach that involves two passes of RF analog mixing. With the recent GSPS (giga sample per second) ADC, the digitization point in the system is getting closer to the antenna after the first mixing stage. The new GSPS ADC supports excellent linearity and analog bandwidth above 3 GHz to support digitization close to the antenna, allowing undersampling of the S-band frequency. This allows for direct RF sampling within the S-band frequency band, eliminating the mixing step and reducing component count and system size.

On the other hand, SDR (Software Defined Radio) refers to a radio architecture of a communication device, not a communication method, and a receiver designed in this manner is called an SDR receiver. The SDR receiver processes the radar signal processing purely in software, not in hardware. Filtering of the signal or demodulation of information from the signal is also a software process.

[0004] However, there is an inconvenience that a product should be developed by changing hardware of an SDR receiver that processes a radar signal whenever a radar specification is changed or another kind of radar is developed. Therefore, there is an urgent need for an SDR receiver for test purposes that can support multiple modes by software modification without changing hardware even when radar specification changes or other kinds of radars are developed.

Korean Patent Laid-Open No. 10-2006-0038518

The technical problem of the present invention is to provide an SDR receiver necessary for developing a radar. It is another object of the present invention to provide an SDR receiver capable of high-speed sampling with respect to a radar signal.

An embodiment of the present invention includes an A / D converter for sampling an input RF signal to generate an I differential signal of two channels and a Q differential signal of two channels, which are parallel low-voltage differential signals, and outputting the signals as a total of four channels; An FPGA for reducing and outputting data amounts of the I differential signal and the Q differential signal, respectively; And a USB controller for uploading an output signal of the FPGA to a computer.

The A / D converter comprises: an A / D first converter module for sampling the RF signal according to a sampling clock provided from the outside to generate an I sampling signal that is in phase with the RF signal; An A / D second converter module for generating a Q sampling signal in which an RF signal is sampled so as to have a phase difference of 90 ° from the I sampling signal according to the sampling clock; An I-signal demultiplexing module for generating and outputting two-channel I-differential signals of an I1-differential signal and an I2-differential signal to the FPGA by de-muxing the I-sampling signal; And a Q-signal demultiplexing module for generating and outputting two-channel Q-differential signals of a Q1 differential signal and a Q2 differential signal to the FPGA by de-muxing the Q-sampling signals.

The A / D first converter module samples the RF signal in a time-interleaved manner to generate two I sampling signals of an I1 sampling signal and an I2 sampling signal, and the A / D second converter module May sample the RF signal in a time-interleaved manner to generate two Q sampling signals of a Q2 sampling signal and a Q2 sampling signal.

The A / D first converter module may sample the RF signal every rising of the sampling clock and alternately output it as an I1 sampling signal and an I2 sampling signal.

The A / D second converter module may sample the RF signal at every down time of the sampling clock and alternately output the sampled RF signal as a Q1 sampling signal and a Q2 sampling signal.

Wherein the FPGA comprises: an I signal demodulation module for demodulating the provided I differential signal to generate an I signal; A Q signal demodulating module for demodulating a provided Q differential signal to generate a Q signal; And a down-converter for generating an I-down signal and a Q-down signal by performing down sampling to reduce the amount of sampling data of the I signal and the Q signal.

An I-differential signal FIFO buffer for pre-selecting and outputting the I1 differential signal and the I2 differential signal to provide the I signal demodulation module; And a Q differential signal FIFO buffer for preliminarily selecting and inputting the Q1 differential signal and the Q2 differential signal and providing the same to the Q signal demodulation module.

Wherein the down-converter comprises: a Cascaded Integrator Comb (CIC) filter for performing down-sampling on the I signal and the Q signal, respectively; And a CFIR (Compensation Finite Impulse Response) filter for improving an amplitude characteristic of the downsampled signal through the CIC filter and outputting the I down signal and the Q down signal.

According to an embodiment of the present invention, high-speed sampling can be performed by a time-interleaved method. Also, by implementing the DDC (Digital Down Converter) reflecting the CIC filter and the CFIR filter in the FPGA, the conventional input signal portion according to the phase division of the DDC does not need to separate the I / Q channel. Therefore, by eliminating the existing RF parts (mixer, etc.), the physical size can be reduced in the analog design part of the receiving module.

FIG. 1 is a view showing an operation of an SDR receiver for a radar test for filtering and demodulating an RF signal of a specific band according to an embodiment of the present invention. FIG.
2 is a configuration block diagram of an SDR receiver for radar testing according to an embodiment of the present invention;
3 is a block diagram of the configuration of an A / D converter according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating sampling in an A / D converter according to an embodiment of the present invention. FIG.
5 is a block diagram of a configuration of an FPGA according to an embodiment of the present invention.
6 is a graph showing an output waveform of the A / D converter before applying the CIC filter;
7 is a graph showing an output waveform after applying the CIC filter;
8 is a graph showing an output waveform after applying both a CIC filter and a CFIR filter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to explain the present invention in detail so that those skilled in the art can easily carry out the present invention. . Other objects, features, and operational advantages of the present invention, including its effects and advantages, will become more apparent from the description of the preferred embodiments. It should be noted that the same reference numerals are used to denote the same or similar components in the drawings.

FIG. 1 is a diagram illustrating an operation of a radar test SDR receiver for filtering and demodulating an RF signal of a specific band according to an embodiment of the present invention. Referring to FIG.

In the embodiment of the present invention, an RF (Radio Frequency) signal, which is an RF signal input to the SDR receiver 200 for radar testing, can utilize an RF module of a normal radar system as a radar signal, 3GHz (S band) will be described as an example. So that the SDR receiver 200 for the radar test performs high-speed ADC sampling. That is, in order to input the RF frequency of 3 GHz in the SDR receiver 200 for radar test, a test jig 100 (jig) for frequency generation connected to the input terminal of the radar test SDR receiver 200 is provided. The test jig 100 sets a carrier frequency Fc at a high frequency of 2.7 GHz through a signal generator 110 and a frequency of 300 MHz through a DDS (Direct Digital Synthesis) To generate a ± 7.5 MHz bandwidth signal, and mix the two signals in a mixer to generate a RF signal with a bandwidth of ± 7.5 MHz at a high frequency transmission frequency of 3 GHz. The DDS module generates and provides a sampling clock of 1.2 GHz to be used in data sampling in the SDR receiver.

The I / Q signal, which is an output value of the SDR receiver 200 for radar test, is transmitted to the USB-connected computer 300 at the output terminal and can monitor the I / Q signal through the computer 300. The computer 300 may also control the DDS module.

An SDR receiver is a receiver that processes most signal processing by software rather than hardware. Software Defined Radio (SDR) is an open signal processing technology that can be reconfigured as a software application on a common hardware platform. The SDR receiver also performs software filtering of the signal or demodulation of the information from the signal. Hereinafter, the SDR receiver 200 for radar testing of the present invention will be described in detail with reference to FIG. 2 to FIG.

3 is a block diagram of an A / D converter according to an embodiment of the present invention. FIG. 4 is a block diagram of an SDR receiver for a radar test according to an embodiment of the present invention. And the sampling is performed by the interleaving method in the A / D converter.

The SDR receiver 200 for a radar test according to the present invention includes an A / D converter 210 for performing high-speed sampling by a time-interleaved method, an FPGA 220 equipped with a DDC algorithm, and an FPGA 220 And a USB controller 230 for uploading a signal-processed result to the computer 300.

The USB controller 230 converts the filtered and resized output signals in the FPGA 220 into a USB communication standard and uploads the converted signals to the computer 300.

The A / D converter 210 performs high-speed sampling by a time-interleaved method on the input RF signal. Until recently, most high-speed A / D converters 210 used a low-voltage differential signal (LVDS) as a means of transferring data between a high-speed ADC and a digital signal processing platform (usually the FPGA 220) do. However, when outputting data from a converter using an LVDS data bus, there is a technical challenge because a single LVDS bus must implement high performance that exceeds the IEEE standard maximum data transfer rate or the level that the FPGA (220) can handle have.

To solve this problem, the A / D converter 210 of the radar test SDR receiver 200 of the present invention demultiplexes output data into two or more general LVDS buses (de-multiplexed) High-speed data transmission is possible by reducing the transmission amount. To this end, the A / D converter 210 samples the input RF frequency, generates an I-differential signal of two channels, which is a parallel low-voltage differential signal, and a Q-differential signal of two channels, .

As shown in FIG. 3, the A / D converter 210 includes an A / D first converter module 2101, an A / D second converter module 2102, an I signal demultiplexer module 2103, And a multiplexing module 2104.

The first A / D converter module 2101 samples an RF signal according to a sampling clock provided from a signal generator 110 in an external test fixture 100, and outputs an in-phase signal I And generates a sampling signal. In addition, the A / D second converter module 2102 receives a Q sampling signal, which is obtained by sampling an RF signal so as to have a phase difference of 90 ° with an I sampling signal according to a sampling clock provided by the signal generator 110 of the test fixture 100, .

For reference, the RF signal provided to the A / D first converter module 2101 may be a signal obtained by converting an RF signal of 3 GHz +/- 7.5 MHz to an intermediate frequency band of the baseband. Here, the I sampling signal refers to an RF signal and an in-phase signal input thereto, and the Q sampling signal refers to a quadrature phase signal having a phase difference of 90 ° with an I sampling signal.

GHz sampling clock supplied from the signal generator 110 in the test jig 100 and outputs the 1.2 GHz sampling clock to the A / D converter module 2101 and the A / D second converter module 2102 By using two ADC (Analog Digital Converter), sampling can be done alternately. Therefore, high-speed sampling up to 2.4GHz is possible. In this case, the sampling of each converter module is performed by a time-interleaved interleaving method to generate two parallel low-voltage differential signals. By sampling in an interleaving manner, a high data transfer rate can be realized.

That is, the A / D first converter module 2101 samples the RF signal in a time-interleaved manner to generate two I sampling signals of the I1 sampling signal and the I2 sampling signal, Converter module 2102 samples the RF signal in a time-interleaved manner to generate two Q sampling signals of a Q1 sampling signal and a Q2 sampling signal.

4, the A / D first converter module 2101 samples the RF signal every rising time of the sampling clock, and outputs the I1 sampling signal and the I2 sampling signal as alternating To the I-signal demultiplexing module 2103. In addition, the A / D second converter module 2102 may sample the RF signal every time the sampling clock is down and output it to the Q signal demultiplexing module 2104 as a Q1 sampling signal and a Q2 sampling signal alternately .

The I-signal demultiplexing module 2103 demultiplexes the I-sampling signal provided from the A / D first converter module 2101 and outputs the I1-differential signal I1 and the I2-differential signal I2, And outputs the I-differential signal to the FPGA 220. The I- Similarly, the Q-signal demultiplexing module 2104 demultiplexes the Q-sampling signal to generate a 2-channel Q-differential signal composed of the Q1 differential signal Q1 and the Q2 differential signal Q2, 220, respectively. Therefore, the FPGA 220 converts the four-channel differential signal composed of the I1 differential signal I1, the I2 differential signal I2, the Q1 differential signal Q1, and the Q2 differential signal Q2 into a parallel low-voltage differential signal LVDS Voltage Differential Signal). Thus, the number of data channels is de-multiplexed with four LVDS buses, thereby enabling high-speed data transmission from the A / D converter 210 to the FPGA 220. [

5 is a block diagram of an FPGA according to an embodiment of the present invention.

The field programmable gate array (FPGA) 220 is a field programmable gate array, which is a combination of logic gates and performs filtering and data extraction through programming. The FPGA 220 of the present invention includes four channels of an I1 differential signal I1, an I2 differential signal I2, a Q1 differential signal Q1, and a Q2 differential signal Q2 transmitted from the A / D converter 210, And outputs the reduced signal and the differential signal, respectively.

To this end, the FPGA 220 includes an I differential signal FIFO buffer 2201, a Q differential signal FIFO buffer 2202, an I signal demodulation module 2203, a Q signal demodulation module 2204, and a down converter 2210 .

I differential signal FIFO buffer 2201 first inputs and outputs the I1 differential signal I1 and the I2 differential signal I2 provided from the A / D converter 210 and outputs them to the I signal demodulation module 2203, And the Q differential signal FIFO buffer 2202 first inputs and outputs the Q1 differential signal Q1 and the Q2 differential signal Q2 provided from the A / D converter 210 and provides the same to the Q signal demodulation module 2204 do. The data provided from the A / D converter 210 can be provided without interruption by performing the buffering input / output in the first-in first-out (FIFO) manner using the FIFO buffer.

I signal demodulation module 2203 demodulates the I differential signal provided as the I1 differential signal and the I2 differential signal to generate an I signal and the Q signal demodulation module 2204 demodulates the Q1 differential signal and the Q2 differential signal Demodulates the Q differential signal to generate a Q signal. The demodulation of the differential signal can follow the demodulation scheme of various known low-voltage differential signals (LVDS).

The down converter 2210 (DDC) generates an I-down signal and a Q-down signal by performing under sampling to reduce the amount of sampling data of the I signal and the Q signal. Therefore, the down-converter 2210 can select only the signal bandwidth and the signal position within the Nyquist band of the high-speed A / D converter 210 and transmit only the appropriate data necessary for the signal processing apparatus.

The down converter 2210 includes a CIC filter 2211 for performing under-sampling on the I signal and the Q signal at predetermined intervals of undersampling, and a CIC filter 2211 for performing an undersampling on the amplitude characteristics of the undersampled signal through the CIC filter 2211 And outputting it as an I down signal and a Q down signal.

The Cascaded Integrator Comb (CIC) filter is different from other filters and has a high computation speed because there is no multiplication operation. Therefore, it is easy to implement in the FPGA (Field Programmable Gate Array) 220. The CIC filter 2211 that improves the characteristics of the pass band may be a function of the type of sin (x) / x that is already known.

Meanwhile, although the CIC filter 2211 has an effect of reducing the sampling data, the frequency response characteristic curve has a sinc function type, and the characteristic in the frequency band is not flat, so that the amplitude is reduced. To compensate for this, a CFIR (Compensation Finite Impulse Response) filter, which is a CIC compensation filter, is applied.

The CFIR filter 2212 is referred to as a compensation CIC filter 2211 as a filter for compensating the output of the CIC filter 2211. The characteristic in the pass band of the CIC filter 2211 is not flat and the sidelobe is very large, so that the portion is corrected to improve and compensate the magnitude characteristic.

6 is a graph showing the output waveform of the A / D converter 210 before the CIC filter 2211 is applied, FIG. 7 is a graph showing the output waveform after the CIC filter 2211 is applied, and FIG. 8 is a graph showing the output waveforms after applying both the CIC filter 2211 and the CFIR filter 2212. FIG. 8 and FIG. 8, the magnitude characteristic of FIG. 8 using the CFIR filter 2212 is improved.

The embodiments of the present invention described above are selected and presented in order to facilitate the understanding of those skilled in the art from a variety of possible examples. The technical idea of the present invention is not necessarily limited to or limited to these embodiments Various changes, modifications, and other equivalent embodiments are possible without departing from the spirit of the present invention.

100: Test jig 200: SDR receiver for radar test
300: computer 210: A / D converter
220: FPGA 230: USB controller
2201: I differential signal FIFO buffer
2202: Q Differential Signal FIFO Buffer
2203: I signal demodulation module
2204: Q signal demodulating module
2210: Downconverter
2211: CIC filter 2212: CFIR filter

Claims (8)

An A / D converter for sampling an input RF signal to generate an I differential signal of two channels and a Q differential signal of two channels, which are parallel low voltage differential signals, and outputting the signals as a total of four channels;
An FPGA for reducing and outputting data amounts of the I differential signal and the Q differential signal, respectively; And
And a USB controller for uploading an output signal of the FPGA to a computer,
The A / D converter includes:
A first A / D converter module for sampling the RF signal according to a sampling clock provided from the outside and generating an I sampling signal that is in phase with the RF signal; An A / D second converter module for generating a Q sampling signal in which an RF signal is sampled so as to have a phase difference of 90 ° from the I sampling signal according to the sampling clock; An I-signal demultiplexing module for generating and outputting two-channel I-differential signals of an I1-differential signal and an I2-differential signal to the FPGA by de-muxing the I-sampling signal; And a Q-signal demultiplexing module for generating and outputting two-channel Q-differential signals of a Q1 differential signal and a Q2 differential signal to the FPGA by de-muxing the Q-sampling signal,
The FPGA includes:
An I signal demodulating module for demodulating the provided I differential signal to generate an I signal; A Q signal demodulating module for demodulating a provided Q differential signal to generate a Q signal; And a down-converter for generating an I-down signal and a Q-down signal by performing under sampling to reduce an amount of sampling data of the I signal and the Q signal.
delete The method according to claim 1,
The first A / D converter module samples the RF signal in a time-interleaved manner to generate two I sampling signals of an I1 sampling signal and an I2 sampling signal,
The A / D second converter module samples the RF signal in a time-interleaved manner to generate two Q sampling signals of a Q2 sampling signal and a Q2 sampling signal.
4. The A / D converter module according to claim 3,
Sampling the RF signal every rising of the sampling clock, and alternately outputting the sampled RF signal as an I1 sampling signal and an I2 sampling signal.
4. The A / D converter module of claim 3,
Sampling the RF signal every time the sampling clock is down, and alternately outputting the Q1 sampling signal and the Q2 sampling signal.
delete The method according to claim 1,
An I-differential signal FIFO buffer for pre-selecting and outputting the I1 differential signal and the I2 differential signal to provide the I signal demodulation module; And
A Q differential signal FIFO buffer for inputting and outputting the Q1 differential signal and the Q2 differential signal to the Q signal demodulation module;
And an SDR receiver for radar testing.
The power converter according to claim 1,
A Cascaded Integrator Comb (CIC) filter for performing under-sampling on the I signal and the Q signal, respectively; And
A CFIR (Compensation Finite Impulse Response) filter for improving an amplitude characteristic of the undersampled signal through the CIC filter to output an I down signal and a Q down signal;
And an SDR receiver for radar testing.

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