CN111865851B - Intermediate frequency digital processing system - Google Patents
Intermediate frequency digital processing system Download PDFInfo
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- CN111865851B CN111865851B CN202010786980.8A CN202010786980A CN111865851B CN 111865851 B CN111865851 B CN 111865851B CN 202010786980 A CN202010786980 A CN 202010786980A CN 111865851 B CN111865851 B CN 111865851B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04L27/00—Modulated-carrier systems
- H04L27/0008—Modulated-carrier systems arrangements for allowing a transmitter or receiver to use more than one type of modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
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Abstract
The invention discloses an intermediate frequency digital processing system, which belongs to the technical field of communication systems and comprises a parallel digital down-conversion module, a serial digital down-conversion module, a reconstruction array, a related despreading module, an ASK demodulation module, an identification module, a DPSK/PPM demodulation module and a configuration bus. The parallel digital down-conversion module processes the broadband signal; the serial digital down-conversion module processes the narrowband signal and the broadband signal processed by the parallel digital down-conversion module; the reconstruction array constructs a data link through a configuration bus, and transmits signals processed by the serial digital down-conversion module to a related despreading module and an ASK demodulation module; the related despreading module is used for despreading the baseband signal to finish related calculation, amplitude calculation and threshold detection; ASK demodulation is carried out by the ASK demodulation module, so that amplitude filtering, self-adaptive threshold discrimination and pulse shaping are completed; the DPSK/PPM demodulation module selects an output signal of the ASK demodulation module or the reconstruction array to carry out DPSK demodulation or PPM demodulation according to the output signal of the identification module.
Description
Technical Field
The invention relates to the technical field of communication systems, in particular to an intermediate frequency digital processing system.
Background
Compared with analog intermediate frequency processing, the digital intermediate frequency processing has better flexibility, can meet various standards, and is applied to the fields of information-based household appliances, radar systems, signal spectrum analysis and the like. The digital intermediate frequency technology is to convert the radio frequency signal and intermediate frequency signal by the analog front end and to modulate and demodulate the digital signal, encode and decode the channel by the digital circuit. In order to meet the requirement of system upgrading, a system consisting of ADC, FPGA, DSP, DAC and the like is constructed, the DSP is used for carrying out operation processing, and the flexibility of the system is improved based on the programmable characteristic of the FPGA.
To reduce the speed of the data stream sampled by the ADC, DDC (Digital Down Converter or, digital down conversion) technology is often used to convert the intermediate frequency signal into the baseband signal. The quadrature mixing-based digital down-conversion includes a digital mixer, an NCO (Nu-merical Control Oscillator, a digitally controlled oscillator), a decimation filter, etc., which converts a high data stream into a low data stream, shifts the frequency spectrum of a target signal to a low frequency or baseband by mixing, generates a pair of sine and cosine waves by the digitally controlled oscillator, multiplies the intermediate frequency signal, and then filters and decimates.
The digital intermediate frequency receiver is developed towards miniaturization, low cost, flexible configuration and the like. By adopting monolithic integration, the integration level and the complexity of digital signal processing are improved, and the high integration level and the light miniaturization of a communication system can be realized. The near-distance transmission processing of the narrowband signals can not meet the application requirements of modern communication on the broadband signals, and the digital intermediate frequency system has the characteristics of multiple signal types, wide frequency coverage, diversified forms and the like. Based on the polyphase filtering principle of digital channelized reception, the wideband signal can be divided into a plurality of sub-bands with different frequencies, and the sub-bands are converted into the same intermediate frequency signal or baseband signal by utilizing down-conversion. The software radio technology and the hardware reconfigurable technology are respectively realized in two modes, the software radio adopts software to process signals, different algorithms are all realized by the software, and the processing speed is slightly poorer when the operation amount is larger. The reconfigurable technology based on FPGA upgrades the circuit structure by reconfiguring the bit stream. The monolithic integrated hardware acceleration unit is positioned between the monolithic integrated hardware acceleration unit and the monolithic integrated hardware acceleration unit, the hardware acceleration unit can improve the operation capability of the system, the software programmable characteristic can improve the flexibility, and the abundant peripheral interfaces can enhance the expansibility.
Disclosure of Invention
The invention aims to provide an intermediate frequency digital processing system, which improves the configurability of each part and the reconfigurability of a data link and provides stronger flexibility for multichannel processing.
In order to solve the above technical problems, the present invention provides an intermediate frequency digital processing system, including:
the parallel digital down-conversion module is used for processing the broadband signal;
the serial digital down-conversion module is used for processing the narrowband signal and the broadband signal processed by the parallel digital down-conversion module;
reconstructing an array, constructing a data link through a configuration bus, and transmitting signals processed by the serial digital down-conversion module to a related despreading module and an ASK demodulation module;
the related despreading module is used for despreading baseband signals and comprises phase calculation, amplitude calculation and threshold detection, and determining the position and peak value of a related peak; the ASK demodulation module performs ASK demodulation to finish amplitude filtering, self-adaptive threshold discrimination and pulse shaping, and outputs pulse amplitude to the recognition module and the DPSK/PPM demodulation module;
and the DPSK/PPM demodulation module selects the ASK demodulation module or the output signal of the reconstruction array to carry out DPSK demodulation or PPM demodulation according to the output signal of the identification module.
Optionally, the parallel digital down-conversion module includes a first buffer module, a polyphase decimation filter and a parallel mixer, performs polyphase filtering, decimation and mixing processing on an input wideband signal, and outputs a signal a and a signal B; the signal A and the signal B are in-phase signals and quadrature signals respectively.
Optionally, the serial digital down-conversion module includes a second buffer module, a MUX, an NCO, a mixer, and a low-pass filter, and performs serial mixing filtering processing on the input narrowband signal and signals a and B.
Optionally, the MUX is configured by the configuration bus to select a narrowband signal output by the second buffer module, and the other path is connected with 0, or a signal a and a signal B; the mixer multiplies the two paths of signals output by the MUX by the digital local oscillator source signal I, Q signal output by the NCO, and outputs the signals to the low-pass filter for filtering after the down-conversion processing is completed.
Optionally, the first buffer module and the second buffer module have the same function, and the clock domain for processing the input signal and the clock domain for processing the output signal of the buffer modules are different.
Optionally, each output signal group of the reconstruction array is independent, any one of the input signal groups can be selected by the configuration bus configuration, and the relevant despreading module and the ASK demodulation module cannot select the same signal group output by the reconstruction array.
Optionally, the DPSK demodulation detects whether an inversion point exists after the identification module outputs the effective signal, and if the inversion point exists, the demodulation data is effective.
Optionally, the configuration bus belongs to an on-chip bus, and is configured to configure coefficients of a polyphase extraction filter and a parallel mixer in the parallel digital down-conversion module, configure coefficients of an NCO and a low-pass filter and MUX selection in the serial digital down-conversion module, configure a code rate, a code length, a phase correlation peak threshold, an amplitude correlation peak threshold and a pulse width threshold of the correlation despreading module, configure a discrimination threshold and an adaptive parameter of the ASK demodulation module, acquire information demodulated by the DPSK/PPM demodulation module, and configure a data link of the reconstruction array.
The invention provides an intermediate frequency digital processing system which comprises a parallel digital down-conversion module, a serial digital down-conversion module, a reconstruction array, a related despreading module, an ASK demodulation module, an identification module, a DPSK/PPM demodulation module and a configuration bus. The parallel digital down-conversion module is used for processing the broadband signal; the serial digital down-conversion module is used for processing the narrowband signal and the broadband signal processed by the parallel digital down-conversion module; the reconstruction array constructs a data link through a configuration bus, and transmits signals processed by the serial digital down-conversion module to a related despreading module and an ASK demodulation module; the related despreading module is used for despreading the baseband signal and comprises phase calculation, amplitude calculation and threshold detection, and determining the position and peak value of a related peak; ASK demodulation module carries out ASK demodulation to complete amplitude filtering, self-adaptive threshold discrimination and pulse shaping, and outputs pulse amplitude to recognition module and DPSK/PPM demodulation module; and the DPSK/PPM demodulation module selects the output signal of the ASK demodulation module or the reconstruction array to carry out DPSK demodulation or PPM demodulation according to the output signal of the identification module.
The invention has the following beneficial effects:
(1) Fully utilizing integrated resources in a chip, supporting the processing of broadband and narrowband signals, supporting ASK demodulation, DPSK demodulation and PPM demodulation, and supporting various code rates and code lengths;
(2) The coefficient configurability and the data connection reconfigurability of each module are improved to a great extent, the reasonable distribution of each sub-module and the data path is realized based on time division multiplexing, and better flexibility is provided for the processing of multichannel broadband signals and narrowband signals.
Drawings
FIG. 1 is an overall schematic diagram of an intermediate frequency digital processing system provided by the present invention;
fig. 2 is a schematic diagram of data connection of a broadband signal according to an embodiment of the present invention.
Detailed Description
An intermediate frequency digital processing system according to the present invention is described in further detail below with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
The invention provides an intermediate frequency digital processing system, the structure of which is shown in figure 1, comprising a parallel digital down-conversion module, a serial digital down-conversion module, a reconstruction array, a related despreading module, an ASK demodulation module, an identification module, a DPSK/PPM demodulation module and a configuration bus. The parallel digital down-conversion module is used for processing broadband signals; the serial digital down-conversion module is used for processing narrowband signals and broadband signals processed by the parallel digital down-conversion module; the reconstruction array constructs a data link through a configuration bus, and transmits signals processed by the serial digital down-conversion module to a related despreading module and an ASK demodulation module; the related despreading module is used for despreading baseband signals and comprises phase calculation, amplitude calculation and threshold detection, and determining the position and peak value of a related peak; the ASK demodulation module performs ASK demodulation to finish amplitude filtering, self-adaptive threshold discrimination and pulse shaping, and outputs pulse amplitude to the recognition module and the DPSK/PPM demodulation module; the DPSK/PPM demodulation module selects the ASK demodulation module or the output signal of the reconstruction array to carry out DPSK demodulation or PPM demodulation according to the output signal of the identification module, and when the DPSK/PPM demodulation module selects the signal of the reconstruction array, the ASK demodulation module can not process the partial signal. In this embodiment, the code rate configuration range of the related despreading module is 5M-100MHz, and the code length supports 16/32/64/128 bits. And when the correlation despreading module performs correlation calculation addition processing, the amplitude correlation output is 16 bits high, and the phase correlation output is 16 bits low.
With continued reference to fig. 1, the parallel digital down-conversion module includes a first buffer module, a polyphase decimation filter, and a parallel mixer, performs polyphase filtering, decimation, and mixing processing on an input wideband signal, and outputs a signal a and a signal B; where signal a is an in-phase signal and signal B is a quadrature signal. The input signal of the parallel digital down-conversion module is a signal which is processed and output by a broadband ADC signal through a broadband ADC receiving end. The parallel digital down-conversion module adopts 128-order polyphase decimation filter, and the decimation multiple is 8. Each path of broadband input signal 96bit data is multiplied and added with 3 groups of data with different frequencies through a parallel digital down-conversion module, and 3 paths of 16bit quadrature signals and 3 paths of 16bit in-phase signals are output through frequency mixing. Under the condition that the frequency spectrum is not aliased, the method is realized by adopting a multiphase structure of extracting and then filtering in order to reduce hardware operation resources. The serial digital down-conversion module comprises a second buffer module, a MUX, an NCO, a mixer and a low-pass filter, and performs serial mixing filtering processing on an input narrowband signal, a signal A and a signal B. The first buffer module and the second buffer module have the same function, and the clock domain for processing the input signal of the buffer module is different from the clock domain for processing the output signal of the buffer module.
The MUX is configured by the configuration bus to select a narrow-band signal output by the second buffer module, and the other path is connected with 0, or a signal A and a signal B; the mixer multiplies the two paths of signals output by the MUX by the digital local oscillator source signal I, Q signal output by the NCO, and outputs the signals to the low-pass filter for filtering after the down-conversion processing is completed. In this embodiment, the narrowband signal input by the serial digital down-conversion module is a signal that is processed and output by the narrowband ADC signal through the narrowband ADC receiving end. The serial digital down-conversion module adopts a 64-order low-pass filter, the NCO outputs signals in real time based on the Cordic method, the NCO frequency can be configured to be 0-25MHz, and the frequency and the precision of the signals are configured through a frequency control word and a phase control word. Each output signal group of the reconstruction array is independent, any one of the input signal groups can be selected by the configuration bus configuration, and the related despreading module and the ASK demodulation module can not select the same group of signals output by the reconstruction array. In this embodiment, the reconstruction array is configured to input 8 IQ signals, each IQ output being reconfigurable. Each output group is independent and any one of the 8 input groups may be selected. The hardware realizes the function of multiplexing input and multiplexing output, and ensures that the same IQ output is not selected for relevant despreading or ASK demodulation during software configuration. And the DPSK demodulation is carried out by detecting whether an inversion point exists after the identification module outputs an effective signal, and demodulating data is effective when the inversion point exists.
Referring to fig. 2, a schematic diagram of data connection of a wideband signal in this embodiment includes a 1-way parallel digital down-conversion module (PDDC 0), an 8-way serial digital down-conversion module (SDDC 0-7), a 4-way related despreading module (CORR 0-3), a 4-way ASK demodulation module (ASK 0-3), an 8-way identification module (RE 0-7), and a 4-way DPSK/PPM demodulation module (DPSK/PPM 0-3), which are consistent with each module in fig. 1 in function and composition, and are multiple instantiations of each module in fig. 1 for constructing multiple channels to process data of different channels. The resources of fig. 2 can be configured through the configuration bus to process signals of different modulation modes, different code lengths, different code rates and different frequency points, such as configuration of polyphase decimation filters and parallel mixer coefficients in the parallel digital down-conversion module, such as configuration of NCO, low-pass filter coefficients and MUX selection in the serial digital down-conversion module, such as configuration of code rate, code length, phase correlation peak threshold, amplitude correlation peak threshold and pulse width threshold of the correlation de-expansion module, such as configuration of discrimination threshold and adaptive parameters of the ASK demodulation module, and further such as configuration of data link of the reconstruction array. The reconstruction array is designed as an 8x8 array, the 8 sets of input signals are converted into 8 sets of output signals, the 8 sets of IQ outputs are mutually independent and reconfigurable, and any one of the 8 sets of input sets can be selected. In fig. 2, only one data connection is shown, SDDC0 is connected to CORR0, SDDC1 is connected to CORR2, SDDC2 is connected to ASK0, SDDC3 is connected to ASK2, and the connection relationship can be reconstructed without choosing the same IQ output for correlated despreading or ASK demodulation.
The intermediate frequency digital processing system provided by the invention is applied to actual measurement:
the intermediate frequency digital processing system provided by the invention is applied to an SoC circuit supporting various peripheral interfaces to realize demodulation and processing of broadband and narrowband signals, and the configuration bus is realized based on an AHB protocol. The SoC circuit integrates a general CPU, a broadband ADC and a narrow-band ADC, is communicated with the on-chip and off-chip devices based on an AHB bus, is configured with the ADC through an SPI interface, and transmits ADC data to the intermediate frequency digital processing system through a multichannel ADC receiving end. The broadband center frequency is 300MHz, the intermediate frequency bandwidth is 120MHz, the narrowband center frequency is 300MHz, and the intermediate frequency bandwidth is 8MHz. The SoC circuit supports 4 groups of broadband signals and 8 groups of narrowband signals, the working frequency is set to 100MHz under the consideration of wiring resources and ADC output frequency, ASK demodulation, DPSK demodulation and PPM demodulation are supported, and various code rates and code lengths are supported. The circuit adopts a 55nm technology, and through practical tests, the multi-frequency point and multi-form signals can be processed in real time, and the demodulated signals have good quality and higher sensitivity and resolution.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (8)
1. An intermediate frequency digital processing system, comprising:
the parallel digital down-conversion module is used for processing the broadband signal;
the serial digital down-conversion module is used for processing the narrowband signal and the broadband signal processed by the parallel digital down-conversion module;
reconstructing an array, constructing a data link through a configuration bus, and transmitting signals processed by the serial digital down-conversion module to a related despreading module and an ASK demodulation module;
the related despreading module is used for despreading baseband signals and comprises phase calculation, amplitude calculation and threshold detection, and determining the position and peak value of a related peak; the ASK demodulation module performs ASK demodulation to finish amplitude filtering, self-adaptive threshold discrimination and pulse shaping, and outputs pulse amplitude to the recognition module and the DPSK/PPM demodulation module;
and the DPSK/PPM demodulation module selects the ASK demodulation module or the output signal of the reconstruction array to carry out DPSK demodulation or PPM demodulation according to the output signal of the identification module.
2. The intermediate frequency digital processing system of claim 1 wherein the parallel digital down conversion module comprises a first buffer module, a polyphase decimation filter, and a parallel mixer, performing polyphase filtering, decimation, and mixing processing on an input wideband signal, outputting signal a and signal B; the signal A and the signal B are in-phase signals and quadrature signals respectively.
3. The intermediate frequency digital processing system of claim 2 wherein said serial digital down conversion module comprises a second buffer module, a MUX, an NCO, a mixer, and a low pass filter for serial mixing filtering of the incoming narrowband signals and signals a, B.
4. The intermediate frequency digital processing system according to claim 3, wherein the MUX is configured by the configuration bus to select a narrowband signal output by the second buffer module, and the other is connected with 0, or signal a and signal B; the mixer multiplies the two paths of signals output by the MUX by the digital local oscillator source signal I, Q signal output by the NCO, and outputs the signals to the low-pass filter for filtering after the down-conversion processing is completed.
5. The intermediate frequency digital processing system of claim 3 wherein the first buffer module and the second buffer module function identically, the clock domain for processing the input signal and the clock domain for processing the output signal of each buffer module being different.
6. The intermediate frequency digital processing system of claim 1 wherein each set of output signals of the reconstruction array is independent, any one of the sets of input signals being selectable by the configuration bus configuration, the correlated despreading module being non-selectable by the ASK demodulation module for reconstructing the same set of signals output by the array.
7. The if digital processing system of claim 1, wherein said DPSK demodulation outputs a valid signal from said identification module and then detects whether an inversion point exists, and if an inversion point exists, the demodulated data is valid.
8. The system of claim 4, wherein the configuration bus is an on-chip bus, and is configured to configure coefficients of a polyphase decimation filter and a parallel mixer in the parallel digital down-conversion module, to configure coefficients of an NCO and a low pass filter and MUX selections in the serial digital down-conversion module, to configure a code rate, a code length, a phase correlation peak threshold, an amplitude correlation peak threshold, and a pulse width threshold of the correlation despreading module, to configure a discrimination threshold and an adaptive parameter of the ASK demodulation module, to obtain information demodulated by the DPSK/PPM demodulation module, and to configure a data link of the reconstruction array.
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| CN109450833A (en) * | 2018-10-08 | 2019-03-08 | 深圳市太赫兹科技创新研究院 | Parallel demodulators and its data processing method |
| CN110646766A (en) * | 2019-09-23 | 2020-01-03 | 四川九洲电器集团有限责任公司 | S-mode interrogation signal detection method, storage medium and detection device |
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| US7103098B2 (en) * | 2002-03-15 | 2006-09-05 | Intel Corporation | Adaptive receiver for multiplex/multi-access communications |
| US20050003781A1 (en) * | 2003-07-02 | 2005-01-06 | California Eastern Laboratories | Multiple format radio frequency receiver |
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| CN109450833A (en) * | 2018-10-08 | 2019-03-08 | 深圳市太赫兹科技创新研究院 | Parallel demodulators and its data processing method |
| CN110646766A (en) * | 2019-09-23 | 2020-01-03 | 四川九洲电器集团有限责任公司 | S-mode interrogation signal detection method, storage medium and detection device |
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| 基于软件无线电的通用数字解调方法研究;马子骥;郑善贤;刘宏立;;长沙交通学院学报(第01期);全文 * |
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