CN204305039U - Catch pulse signal power device in real time - Google Patents
Catch pulse signal power device in real time Download PDFInfo
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- CN204305039U CN204305039U CN201420867049.2U CN201420867049U CN204305039U CN 204305039 U CN204305039 U CN 204305039U CN 201420867049 U CN201420867049 U CN 201420867049U CN 204305039 U CN204305039 U CN 204305039U
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Abstract
The utility model discloses one and catch pulse signal power device in real time, the eisa bus comprising Receiver Module, industrial computer control module, the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and intercom mutually with each module, mobile terminal upward signal Receiver Module through to be mixed to for twice fixed intermediate frequency, again by A/D converter to FPGA, realize catching the test of pulse signal power index in real time by software control FPGA.The utility model is rational in infrastructure, design principle is simple, be easy to expansion, with low cost, function height is integrated, automatic extraction frame synchronization, realize detecting in real time fast mobile terminal TPC index, be applicable to the detection comprising the terminal transmission signal pulse time slot powers such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM.
Description
Technical field
The utility model relates to mobile communication terminal index test technical field, particularly relates to one and catches pulse signal power device in real time.
Background technology
At present, mobile communication terminal test instrumentation is tested according to the conformity specification such as 3GPP TS34.120/2/3 or TS 36.521-1 terminal uplink transmit signal power (signaling/non-signaling pattern) test is general.For " RF consistency " terminal test instrument, the test case " TPC (Transmit Power Control; terminal uplink transmitting power controls) " of Application and Development scene, under signaling mode, synchronizing signal is provided by base band (physical layer); Under non-signaling pattern (or without outer synchronous signal) to terminal carry out " TPC " test time, if only rely on " power level " to trigger obtain synchronizing signal, can be working properly during large-signal, but during small-signal, (poor signal to noise) can false triggering cause synchronizing signal to be made mistakes.Therefore, dependence outer synchronous signal carries out the device that pulse signal is caught, and flexibility and the scope of application are all poor.In addition, external VSA does not generally provide the power detection having and automatically catch " figure ray mode " in real time, pulse signal can only be caught at random sweep time by strengthening, but this scheme is limited by data storage capacity restriction can not catch random time length signals flexibly, figure display also inconvenient tester's observation signal and the analysing terminal performance index of simultaneously catching at random.
Therefore need badly and provide a kind of novel device with self adaptation automatic synchronizing function to solve the problems referred to above.
Utility model content
Technical problem to be solved in the utility model is to provide one and catches pulse signal power device in real time, can not rely on external wireless frame synchronizing signal and realizes detecting in real time fast mobile terminal TPC index.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is: provide one to catch pulse signal power device in real time, comprise Receiver Module, industrial computer control module, the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and the eisa bus intercomed mutually with each module, Receiver Module comprises the receiving attenuation device be connected successively, first self oscillating mixer, first if bandpas filter, second self oscillating mixer, second if bandpas filter, local oscillator module is made up of phase-locked loop, and its output connects the first self oscillating mixer of Receiver Module, and referrer module comprises crystal oscillator, the phase-locked loop be connected with crystal oscillator, crystal oscillator respectively with local oscillator module, data intermediate frequency module is connected, and the output of referrer module is connected with the second self oscillating mixer of Receiver Module, and data intermediate frequency module comprises clock distributor, the data acquisition module be connected successively, FPGA, eisa bus interface, clock distributor respectively with data acquisition module, FPGA is connected.
In the utility model preferred embodiment, the data acquisition module of described data intermediate frequency module is connected with the second if bandpas filter of Receiver Module, data acquisition module comprises the amplifier connected successively, frequency overlapped-resistable filter, A/D converter, FPGA comprises the Digital Down Converter Module be connected successively, abstraction module, filter, effective value detection module, what be connected with effective value detection module output respectively catches pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, the TPC trigger module be connected with startup trapping module input and control logic module, wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, clock distributor respectively with the A/D converter of data acquisition module, the DCM of FPGA is connected.Described data intermediate frequency module is described core component of catching pulse signal power device in real time, is mainly tested mobile terminal and sets up adaptive frame synchronization, in real time calculating signal power and catch TPC changed power curve.
In the utility model preferred embodiment, described phase-locked loop is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.
In the utility model preferred embodiment, the crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively.Crystal oscillator is respectively local oscillator module and provides the clock signal of 100MHz, provides the clock signal of 122.88MHz for data intermediate frequency module.
In the utility model preferred embodiment, described industrial computer control module comprises main control module, interface module, display module, operating system, Switching Power Supply.Described industrial computer control module is the core control axis of catching pulse signal power device in real time, carries out Initialize installation, data interaction and software control by eisa bus to each module.
The beneficial effects of the utility model are: described in the utility modelly catch that pulse signal power device is rational in infrastructure in real time, design principle is simple, be easy to expansion, with low cost, function height is integrated, automatic extraction frame synchronization, realize detecting in real time fast mobile terminal TPC index, be applicable to the detection comprising the terminal transmission signal pulse time slot powers such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the utility model catches pulse signal power device one preferred embodiment in real time.
Fig. 2 is the theory diagram of described data intermediate frequency module.
Fig. 3 is described software flow pattern of catching pulse signal power device in real time.
Fig. 4 is the described using state figure catching pulse signal power device in real time.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present utility model is described in detail, to make advantage of the present utility model and feature can be easier to be readily appreciated by one skilled in the art, thus more explicit defining is made to protection range of the present utility model.
Refer to Fig. 1, the utility model embodiment comprises:
One catches pulse signal power device in real time, the eisa bus comprising Receiver Module, industrial computer control module, the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and intercom mutually with each module.Receiver Module comprises the receiving attenuation device, the first self oscillating mixer, the first if bandpas filter, the second self oscillating mixer, the second if bandpas filter that are connected successively.Local oscillator module is made up of phase-locked loop, and its output connects the first self oscillating mixer of Receiver Module.The phase-locked loop that referrer module comprises crystal oscillator, is connected with crystal oscillator, crystal oscillator is connected with local oscillator module, data intermediate frequency module respectively, and the output of referrer module is connected with the second self oscillating mixer of Receiver Module.Data acquisition module, FPGA, eisa bus interface that data intermediate frequency module comprises clock distributor, is connected successively, clock distributor is connected with data acquisition module, FPGA respectively.
Described local oscillator module forms identical with the phase-locked loop of referrer module, is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.The crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively, the clock signal that the phase discriminator that crystal oscillator is respectively referrer module provides the clock signal of 10MHz, provides the clock signal of 100MHz, provides 122.88MHz for data intermediate frequency module for local oscillator module.The voltage-controlled vibrator of local oscillator module is to the high frequency carrier of first self oscillating mixer input 400MHz ~ 6GHz of Receiver Module, and the voltage-controlled vibrator of referrer module is to the low frequency carrier signal of the second self oscillating mixer input 1GHz of Receiver Module.The receiving attenuation device of described Receiver Module receives the radiofrequency signal of measured terminal, the high frequency carrier launched with local oscillator module enters the first self oscillating mixer, export the mixed frequency signal of 846.4MHz subsequently, after the filtering of the first if bandpas filter, the low frequency carrier signal launched with referrer module enters the second self oscillating mixer, export the intermediate-freuqncy signal of 153.6MHz subsequently, after the filtering of the second if bandpas filter, send into the data acquisition module of data intermediate frequency module.
Composition graphs 2, the data acquisition module of described data intermediate frequency module comprises the amplifier, frequency overlapped-resistable filter, the A/D converter that connect successively, FPGA comprise be connected successively Digital Down Converter Module, abstraction module, filter, effective value detection module, is connected with effective value detection module output respectively catch pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, the TPC trigger module be connected with startup trapping module input and control logic module.Wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, and clock distributor is connected with the A/D converter of data acquisition module, the DCM of FPGA respectively.Described data intermediate frequency module is described core component of catching pulse signal power device in real time, is mainly tested mobile terminal and sets up adaptive frame synchronization, in real time calculating signal power and catch TPC changed power curve.And FPGA is the core component of described data intermediate frequency module, Receiver Module output signal transfers to FPGA process after amplifications, filtering, analog-to-digital conversion, adopt in FPGA inside that VHDL top-down design realizes Digital Down Convert, digital decimation, digital filtering, effective value (RMS) detection, power peak are searched for, catch pulse edge, frame synchronization, TPC triggering, realtime power catch with store, logic control.Wherein, Digital Down Convert, digital decimation, digital filtering, effective value detection, power peak search and catch pulse along being pile line operation, data are ceaselessly refreshing in real time, wait for that software sends instruction and starts frame synchronization process process, to arrive moment reset timer internal along (signal trigger instants) according to catching pulse, realizing any period impulsive synchronization process.Software instruction (mating with terminal comprehensive test instrument) is waited for after the preset TPC template of initialization, according to the accurate position pulse time slot position of timer internal, catch effective impulse and root mean square (integration) process is carried out to it, power after process is saved in dual port RAM in real time, and notifies that main control software reads data in good time.
Described industrial computer control module is made up of main control software, hardware industrial computer, bus mainboard etc., comprises main control module, interface module, display module, operating system, Switching Power Supply.Described industrial computer control module is the core control axis of catching pulse signal power device in real time, carries out Initialize installation, data interaction and software control by eisa bus to each module.Receiver Module, local oscillator module, referrer module and data intermediate frequency module all need industrial computer control module software initialization by eisa bus configuration parameter.Whole data-signal of catching pulse signal power device in real time flows to and is followed successively by measured terminal, Receiver Module, data intermediate frequency module, industrial computer control module, and control signal flows to as industrial computer control module, Receiver Module and local oscillator module, referrer module and data intermediate frequency module.
Described main control software flow chart of catching pulse signal power device in real time as shown in Figure 3, mainly completes the contents such as hardware controls, information processing, interaction process, man-machine interface.By the modular design method of standard, mainly comprise following several part:
(1) hardware initialization: the software operation of the power-up initializing of hardware.
(2) DDS/FPGA initialization: the calling by main control software when starting shooting, completes the initial configuration to the inner each submodule of multiple DDS (direct digital synthesis technique) and FPGA.
(3) hardware module self-inspection: the self-inspection of self-inspection software complete twin installation main hardware module together with instrument hardware self-checking circuit, and real-time report self-detection result.Calibration software comprises start calibration, user's calibration and device self calibration three parts, is the very important measures that device realizes stability index, by the calibration to hardware module, makes it to reach optimum Working.
(4) module initially controls: complete the state modulator to hardware circuit state according to test target, and it mainly comprises, and instrumental keyboard controls, module controls, and concrete comprises:
Synthesis local oscillator controls: the FREQUENCY CONTROL mainly completing synthesis local oscillator, and eat dishes without rice or wine to access frequency according to different mode terminal, sending controling instruction produces correct local frequency, ensures the correctness of radio frequency reception;
Radio frequency reception controls: the power and the FREQUENCY CONTROL that complete radio-frequency channel, channel switch control etc.;
Digital intermediate frequency controls: mainly complete the control of high-speed a/d converter and FPGA digital processing etc.;
Real-time analysis controls: the state modulator completing the realtime frame synchronization to FPGA, timer and TPC template;
Wherein module controls is mainly the control of main control software to FPGA, and described real-time detection and storing of catching pulse signal power device is in real time completed by hardware FPGA completely.Software sub-process in described module controls comprises: first main control software removes all flag bits, start the frame synchronization timing device of FPGA, and trigger delay configuration is carried out to TPC trigger module, ensure that measured terminal is in various stepping-in amount (1dB, 2dB or 3dB) situation, TPC signal from keep maximum to reduce time change point remain that position is fixed, the overall process of true representation measured terminal changed power, then send TPC instruction, TPC test process starts.When main control software detects complement mark position, represent a close-loop power control process and terminate, namely read the test data in dual port RAM.
(5) data acquisition and procession, interface Read-write Catrol, measurement result display: three is man-machine interface portion, completes the Graphics Processing of complete machine, measures interaction process, provides perfect help information.
During use, refer to Fig. 4, described pulse signal power device of catching in real time is between measured terminal and radio frequency mobile terminal comprehensive test instrument, interconnected by radio frequency cable with power splitter, namely measured terminal and terminal comprehensive test instrument are set up signaling loop and are caught pulse signal power device in real time and be in and monitor and detection position, and measured terminal is up to transmit and export this device to through power splitter.This device does not need outer triggering signal, can detect in real time, catch and memory mobile terminal (such as mobile phone) uplink service signal.
Describedly catch that pulse signal power device is rational in infrastructure in real time, design principle is simple, be easy to expansion, with low cost, function height is integrated, automatic extraction frame synchronization, realize detecting in real time fast mobile terminal TPC index, be applicable to the detection comprising the terminal transmission signal pulse time slot powers such as time-multiplexed TD-LTE-A/TD-LTE/TD-SCDMA/GSM.
The foregoing is only embodiment of the present utility model; not thereby the scope of the claims of the present utility model is limited; every utilize the utility model specification and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.
Claims (5)
1. catch pulse signal power device in real time for one kind, comprise Receiver Module, industrial computer control module, it is characterized in that, also comprise the data intermediate frequency module be connected with Receiver Module respectively, local oscillator module, referrer module and the eisa bus intercomed mutually with each module, Receiver Module comprises the receiving attenuation device be connected successively, first self oscillating mixer, first if bandpas filter, second self oscillating mixer, second if bandpas filter, local oscillator module is made up of phase-locked loop, its output connects the first self oscillating mixer of Receiver Module, referrer module comprises crystal oscillator, the phase-locked loop be connected with crystal oscillator, crystal oscillator respectively with local oscillator module, data intermediate frequency module is connected, the output of referrer module is connected with the second self oscillating mixer of Receiver Module, data intermediate frequency module comprises clock distributor, the data acquisition module be connected successively, FPGA, eisa bus interface, clock distributor respectively with data acquisition module, FPGA is connected.
2. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, the data acquisition module of described data intermediate frequency module is connected with the second if bandpas filter of Receiver Module, and data acquisition module comprises the amplifier connected successively, frequency overlapped-resistable filter, A/D converter, FPGA comprises the Digital Down Converter Module be connected successively, abstraction module, filter, effective value detection module, what be connected with effective value detection module output respectively catches pulse along module and power peak search module, frame synchronization timing device, start trapping module, realtime power memory module, dual port RAM, with start the TPC trigger module and control logic module that trapping module input is connected, wherein power peak search module with catch the output of pulse along module and be connected with frame synchronization timing device respectively, the input of eisa bus interface is connected with dual port RAM, output is connected with TPC trigger module and control logic module, clock distributor respectively with the A/D converter of data acquisition module, the DCM of FPGA is connected.
3. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, described phase-locked loop is made up of end to end voltage controlled oscillator, loop filter, phase discriminator.
4. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, the crystal oscillator of described referrer module is connected with the phase discriminator of local oscillator module, the clock distributor of data intermediate frequency module respectively.
5. according to claim 1ly catch pulse signal power device in real time, it is characterized in that, described industrial computer control module comprises main control module, interface module, display module, operating system, Switching Power Supply.
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| CN201420867049.2U CN204305039U (en) | 2014-12-30 | 2014-12-30 | Catch pulse signal power device in real time |
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| CN201420867049.2U CN204305039U (en) | 2014-12-30 | 2014-12-30 | Catch pulse signal power device in real time |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104539383A (en) * | 2014-12-30 | 2015-04-22 | 中国电子科技集团公司第四十一研究所 | Real-time pulse signal power capturing device and implement method thereof |
| CN109407057A (en) * | 2018-11-29 | 2019-03-01 | 武汉大学 | A kind of signal source of S-band wave observation radar |
| CN114244384A (en) * | 2021-12-20 | 2022-03-25 | 浙江嘉科电子有限公司 | Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver |
-
2014
- 2014-12-30 CN CN201420867049.2U patent/CN204305039U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104539383A (en) * | 2014-12-30 | 2015-04-22 | 中国电子科技集团公司第四十一研究所 | Real-time pulse signal power capturing device and implement method thereof |
| CN104539383B (en) * | 2014-12-30 | 2017-05-10 | 中国电子科技集团公司第四十一研究所 | Real-time pulse signal power capturing device and implement method thereof |
| CN109407057A (en) * | 2018-11-29 | 2019-03-01 | 武汉大学 | A kind of signal source of S-band wave observation radar |
| CN109407057B (en) * | 2018-11-29 | 2023-08-29 | 武汉大学 | Signal source of S-band wave-measuring radar |
| CN114244384A (en) * | 2021-12-20 | 2022-03-25 | 浙江嘉科电子有限公司 | Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver |
| CN114244384B (en) * | 2021-12-20 | 2023-06-16 | 浙江嘉科电子有限公司 | Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver |
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Effective date of registration: 20190318 Address after: 266000 No. 98 Xiangjiang Road, Huangdao District, Qingdao City, Shandong Province Patentee after: CHINA ELECTRONICS TECHNOLOGY INSTRUMENTS Co.,Ltd. Address before: 233006 Mailbox 101, 726 Zhengzheng Road, Bengbu City, Anhui Province Patentee before: THE 41ST INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY Group Corp. |
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