CN114244384B - Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver - Google Patents
Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver Download PDFInfo
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Abstract
The invention provides a continuous wave peak value capturing circuit and a continuous wave peak value capturing method for a zero intermediate frequency receiver, wherein the continuous wave peak value capturing circuit for the zero intermediate frequency receiver comprises an FPGA input end and an FPGA output end which are arranged on an FPGA, and further comprises a control module, an FFT module and a peak value detection module which are arranged on the FPGA, wherein the FPGA input end comprises an FPGA input signal, the FPGA input signal comprises two quadrature digital baseband signals, the control module outputs the control signal to the FFT module and the peak value detection module, the FFT module outputs the signal to the peak value detection circuit, and the peak value detection circuit is connected with the FPGA output end. The invention can be realized in a digital domain and can be used for a continuous wave peak value capturing circuit of a zero intermediate frequency receiver, can simplify the design of a radio frequency front end, adopts a monolithically integrated radio frequency transceiver chip with a zero intermediate frequency architecture, can complete the whole application design by matching with a small amount of peripheral auxiliary circuits, and can reduce the design difficulty, save the development cost and accelerate the development speed.
Description
Technical Field
The invention belongs to the technical field of field programmable gate array development, and particularly relates to a continuous wave peak value capturing circuit for a zero intermediate frequency receiver.
Background
The radio spectrum is an extremely important strategic resource, and it is essential to recognize and manage the radio spectrum. The continuous peak value capturing circuit has important practical significance in the fields of radio spectrum management, radio spectrum interference, interference resistance and the like.
The capturing of the maximum value of the signal in the traditional analog domain often needs complicated hardware circuits, occupies a large volume and has low reliability, and meanwhile, the capturing of the maximum value of the signal also needs large investment of manpower and material resources and has low economic benefit.
The zero intermediate frequency transceiver of the current monolithic integration is mature, the performance is gradually excellent, and the product is more reliable. While the peak capture circuit for this type of transceiver must be implemented in the digital domain. There is therefore a great need in the industry for a continuous wave peak acquisition circuit implemented in the digital domain that can be used in a zero intermediate frequency receiver. And a continuous wave peak value capturing circuit implemented in the digital domain that can be used in a zero intermediate frequency receiver is not disclosed.
Disclosure of Invention
The invention aims to solve the problems, and provides a continuous wave peak value capturing circuit and a continuous wave peak value capturing method for a zero intermediate frequency receiver, which can be realized in a digital domain and can be used for the zero intermediate frequency receiver, and the continuous wave peak value capturing circuit has the advantages of low design difficulty, low cost, good productivity and short research and development period.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the utility model provides a continuous wave peak value capture circuit for zero intermediate frequency receiver, including setting up FPGA input and the FPGA output on the FPGA, still including set up in control module, FFT module and peak detection module on the FPGA, the FPGA input includes the FPGA input signal, the FPGA input signal includes two quadrature digital baseband signals, control module output control signal is to FFT module and peak detection module, FFT module output signal is to peak detection circuit, peak detection circuit connects the FPGA output. The FPGA input end comprises two orthogonal digital baseband signals, and can be connected with a front-stage radio frequency channel of orthogonal demodulation, so that a monolithic integrated transceiver chip of the existing zero intermediate frequency architecture can be matched with a continuous wave peak value capturing circuit for a zero intermediate frequency receiver, and the design of the front-end radio frequency channel can be simplified; the invention processes two orthogonal digital baseband signals in the FPGA, thereby realizing signal detection, and simultaneously adopting a control module, an FFT module, a peak detection module and other basic modules, realizing modular design, and reducing design difficulty by only mainly designing control logic by researchers; in addition, the invention has lower cost under the condition of large-scale mass production in the FPGA.
Further, the FPGA input terminal further includes a global clock signal (clk) and a reset signal (rstn) input to the control module, the FFT module, and the peak detection module, and further includes an FPGA input control parameter input to the control module.
Further, the FPGA input signal is input to the FFT module and includes a first quadrature digital baseband signal (I) and a second quadrature digital baseband signal (Q), and the FPGA input control parameter includes a detection period (detp), the number of FFTs in a single period (ctpc), a detection threshold level (detl), and the number of FFT points (nfft). The first quadrature digital baseband signal (I) and the second quadrature digital baseband signal (Q) of the present invention are suitable for use in a zero intermediate frequency receiver. The input parameters of the invention are used for setting the working state of each module, and the accuracy of peak value capturing can be improved to a certain extent by adjusting each parameter.
Further, the output end of the FPGA comprises a maximum peak value (map), a frequency serial number (midx) corresponding to the maximum peak value and an output end valid indication signal (vld). The signals at the output end of the FPGA are provided for a user, and the signal strength, the signal frequency and whether the current output is effective or not can be represented respectively.
Further, the control module comprises a control module input end, a detection period timing module for detecting period timing, a single-period in-detection counting module for counting FFT times in a single period, a parameter forwarding control module for parameter forwarding and a control module output end;
the detection period timing module is in communication connection with the single-period internal detection metering module, the single-period internal detection metering module is in communication connection with the parameter forwarding control module, and the detection period timing module is in communication connection with the parameter forwarding control module.
Further, the control module output end outputs a first control signal (ctrl 1) and a second control signal (ctrl 2), wherein the first control signal (ctrl 1) is connected with and controls the FFT module, and the second control signal (ctrl 2) is connected with and controls the peak detection module. The first control signal (ctrl 1) and the second control signal (ctrl 2) can be used for controlling the start and stop of each module to realize period detection.
Further, the FFT module comprises an FFT core for fast Fourier transform and a RAM module for ordering the results output by the FFT core according to the frequency; the FFT module outputs a first signal (Amp) and a second signal (Idx) to a peak detection module.
Further, the peak detection module comprises a super-threshold interval detection module for detecting an interval exceeding a threshold level in a single FFT, a single interval peak detection module for detecting signal peaks in each interval, a full interval peak detection module for detecting the maximum value of the signal peaks in each interval and a period peak detection module for detecting the signal peak in each detection period; the super-threshold interval detection module, the single-interval internal peak detection module, the full-interval peak detection module and the periodic peak detection module are sequentially in communication connection.
The invention also provides a continuous wave peak value capturing method for the zero intermediate frequency receiver, which comprises the following specific steps:
s1, power-on reset, initializing and configuring all parameters of a continuous peak value capturing circuit of the zero intermediate frequency receiver, and starting a control module, an FFT module and a peak detection module;
s2, a single-period in-detection counting module in the control module starts to count times in a detection period, and when the count times in the period reach a target value, the control module outputs a control signal to control the FFT module and the peak detection module to stop;
and S3, simultaneously, a detection period timing module in the control module starts detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the in-period counting module to restart, and starts a new detection round.
Further, when the FFT module is started, the FFT in the FFT module checks the first quadrature digital baseband signal (I) and the second quadrature digital baseband signal (Q) to do FFT point number fast Fourier transform and output, and the result output by the FFT core is ordered from low to high according to frequency by the RAM module in the FFT module and the first signal (Amp) and the second signal (Idx) are output to the peak detection module;
the peak detection module receives the signal output by the FFT and completes continuous wave peak detection in each detection period, and finally outputs a maximum peak value (mamp), a frequency serial number (midx) corresponding to the maximum peak value and an output end effective indication signal (vld), which are specifically as follows: and the whole-interval peak value detection module screens out the maximum value and the corresponding frequency sequence number in all marked intervals by a successive comparison method, and records and the periodic peak value detection module screens out the signal maximum value and the corresponding frequency sequence number in a single detection period by the successive comparison method.
Compared with the prior art, the invention has the advantages that:
1. the continuous wave peak value capturing circuit for the zero intermediate frequency receiver can be realized in a digital domain and can be used for the continuous wave peak value capturing circuit of the zero intermediate frequency receiver, the design of the radio frequency front end can be simplified, the monolithic integrated radio frequency transceiver chip with the zero intermediate frequency architecture is adopted, the whole application design can be completed by matching with a small amount of peripheral auxiliary circuits, the design difficulty can be reduced, the development cost can be saved, and the development speed can be accelerated;
2. the invention can solve the problem of continuous wave signal reconnaissance, can be used in frequency spectrum control equipment, is convenient for a management department to discover the frequency spectrum use problem in time and avoids risks; the method can also be used in interference equipment to realize aiming interference and reduce unnecessary energy loss.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
FIG. 1 is a schematic diagram of a continuous wave peak value capturing circuit for a zero intermediate frequency receiver according to the present invention;
fig. 2 is a flow chart of a continuous wave peak value capturing method for a zero intermediate frequency receiver according to the present invention.
In the figure, a global clock signal clk, a reset signal rstn, a quadrature digital baseband signal I, a quadrature digital baseband signal Q, a detection period detp, FFT times ctpc in a single period, a detection threshold level detl and FFT points nfft; maximum peak value mamp, frequency serial number midx corresponding to maximum peak value, output end effective indication signal vld; a first control signal ctrl1, a second control signal ctrl2; the first signal Amp and the second signal Idx.
Detailed Description
In order to enable those skilled in the art to better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
Example 1
As shown in fig. 1, the continuous wave peak value capturing circuit for the zero intermediate frequency receiver of the embodiment comprises an FPGA input end and an FPGA output end which are arranged on an FPGA, and further comprises a control module, an FFT module and a peak value detection module which are arranged on the FPGA, wherein the FPGA input end comprises an FPGA input signal, the FPGA input signal comprises two orthogonal digital baseband signals, the control module outputs two control signals to the FFT module and the peak value detection module respectively, the FFT module outputs signals to the peak value detection circuit, and the peak value detection circuit is connected with the FPGA output end. The input end of the FPGA of the embodiment comprises two orthogonal digital baseband signals which can be connected with a front-stage radio frequency channel of orthogonal demodulation, so that a monolithic integrated transceiver chip of the existing zero intermediate frequency architecture can be matched with a continuous wave peak value capturing circuit of the zero intermediate frequency receiver of the embodiment, and the design of the front-end radio frequency channel can be simplified; in the embodiment, two orthogonal digital baseband signals are processed in the FPGA, so that signal detection can be realized, meanwhile, basic modules such as a control module, an FFT module, a peak detection module and the like are adopted, modular design can be realized, and researchers only need to design control logic in a key way, so that the design difficulty is reduced; in addition, the embodiment has lower cost under the condition of large-scale mass production in the FPGA.
The FPGA input end of the present embodiment further includes a global clock signal clk and a reset signal rstn input to the control module, the FFT module, and the peak detection module, and further includes FPGA input control parameters input to the control module. The input signals of the FPGA in the embodiment are input to an FFT module and comprise a first quadrature digital baseband signal I and a second quadrature digital baseband signal Q, and the input control parameters of the FPGA comprise a detection period detp, FFT times ctpc in a single period, a detection threshold level detl and FFT point number nfft. The first quadrature digital baseband signal I and the second quadrature digital baseband signal Q of this embodiment are suitable for a zero intermediate frequency receiver. The parameters can be used for setting the working state of each module, and the accuracy of peak value capturing can be improved to a certain extent by adjusting each parameter.
The output end of the FPGA of the embodiment comprises a maximum peak value mamp, a frequency serial number midx corresponding to the maximum peak value and an effective indication signal vld of the output end. Where the signal is provided to the user, characterizing the signal strength, signal frequency, and whether the current output is valid, respectively, where a vld high level indicates that the output is valid. The control module of the embodiment comprises a control module input end, a detection period timing module for detecting period timing, a single-period in-detection counting module for counting FFT times in a single period, a parameter forwarding control module for parameter forwarding and a control module output end; the detection period timing module is in communication connection with the single-period internal detection metering module, the single-period internal detection metering module is in communication connection with the parameter forwarding control module, and the detection period timing module is in communication connection with the parameter forwarding control module.
The output end of the control module of this embodiment outputs a first control signal ctrl1 and a second control signal ctrl2, where the first control signal ctrl1 is connected to and controls the FFT module, and the second control signal ctrl2 is connected to and controls the peak detection module. In this embodiment, the first control signal ctrl1 and the second control signal ctrl2 are used to control the start and stop of each module, so as to implement cycle detection.
The FFT module of the embodiment comprises an FFT core for fast Fourier transform and a RAM module for ordering the output result of the FFT core according to the frequency; the FFT module outputs a first signal Amp and a second signal Idx to the peak detection module. In this embodiment, the first signal Amp is the amplitude, and the second signal Idx is the natural order 0-nfft-1. The RAM module in this embodiment may adopt a single port mode, and adopts a read-before-write mode, that is, the result generated by the FFT core is first stored into the RAM from low to high according to the address, and then the RAM address is mapped from low to high according to the frequency, so as to read the data as a whole.
The peak detection module of the embodiment comprises a super-threshold interval detection module for detecting an interval exceeding a threshold level in a single FFT, a single interval peak detection module for detecting signal peaks in each interval, a full interval peak detection module for detecting the maximum value of the signal peaks in each interval and a period peak detection module for detecting the signal peak in each detection period; the super-threshold interval detection module, the single-interval internal peak detection module, the full-interval peak detection module and the periodic peak detection module are sequentially in communication connection.
The design inputs of the circuit of this embodiment include the first quadrature digital baseband signal I and the second quadrature digital baseband signal Q, thus necessarily requiring that the front-end radio frequency channel be quadrature demodulated, so that the zero intermediate frequency architecture monolithically integrated transceiver chip is adapted to the circuit of this embodiment, which simplifies the design of the front-end radio frequency channel. In the embodiment, the first quadrature digital baseband signal I and the second quadrature digital baseband signal Q are processed in the FPGA, so that signal detection is realized, the base modules such as FFT, RAM and the like, and the counter and the like are adopted, modular design is realized, and researchers only need to focus on designing control logic, so that the design difficulty is reduced. Furthermore, the embodiment has the further advantage of good productivity, and the embodiment only needs to be burnt into a proper FPGA device, so that the cost is lower under the condition of large-scale mass production. Therefore, the embodiment can be realized in a digital domain and can be used for a continuous wave peak value capturing circuit of a zero intermediate frequency receiver, the design of a radio frequency front end can be simplified, a monolithically integrated radio frequency transceiver chip with a zero intermediate frequency architecture is adopted, the whole application design can be completed by matching with a small amount of peripheral auxiliary circuits, the design difficulty can be reduced, the development cost can be saved, and the development speed can be accelerated.
The continuous wave crest value capturing circuit for the zero intermediate frequency receiver can be used in spectrum control equipment, so that a management department can find spectrum use problems in time, and risks are avoided; the method can also be used in interference equipment to realize aiming interference and reduce unnecessary energy loss.
Example 2
This embodiment differs from embodiment 1 in that: the RAM module of the embodiment adopts a dual-port mode, and simultaneously performs read-write operation, namely, the RAM addresses are mapped from low to high according to the frequency, and then each address space of the RAM is subjected to the read-write operation before the read operation, so that the running speed of the circuit can be improved.
Example 3
As shown in fig. 2, the present embodiment provides a continuous wave peak value capturing method for a zero intermediate frequency receiver, which includes a continuous wave peak value capturing circuit for a zero intermediate frequency receiver as described in embodiment 1 or embodiment 2, and specifically includes the following steps:
s1, power-on reset, initializing and configuring all parameters of a continuous peak value capturing circuit of the zero intermediate frequency receiver, and starting a control module, an FFT module and a peak detection module;
s2, a single-period in-detection counting module in the control module starts to count times in a detection period, and when the count times in the period reach a target value, the control module outputs a control signal to control the FFT module and the peak detection module to stop;
and S3, simultaneously, a detection period timing module in the control module starts detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the in-period counting module to restart, and starts a new detection round.
When the FFT module is started, the FFT in the FFT module checks the first quadrature digital baseband signal I and the second quadrature digital baseband signal Q to perform FFT point number fast Fourier transform and output, and the output result of the FFT module is ordered from low to high according to frequency through the RAM module in the FFT module and outputs a first signal Amp and a second signal Idx to the peak detection module;
the peak detection module receives the signal output by the FFT and completes continuous wave peak detection in each detection period, and finally outputs a maximum peak value mamp, a frequency serial number midx corresponding to the maximum peak value and an output end effective indication signal vld, which specifically comprises the following steps: and the whole-interval peak value detection module finds out the maximum value and the corresponding frequency sequence number in all marked intervals by a successive comparison method, and records, and the periodic peak value detection module finds out the signal maximum value and the corresponding frequency sequence number in a single detection period by the successive comparison method, records and outputs the peak value of the continuous wave in one detection period.
The specific embodiments described herein are offered by way of example only to illustrate the spirit of the invention. Those skilled in the art may make various modifications or additions to the described embodiments or substitutions thereof without departing from the spirit of the invention or exceeding the scope of the invention as defined in the accompanying claims.
Claims (8)
1. The continuous wave peak value capturing circuit for the zero intermediate frequency receiver comprises an FPGA input end and an FPGA output end which are arranged on an FPGA, and is characterized by further comprising a control module, an FFT module and a peak value detection module which are arranged on the FPGA, wherein the FPGA input end comprises an FPGA input signal, the FPGA input signal comprises two orthogonal digital baseband signals, the control module outputs the control signal to the FFT module and the peak value detection module, the FFT module outputs the signal to the peak value detection circuit, and the peak value detection circuit is connected with the FPGA output end;
the FPGA input signal is input to an FFT module and comprises a first quadrature digital baseband signal (I) and a second quadrature digital baseband signal (Q), and the FPGA input control parameters comprise a detection period (detp), FFT times (ctpc) in a single period, a detection threshold level (detl) and FFT points (nfft);
the control module comprises a control module input end, a detection period timing module for detecting period timing, a single-period in-detection counting module for counting FFT times in a single period, a parameter forwarding control module for parameter forwarding and a control module output end;
the detection period timing module is in communication connection with the single-period internal detection metering module, the single-period internal detection metering module is in communication connection with the parameter forwarding control module, and the detection period timing module is in communication connection with the parameter forwarding control module.
2. A continuous wave peak capture circuit for a zero intermediate frequency receiver according to claim 1, wherein the FPGA input further includes a global clock signal (clk) and a reset signal (rstn) input to the control module, the FFT module and the peak detection module, and further includes FPGA input control parameters input to the control module.
3. A continuous wave peak capturing circuit for a zero intermediate frequency receiver according to claim 1, wherein the FPGA output includes a maximum peak value (mamp), a frequency number (midx) corresponding to the maximum peak value, and an output valid indication signal (vld).
4. A continuous wave peak acquisition circuit for a zero intermediate frequency receiver according to claim 1, characterized in that the control module output outputs a first control signal (ctrl 1) and a second control signal (ctrl 2), the first control signal (ctrl 1) being connected to and controlling the FFT module, the second control signal (ctrl 2) being connected to and controlling the peak detection module.
5. The continuous wave peak value capturing circuit for zero intermediate frequency receiver according to claim 1, wherein said FFT module comprises a FFT core for fast fourier transform and a RAM module for ordering the results of FFT core output by frequency in high and low order, which are communicatively connected; the FFT module outputs a first signal (Amp) and a second signal (Idx) to a peak detection module.
6. The continuous wave peak capturing circuit for zero intermediate frequency receiver according to claim 1, wherein the peak detection module comprises a super-threshold section detection module for detecting a section exceeding a threshold level in a single FFT, a single section peak detection module for detecting signal peaks in respective sections, a full section peak detection module for detecting a maximum value of signal peaks in respective sections, and a period peak detection module for detecting signal peaks in each detection period; the super-threshold interval detection module, the single-interval internal peak detection module, the full-interval peak detection module and the periodic peak detection module are sequentially in communication connection.
7. A continuous wave peak value capturing method for a zero intermediate frequency receiver, comprising a continuous wave peak value capturing circuit for a zero intermediate frequency receiver according to any one of claims 1 to 6, comprising the steps of:
s1, power-on reset, initializing and configuring all parameters of a continuous peak value capturing circuit of the zero intermediate frequency receiver, and starting a control module, an FFT module and a peak detection module;
s2, a single-period in-detection counting module in the control module starts to count times in a detection period, and when the count times in the period reach a target value, the control module outputs a control signal to control the FFT module and the peak detection module to stop;
and S3, simultaneously, a detection period timing module in the control module starts detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the in-period counting module to restart, and starts a new detection round.
8. A continuous wave peak value capturing method for zero intermediate frequency receiver according to claim 7, wherein when said FFT module is started, the FFT in the FFT module checks the first quadrature digital baseband signal (I) and the second quadrature digital baseband signal (Q) to make FFT point number fast fourier transform and output, and the result of FFT kernel output is ordered from low to high frequency by the RAM module in the FFT module and outputs the first signal (Amp) and the second signal (Idx) to the peak detection module;
the peak detection module receives the signal output by the FFT and completes continuous wave peak detection in each detection period, and finally outputs a maximum peak value (mamp), a frequency serial number (midx) corresponding to the maximum peak value and an output end valid indication signal (vld), which are specifically as follows: and the whole-interval peak value detection module screens out the maximum value and the corresponding frequency sequence number in all marked intervals by a successive comparison method, and records and the periodic peak value detection module screens out the signal maximum value and the corresponding frequency sequence number in a single detection period by the successive comparison method.
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