CN105391497B - A kind of 433M digital FM receivers - Google Patents
A kind of 433M digital FM receivers Download PDFInfo
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- CN105391497B CN105391497B CN201510726790.6A CN201510726790A CN105391497B CN 105391497 B CN105391497 B CN 105391497B CN 201510726790 A CN201510726790 A CN 201510726790A CN 105391497 B CN105391497 B CN 105391497B
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- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
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Abstract
Patent of the present invention is related to digital FM receiver field, and in particular to a kind of 433M digital FM receivers.Including：Input terminal low-noise amplifier and 433M filter segments；392.3M local vibration source signal circuit sections；Frequency mixer and intermediate-frequency filter part；Demodulate secondary frequency down circuit part；Microcontroller micro-process part；The power supply control of whole circuit diagram and ground part.The 433M digital FM receiver devices that patent of the present invention provides are ingenious in design, rationally distributed, and low in energy consumption, high sensitivity, dynamic range are big, using the modulation /demodulation pattern of 2FSK, can carry out real-time Communication for Power with 433M Digital Frequency Modulation Transmitters well.Patent of the present invention all there is very high scientific research to be worth in 433M digital FM receivers field and ultra short wave communication field, while also have certain engineering application value.
Description
Technical field
Patent of the present invention is related to digital FM receiver field, and in particular to a kind of 433M digital FM receivers.
Background technology
Existing receiver type mainly has phase modulation, FM receiver and AM receiver, and FM receiver is the most commonly used.
Wherein FM receiver species has following several, has superhet frequency conversion receiver, image frequency suppression receiver, zero intermediate frequency to receive
Machine and digital radio frequency receiver etc..The function of of coursing digital radio frequency receiver is best.
For superhet frequency conversion receiver, its main advantage is, simple in structure, be easily achieved, although
Its structure is simple, but up to the present, superhet frequency conversion receiver is still the most common structure shape of engineers
Formula.The shortcomings that superhet frequency conversion receiver is that superhet frequency conversion receiver needs more high performance filter and mixes
Frequency device completes whole reception system, this has resulted in the reception of the relatively other species of volume of superhet frequency conversion receiver
Body product it is larger, certainly this also just cause therewith it manufacture cost it is higher than the receiver of other species.The secondary change of superhet
Frequency receiver can be by selecting appropriate IF frequency value and intermediate-frequency filter come the preferable frequency selectivity obtained and reception
The technical indicators such as clever sensitivity, so superhet double conversion reception system is considered as most reliable receiver structure, certainly
With being also most commonly used.Patent 433M digital FM receivers of the present invention also have double conversion.
For zero intermediate frequency reciver, its main advantage is, small, cost is low, is easy to single-chip integration etc..
The preferable Image interference rejection ability of zero intermediate frequency reciver structural requirement, because the power level of its image disturbing signal is necessary
It is required that the power level less than or equal to required demodulated signal.Since zero intermediate frequency reciver is directly acted on by a local oscillation signal
Down-conversion signal, relative to superhet, zero intermediate frequency reciver reduces optical mixing process.Generally speaking, zero intermediate frequency receives
Machine structure is to be made good in terms of reducing design cost, reducing chip area and reduce power consumption.Zero intermediate frequency reciver is in nothing
Application in the line communications field more comes also extensive.
China's software radio technilogy was grown rapidly in recent years, and digital radio frequency receiver technology is also come into being therewith.Number
Word radio-frequency transmitter is to use Digital Signal Processing skill after one kind is digitized modulated signal by analog-digital converter
Art carries out modulated signal the radio-frequency transmitter of the digital signal processings such as digital frequency conversion, digital filtering, digital demodulation in fact.Number
The various technical indicators of word receiver can realize relatively digitized expression, and digital receiver has compared to analog receiver
Have a lot of advantages, for example, his sensitivity accuracy is high, stability is good, flexible design and it can realize many analog receivers
Irrealizable sophisticated functions, generally speaking digital receiver it have become in the various systems of receiver and most have development potentiality
A kind of structure type.And patent 433M digital FM receivers of the present invention are exactly the one kind for belonging to digital radio frequency receiver.
The content of the invention
It is an object of the invention to provide the 433M digital FM receivers that a kind of sensitivity accuracy is high, stability is good.
The object of the present invention is achieved like this：
The present invention includes：Input terminal low-noise amplifier and 433M filter segments；392.3M local vibration source signal circuit portion
Point；Frequency mixer and intermediate-frequency filter part；Demodulate secondary frequency down circuit part；Microcontroller micro-process part；Whole circuit diagram
Power supply controls and ground part, it is characterised in that：Signal is entered by input terminal low-noise amplifier and 433M filter segments；
392.3M local vibration sources signal circuit section provides local oscillation signal, 392.3MHz to frequency mixer and intermediate-frequency filter part；Signal from
Input terminal low-noise amplifier and 433M filter segments complete first after coming out in frequency mixer and intermediate-frequency filter part
Secondary frequency reducing, 40.7M is reduced to by 433M；Demodulation second of frequency reducing of secondary frequency down circuit part progress is entered back into from 40.7M to be changed into
10.7M, is then demodulated；Microcontroller micro-process part controls 392.3M local vibration sources signal circuit section and the secondary drop of demodulation
Frequency circuit part；The power supply of whole circuit diagram controls and ground part is module 392.3M local vibration source signal circuit sections；；Demodulation two
Secondary frequency down circuit part；Microcontroller micro-process part provides numeral and analog power and earth signal；
Input terminal low-noise amplifier and 433M filter segments：
Use low noise amplifier MAX2650；Signal is entered by the tuner P1 of module 1, by 433M SAW filter cores
Go out into 1 pin of the RF2418DS chips of module 3 port 5 of piece U4；P1 is tuner, and tuner is connected to after antenna,
The ripple of all frequency ranges including 433M carrier waves is included, entering chip U3 low-noise amplifiers MAX2650 by P1 carries out power amplification,
Next stage is exported by port 3 after amplification, what port 4 connected is+5V power supplies, and port 2 is grounded；Low-noise amplifier
The supply voltage of MAX2650 is+5V, the capacitance C11 and magnetic bead L4 of the capacitance C10 and polarized 10uf of 0.1uf to power supply into
Row filters, and the blocking capacitance value at the input/output interface of MAX2650 is：
Wherein, the unit of frequency F is MHz, and the carrier frequency of receiver is 433MHz, the electricity of MAX2650 input/output terminals
Capacitance is 122pF；Its both ends must add the capacitance C101 and capacitance C102 of 0.1uf, direct current signal is filtered, U4 is
433MHz SAW filters, are entered by 2 pins, and the pin 1 of the RF2418DS chips of module 3 is output to from 5 pins；
392.3M local vibration source signal circuit sections：
4,5 pins of ADF4360-8 chips are connected to 8 pipes of frequency mixer and the RF2418DS chips of intermediate-frequency filter part
Foot；The minimum system that MSP430F149 singlechip chips are formed is controlled ADF4360-8 chips, produces the local oscillator of 392.3M
Frequency；Voltage controlled oscillator output frequency inside ADF4360-8 chips is：
fVCO=[(P × B)+A] × fREFIN/R
Wherein fVCOFor voltage controlled oscillator output frequency, P is pre- frequency division coefficient, fREFINFor reference frequency；
Fcco=B × Frefin/R
FccoBe phaselocked loop output frequency, Fcco=392.3M, B are the binary registers of 13, its value range is 3
~8191, Frefin are 16 pin REF of ADF4360-8 chipsinThe frequency for having source crystal oscillator of input, R is that the binary system of 14 is posted
Storage, Frefin select 50M, R=500, B=3923；16 pin REF of ADF4360-8 chipsinWhat is connect is that 50M has source crystal oscillator
U12；The CPGND of 1 pin, the AGND of 3 pins, the AGND of 8 pins, the AGND of 11 pins, 12 pin Cc, 15 pins DGND,
The AGND of 22 pins all connect simulation i.e. GND；Take the supply voltages of+3.3V as phaselocked loop ADF4360-8 chips, 2 pins
Avdd, the Vvco of 6 pins, the Dvdd of 21 pins, the CE of 23 pins connect the power supply of+3.3V, each power supply need connection and
The same filter circuit in module 1；Voltage stabilizing the piece AMS1117-3.3, U13 that chip U13 is+3.3V are phaselocked loop ADF4360-8
The voltage of chip offer+3.3.V, the input of 3 pins, the output of 2 pins, input is+5V power supplys, and output is exactly+3.3V；9 pin L1、
10 pin L2Resistance R32, a R33 and inductance L29, a L30 are all met respectively, and wherein resistance R32, R33 is 470 Ω；Electricity
Inductance value：
In formula, FoIt is 392.3M, Lext is required inductance value, Lext=16.8nH；17 pin CLK, 18 pins
DATA, 19 pin LE are connected on MSP430F149 singlechip chips, are connected to I/O port 5.3,5.1,5.4, resistance R22, R24,
R2 is 0 Ω, and 20 pin MUXOUT are connected with LED light D3, and 24 pin CP meet a low-pass filter, 16 pin REFinMeet 50M
Have source crystal oscillator, filter circuit need to be connected by being connected with the power supply of source crystal oscillator, there is source crystal oscillator pin 3 and phaselocked loop ADF4360-8 cores
The 50 Ω resistors match circuits that piece pin 16 extracts are connected directly the resistance R26 groups of capacitance C73, C75 and 51 Ω by 1nF
Into；Resistance R27, R28, the tuner P12 of 0 Ω is external to frequency spectrograph, for testing the frequency of phaselocked loop ADF4360-8 chips generation
Whether rate is 392.3MHz, and the local frequency that phaselocked loop ADF4360-8 chips produce is output to frequency mixer 8 from 4 pin RfoutA
Pin LO IN, the inductance L18 of the capacitance C44 and 10nH of the 4pF of 8 pin of the RF2418DS chips connection in module 3 complete lock phase
The resistors match of 50 Ω between ring ADF4360-8 chips and mixing chip RF2418DS；
Frequency mixer and intermediate-frequency filter part：
U5 chips are RF2418 mixer chips；The pin 1 of RF2418DS chips connect input terminal low-noise amplifier and
The port 5 of the U4 chips of 433M filter segments, the pin 8 of RF2418DS chips connect 392.3M local vibration source signal circuit sections
The RF In pins connection of the RfoutA of 4, the 5 pins connection of ADF4360-8 chips, U2 chips MAX2650 demodulate secondary frequency reducing electricity
1 pin of the U1 chips of road part；The inductance L12 of the resistance R8 and 10nH of the 5.11K that the pin 1 of RF2418 chips connects；3 pipes
Foot VDD1 connection+5V DC power supplies, 4 pin VDD2 do not have to connection, magnetic bead L13,10uF capacitance C34,47pF capacitance C32,0.1uF
Capacitance C35 forms filter circuit, and right+5V DC power supplies are filtered；By input terminal low-noise amplifier and 433M wave filters
Signal after partly coming out, enters frequency mixer RF2418 chips by pin 1LNA IN, enters 11 pipes by 14 pin LNA OUT
Foot RF IN, the signal after being mixed are input to the intermediate-frequency filter circuit part IN of this module by 6 pin IF2OUT,
The local oscillation signal for the 392.3MHz that 392.3M local vibration source signal circuit sections phaselocked loop produces is input to U5 frequency mixers by 8 pins
RF2418DS chips, the capacitance C44 and 10nH inductance L18 of 4pF complete 50 between ADF4360-8 chips and RF2418DS chips
The resistors match of Ω, circuit defaults connection at 7 pins, the 0.1uF capacitance C40 and 1.5K resistance R13 of 6 pins complete RF2418DS
The resistors match of 50 Ω between chip and the intermediate-frequency filter of this module；Intermediate-frequency filter part by 33pF capacitance C18,
The capacitance C20 compositions of inductance L7,33pF of capacitance C19,220nH of inductance L6,110pF of 220nH, signal enter from IN mouthfuls,
Go out from INI mouthfuls, IN mouthfuls that connect is the pin 6IF2OUT for being mixed chip RF2418DS, is come out at the IN of 6 pins, there is two-way
Signal, a frequency is 40.7M, the other is 825.3M, low-pass filter filters out the signal that 825.3M signals retain 40.7M；
Signal from INI mouthfuls out after enter next low-noise amplifier U2, the secondary frequency down circuit part of the connection demodulation of pin 3 of U2
The pin 1 of SA639 chips, the pin 4 of U2 connect+5V power supplys, power supply connection filter circuit, the input pin 1 of MAX2650 and defeated
Go out blocking filter capacitor C103 and C104 that pin 3 all connects 0.1uf；
Demodulate secondary frequency down circuit part：
Select U1 chips SA639 to complete secondary frequency reducing, 10.7M and demodulation are changed into from 40.7M；The intermediate-freuqncy signal of 40.7M by
The RF In pins of the U2 chips of module 3 enter 1 pin of the U1 chips for demodulating secondary frequency down circuit part；The inductance of 760nH
The capacitance C9 of the capacitance C6 and 16pF of L3,3pF complete frequency mixer and the MAX2650 low-noise amplifiers 50 of intermediate-frequency filter part
Resistors match between 800 Ω input resistances of Ω output resistances and SA639 demodulation chips；C1 pairs of the C8 and 1nF of 0.1 μ f
40.7M signals carry out blocking filtering；What 1,4,24 pins of SA639 demodulation chips were formed is a frequency mixer, and 2 pins are grounded, 3
Pin does not connect, and what 4 pins met 30M has a source crystal oscillator U6, and the 40.7M signals of 1 pin input are completed to be mixed together；By SA639
10.7M signals inside demodulation chip after filtering are exported by 24 pin MIXER OUT, by the ceramic filtering of first 10.7M
Ripple device PLT1 is filtered, and filtering for the first time is followed by 22 pin IF AMP IN, signal passing through inside SA639 demodulation chips again
20 pin IF AMP OUT are come, are then filtered again by the ceramic filter PLT2 of a 10.7M, after this time filtering
It is connected to 18 pin LIMITER；23rd, 21,16,17,19 pins ground connection GND；5 pin VCC connect+5V power supplys；6th, 7,8 pins acquiescence connects
Connect；The signal of 10.7M after filtering twice is come out by 15 pins, 90 degree of networks of a phase shift is connected, before making to enter
90 degree of 10.7M signal phase shifts, 90 degree of networks of this phase shift are by the C27 of C28,11pF of R7,15pF of L11,1.3K of 4.7uH
Composition, enters SA639 demodulation chips by 90 degree of 10.7M signals of phase shift by 14 pins；By the entrance of 18 pins without phase
Move 90 degree of 10.7M signals and by the 10.7M signals by 90 degree of phase shift that 14 pins enter into the multiplier inside SA639
It is multiplied, by that will produce two components after multiplier, one high fdrequency component of a low frequency component, low frequency component is exactly code
First signal；The connection of 9 pin of chip internal, 10 pin is all an operational amplifier, and the operational amplifier of 9 pins is completed to penetrate
With function, the operational amplifier of 10 pins is just electric with exterior 5.6K resistance R4,5.6K resistance R5,22pF capacitances C24,33pF
Hold C26 and connect and compose the active low-pass filter of two ranks, only retain the low frequency component of chip rate；The 12 of SA639 demodulation chips
Pin connects+2.5V power supplys, and the right+5V power supplys of resistance R9, R10 partial pressure that is averaged by being both 22K obtains, what 13 pins were connect
510 Ω resistance R6,10nF capacitances C25 also form low-pass filter, and the low frequency component of chip rate is filtered again；By 13
Pin come out be positive low frequency component, and by 11 pins come out be negative low frequency component, two paths of differential signals inputs together
To LM311 comparator chip U7, what it is from the output of 7 pin of LM311 comparators chip is exactly symbol square wave information；LM311 comparators
7 pins of chip are connected on the I/O port P5.5 of MSP430f149 chips U11, detection of preamble are carried out to information, frame extracts and shows
Ripple device shows symbol square wave information waveform；1, the 4 pins ground connection of comparator chip U7,5,6 pins do not connect, 7,8 pin connection+5V
Power supply ,+5V power supplys connection filter circuit；
Microcontroller micro-process part：
17 pin CLK, 18 pin DATA, the 19 pin LE of ADF4360-8 chips are connected to microcontroller micro-process part
The I/O port 5.3,5.1,5.4 of MSP430F149 singlechip chips, 7 pins of the LM311 comparator chips of module 4 are connected to
The I/O port P5.5 of MSP430f149 chips U11；P8 is emulator chip, and the minimum system of MSP430F149 singlechip chips is selected
Exterior 8M crystal oscillators XTCLK3, P5 is spare row's pin, and P10 meets row's pin of 12864 liquid crystal, U10 and J2 composition serial communications system
System, U11 are MSP430F149 singlechip chips, and LED liquid crystal D4 connection P1.0 pins, interrupt chip REST1 composition external interrupts
Circuit；The supply voltage of MSP430F149 singlechip chips is+3.3V, and U8 is the voltage stabilizing piece chip of+3.3V, and LED liquid crystal D2 connects
Connect+3.3V power supplys；+ 3.3V voltage stabilizing piece chip U13, the MSP430F149 microcontrollers of phaselocked loop ADF4360-8 chip analogue types
+ 3.3V voltage stabilizings the piece chip U8, voltage stabilizing piece U8 of chip numeric type have three pins, pin 1 is grounded, pin 3 be enter termination+
5V power supplys, pin 2 are output terminals, output+3.3V power supplys；
The power supply control of whole circuit diagram and ground part：
All digitally DGND and whole circuit that MSP430F149 singlechip chip minimum systems are connected remaining
All simulation ground GND link together；For+5V the power circuits of whole circuit power supply, the capacitance of capacitance C36,0.1uF of 10uF
C38 carries out the+5V power supplys of whole circuit blocking filtering, and the exterior+5V power supplys of LED liquid crystal D1 connections, J1 and DC-IN-2 are whole
+ 5V the electric outlet structures of circuit power supply.
The beneficial effects of the present invention are：
The 433M digital FM receiver devices that patent of the present invention provides are ingenious in design, rationally distributed, low in energy consumption, sensitivity
Height, dynamic range are big, using the modulation /demodulation pattern of 2FSK, can be led in real time with 433M Digital Frequency Modulation Transmitters well
Letter.Patent of the present invention all has very high scientific research valency in 433M digital FM receivers field and ultra short wave communication field
Value, while also there is certain engineering application value.
Brief description of the drawings
The complete machine schematic diagram of Fig. 1 patent 433M digital FM receiver devices of the present invention, can be clearly from schematic diagram
Find out the modules of schematic diagram.
Fig. 2 input terminals low-noise amplifier and 433M filter segment circuit diagrams, can will be apparent that finding out from this figure
The specific connection of this partial circuit.
Fig. 3 392.3M local vibration source signal circuit sections, can will be apparent that finding out the specific of this partial circuit from this figure
Connection.
The circuit of Fig. 4 .1 mixing units, can will be apparent that finding out the specific connection of this partial circuit from this figure.
Fig. 4 .2 intermediate-frequency filter partial circuits, can will be apparent that finding out the specific connection of this partial circuit from this figure.
Fig. 4 .3 low-noise amplifier partial circuits, can will be apparent that finding out that the specific of this partial circuit connects from this figure
Connect.
Fig. 5 .1 demodulator circuits part, can will be apparent that finding out the specific connection of this partial circuit from this figure.
The cut-away view of Fig. 5 .2 SA639 demodulation chips, can will be apparent that finding out this partial circuit from this figure
Specific connection.
Fig. 6 singlechip chip minimum systems part, can will be apparent that finding out that the specific of this partial circuit connects from this figure
Connect.
The power supply control of the whole circuit diagrams of Fig. 7 and ground circuit part, can will be apparent that finding out this part electricity from this figure
The specific connection on road.
The complete machine module map of Fig. 8 patent 433M digital FM receiver devices of the present invention, can be clearly in slave module figure
Find out the connection of each module.
Fig. 9 header structure figures, we can see that the composition of header.
The header oscillogram of Figure 10 oscilloscope displays, we can see that the content of message is exactly the ASCII of A and B in fact
Code.
The message oscillogram that Figure 11 oscillographs detect, we may safely draw the conclusion, patent 433M receivers of the present invention, warp
Detection of preamble and frame extraction are crossed, the A entrained by carrier wave and the waveform of B, that is, so-called symbol waveform are accurately displayed in oscillograph
On.
Figure 12 the design 433M digital FM receiver complete machine pictorial diagrams.
Figure 13 is that the partial pressure formed using capacitance and single-tunded circuit transmits phase-shift network.
Embodiment
The present invention is described further below in conjunction with the accompanying drawings.
Patent of the present invention provides a kind of 433M digital FM receivers device.It is made of 6 modules, is defeated respectively
Enter to hold low-noise amplifier and 433M filter segments, 433M signals are extracted for amplifying；392.3M local oscillator source signal is electric
Road part, for producing the local oscillation signal of 392.3M；Frequency mixer and intermediate-frequency filter part, for being mixed and extracting down coversion
40.7M signals；Demodulator circuit part, for demodulating the information entrained by carrier wave；Microcontroller micro-process part, locks for controlling
Phase ring and demodulation circuit part；Whole system power supply control and ground part, for whole device system provide different power supplys with
Ground.The 433M digital FM receiver devices that patent of the present invention provides are ingenious in design, rationally distributed, and low in energy consumption, high sensitivity, move
State scope is big, using the modulation /demodulation pattern of 2FSK, can carry out real-time Communication for Power with 433M Digital Frequency Modulation Transmitters well.This
Patent of invention all there is very high scientific research to be worth in 433M digital FM receivers field and ultra short wave communication field, together
When also there is certain engineering application value.
Patent 433M digital FM receivers of the present invention are both comprising the electric circuit diagram design invention on Theoretical Design, software code
Write debugging invention while also have the invention in kind of final molding.The 433M digital FM receiver devices that patent of the present invention provides
It is ingenious in design, rationally distributed, reliability is high, low in energy consumption, high sensitivity, the bit error rate is low, dynamic range is big, integrated level is high, anti-dry
It is strong to disturb ability.Different from the receiver of other structures, this receiver complete machine scheme uses unique frequency redution mode twice, be mixed,
Demodulation effect is more preferable, and signal transmission is more stable, and information distortion rate is small；The simulation used different from other ultrashort wave frequency band receivers
Structure, the information transmission of this receiver is using the digital demodulation pattern of unique 2FSK Binary Frequency Shift Keyings, Digital Transmission
Information, stablizes, is accurate, anti-noise ability and antidamping ability are more preferable.Comprehensive this 2 points innovations so that this receiver apparatus is demodulating
Message context ensure that the phase continuity during change of intersymbol frequency, reduce the out-of-band radiation of radiofrequency signal, information carrying
Amount is more, and transmission rate is fast.Patent of the present invention all has very in 433M digital FM receivers field and ultra short wave communication field
High scientific research value, while also there is certain engineering application value, in television signal transmission, radar target acquisition, shifting
Dynamic station telecommunication etc. can provide technical support well.
Just explain the content of the invention of patent of the present invention and the content of the invention of hardware circuit diagram in detail below.Patent of the present invention
433M modulating modes are that 2FSK receivers one are divided into 6 modules to form the circuitry figure of final 2FSK receivers, they
It is respectively：(1) input terminal low-noise amplifier and 433M filter segments (2) 392.3M local vibration sources signal circuit section (3) are mixed
Frequency device and intermediate-frequency filter part (4) demodulation (secondary frequency reducing) circuit part (5) microcontroller micro-process part (6) whole circuit diagram
Power supply control and ground part.Signal is entered by module 1；Module 2 provides local oscillation signal to module 3：392.3MHz；Signal is from mould
Block 1 completes first time frequency reducing after coming out in module 3, and 40.7M is reduced to by 433M；Then module 4 is entered back into carry out second
Frequency reducing is changed into 10.7M from 40.7M, is then demodulated；5 control module 2 of module and module 4；Module 6 carries for module 2,4,5
For numeral and analog power and earth signal.The direction just advanced below according to signal, point above-mentioned 6 module grounds are explained in detail
The design process and the content of the invention of the circuitry of the design 433M receivers once.
(1) module 1：Input terminal low-noise amplifier and 433M filter segments：
This module uses low noise amplifier MAX2650.Signal is entered by the tuner P1 of module 1, is filtered by 433M sound surface
Go out into 1 pin of the RF2418DS chips of module 3 port 5 of ripple device chip U4.P1 is tuner, and tuner is connected to antenna
Afterwards, the ripple of all frequency ranges including 433M carrier waves is included, entering chip U3 low-noise amplifiers MAX2650 by P1 carries out power
Amplification, exports next stage, what port 4 connected is+5V power supplies, and port 2 is grounded after amplification by port 3.Low noise amplification
The supply voltage of device MAX2650 is+5V, and the capacitance C11 and magnetic bead L4 of the capacitance C10 and polarized 10uf of 0.1uf are to power supply
Be filtered, they form filter circuit, behind can repeatedly use.Blocking capacitance value at the input/output interface of MAX2650
Determined by the following formula：
Wherein, the unit of frequency F is MHz, and the carrier frequency of this receiver is 433MHz, substitutes into formula, MAX2650 inputs
The capacitance of output terminal is 122pF.Its both ends must add the C101 and C102 of 0.1uf, direct current signal is filtered, otherwise
Waveform cannot occur.U4 is 433MHz SAW filters, is entered by 2 pins, and the RF2418DS of module 3 is output to from 5 pins
The pin 1 of chip.Input terminal low-noise amplifier and 433M filter segments this modules are as shown in Figure 2.
(2) module 2:392.3M local vibration source signal circuit sections：
This module uses ADF4360-8 chips U18.Module 2 provides the local oscillation signal source of 392.3M for module 3, module 2
4,5 pins of ADF4360-8 chips are connected to 8 pins of the RF2418DS chips of module 3.MSP430F149 singlechip chip structures
Into minimum system ADF4360-8 chips are controlled, it is accurately produced the local frequency of 392.3M.ADF4360-8
Voltage controlled oscillator output frequency calculation formula inside chip is：
fVCO=[(P × B)+A] × fREFIN/R (4-2)
Wherein fVCOFor voltage controlled oscillator output frequency, P is pre- frequency division coefficient, fREFINFor reference frequency.
Fcco=B × Frefin/R (4-3)
FccoIt is the frequency of phaselocked loop output, F in the designcco=392.3M, B are the binary registers of 13, it takes
Value scope is that 3~8191, Frefin is 16 pin REF of ADF4360-8 chipsinThe frequency for having source crystal oscillator of input, R is 14
Binary register, the design Frefin select 50M, R=500, B=3923 therefore 16 pin REF of ADF4360-8 chipsinInstitute
What is connect is that 50M has source crystal oscillator U12.The CPGND of 1 pin, the AGND of 3 pins, the AGND of 8 pins, the AGND of 11 pins, 12 pins
Cc, the DGND of 15 pins, the AGND of 22 pins with all connecing simulation i.e. GND.+ 3.3V is taken as phaselocked loop ADF4360-8 chips
Supply voltage, 2 pin Avdd, the Vvco of 6 pins, the Dvdd of 21 pins, the CE of 23 pins connect the power supply of+3.3V, each
Power supply all needs to connect the filter circuit as in module 1.Voltage stabilizing the piece AMS1117-3.3, U13 that chip U13 is+3.3V are lock
The voltage of phase ring ADF4360-8 chip offers+3.3.V, 3 pins input, 2 pins output, input is+5V power supplys, output be exactly+
3.3V.9 pin L1, 10 pin L2Resistance R32, a R33 and inductance L29, a L30, wherein resistance R32, R33 are all met respectively
All it is 470 Ω.Inductance value is calculated according to formula below,
In formula, FoIt is 392.3M, Lext is required inductance value, Lext=16.8nH.17 pin CLK, 18 pins
DATA, 19 pin LE are connected on MSP430F149 singlechip chips, they are connected respectively to I/O port 5.3,5.1,5.4, resistance
R22, R24, R2 are 0 Ω, and 20 pin MUXOUT are connected with LED light D3, and 24 pin CP connect a low-pass filter, 16 pins
REFinMeet 50M has source crystal oscillator, is connected with the power supply of source crystal oscillator and need to connect filter circuit, there is source crystal oscillator pin 3 and phaselocked loop
The 50 Ω resistors match circuits that ADF4360-8 chip pins 16 extract are connected directly, it be by 1nF capacitance C73, C75 and
The resistance R26 compositions of 51 Ω.Resistance R27, R28, the tuner P12 of 0 Ω can be external to frequency spectrograph, for testing phaselocked loop
Whether the frequency that ADF4360-8 chips produce is 392.3MHz, and the local frequency that phaselocked loop ADF4360-8 chips produce is managed from 4
Foot RfoutA is output to 8 pin LO IN of frequency mixer, the capacitance C44 of the 4pF of 8 pin of the RF2418DS chips connection in module 3 and
The inductance L18 of 10nH completes the resistors match of phaselocked loop ADF4360-8 chips and 50 Ω being mixed between chip RF2418DS.
392.3M local vibration sources signal circuit section this module is as shown in Figure 3.
(3) module 3:Frequency mixer and intermediate-frequency filter part：
This module RF2418 is reduced to 40.7M, U5 chips are just as once descending frequency reducing chip to complete first time frequency reducing by 433M
It is RF2418 mixer chips.The port 5 of the U4 chips of 1 connection module 1 of pin of RF2418DS chips, the pipe of RF2418DS chips
The RfoutA of 4, the 5 pins connection of the ADF4360-8 chips of 8 connection module 2 of foot, the RF In pins of this module U2 chips MAX2650
1 pin of the U1 chips of link block 4.The inductance L12 of the resistance R8 and 10nH of the 5.11K that the pin 1 of RF2418 chips connects.
3 pin VDD1 connection+5V DC power supplies, 4 pin VDD2 do not have to connect, magnetic bead L13,10uF capacitance C34,47pF capacitance C32,
0.1uF capacitances C35 forms filter circuit, and right+5V DC power supplies are filtered.Signal after being come out by module 1, by pin
1LNA IN enter frequency mixer RF2418 chips, enter 11 pin RF IN by 14 pin LNA OUT, the signal after being mixed is by 6
Pin IF2OUT is input at the intermediate-frequency filter circuit part IN of this module, the sheet for the 392.3MHz that 2 phaselocked loop of module produces
The signal that shakes is input to U5 frequency mixer RF2418DS chips by 8 pins, and the capacitance C44 and 10nH inductance L18 of 4pF completes ADF4360-
The resistors match of 50 Ω between 8 chips and RF2418DS chips, circuit defaults connection, the 0.1uF capacitances of 6 pins at 7 pins
C40 and 1.5K resistance R13 completes the resistors match of 50 Ω between RF2418DS chips and the intermediate-frequency filter of this module.This mould
The intermediate-frequency filter part of block by 33pF capacitance C18,220nH inductance L6,110pF capacitance C19,220nH inductance L7,
The capacitance C20 compositions of 33pF, signal are gone out from INI mouthfuls from IN mouthful entrance, IN mouthfuls connect be mixing chip RF2418DS pin
6IF2OUT, comes out at the IN of 6 pins, there is two paths of signals, and a frequency is 40.7M, the other is 825.3M, this low pass filtered
The effect of ripple device is to filter out the signal that 825.3M signals retain 40.7M.Signal from INI mouthfuls out after put into next low noise
The pin 1 of the SA639 chips of 3 link block 4 of pin of big device U2, U2, the pin 4 of U2 connect+5V power supplys, power supply connection filtering
Circuit, the input pin 1 and output pin 3 of MAX2650 all connect blocking the filter capacitor C103 and C104 of 0.1uf.Frequency mixer
Partial circuit is as shown in attached drawing 4.1, and for intermediate-frequency filter partial circuit as shown in attached drawing 4.2, amplifier circuit in low noise is for example attached
Shown in Fig. 4 .3.
(4) module 4:Demodulate (secondary frequency reducing) circuit part：
This module selects U1 chips SA639 to complete secondary frequency reducing, is changed into 10.7M and demodulation from 40.7M.40.7M intermediate frequency
Signal is entered 1 pin of the U1 chips of module 4 by the RF In pins of the U2 chips of module 3.Inductance L3,3pF's of 760nH
The capacitance C9 of capacitance C6 and 16pF complete the 50 Ω output resistances of MAX2650 low-noise amplifiers of module 3 and the SA639 of this module
Resistors match between 800 Ω input resistances of demodulation chip.The C1 of the C8 and 1nF of 0.1 μ f carry out blocking filter to 40.7M signals
Ripple.What 1,4,24 pins of SA639 demodulation chips were formed is a frequency mixer, and 2 pins are grounded, and 3 pins do not connect, and 4 pins meet 30M
The source crystal oscillator that has carry out U6, and the 40.7M signals of 1 pin input are completed to be mixed together.By filtering inside SA639 demodulation chips
10.7M signals afterwards are exported by 24 pin MIXER OUT, are filtered by the ceramic filter PLT1 of first 10.7M, the
Once filtering is followed by 22 pin IF AMP IN, and signal by coming 20 pin IF AMP again inside SA639 demodulation chips
OUT, is then filtered by the ceramic filter PLT2 of a 10.7M again, and this time filtering is followed by 18 pins
LIMITER.23rd, 21,16,17,19 pins ground connection GND.5 pin VCC connect+5V power supplys.6th, 7,8 pin default connection.By two
The signal of 10.7M after secondary filtering is come out by 15 pins, connects 90 degree of networks of a phase shift, the 10.7M letters before making to enter
Number 90 degree of phase shift, 90 degree of networks of this phase shift are made of the C27 of C28,11pF of R7,15pF of L11,1.3K of 4.7uH, pass through
The 10.7M signals of 90 degree of phase shift enter SA639 demodulation chips by 14 pins.By 18 pins enter without 90 degree of phase shift
The multiplier that 10.7M signals and the 10.7M signals by 90 degree of phase shift entered by 14 pins enter inside SA639 carries out phase
Multiply, by that will produce two components, one high fdrequency component of a low frequency component after multiplier, low frequency component is exactly symbol letter
Number.The connection of 9 pin of chip internal, 10 pin is all an operational amplifier, and the operational amplifier of 9 pins completes emitter following work(
Can, the operational amplifiers of 10 pins just with exterior 5.6K resistance R4,5.6K resistance R5,22pF capacitance C24,33pF capacitances
C26 connects and composes the active low-pass filter of two ranks, and the function of this low-pass filter is exactly to filter the generation of previous multiplications device
That high fdrequency component, only remains the low frequency component of that chip rate.12 pins of SA639 demodulation chips connect+2.5V power supplys,
Right+5V the power supplys of resistance R9, R10 partial pressure that be averaged by being both 22K obtains, and 510 Ω resistance R6,10nF that 13 pins are connect are electric
Hold C25 and also form low-pass filter, the low frequency component of chip rate is filtered again.What is come out by 13 pins is positive low
Frequency component, and by 11 pins come out be negative low frequency component, two paths of differential signals is input to LM311 comparator chips together
U7, what it is from the output of 7 pin of LM311 comparators chip is exactly symbol square wave information.7 pins of LM311 comparator chips are connected to
On the I/O port P5.5 of MSP430f149 chips U11, detection of preamble, frame extraction and oscilloscope display symbol square wave are carried out to information and is believed
Cease waveform.1, the 4 pins ground connection of comparator chip U7,5,6 pins do not connect, 7,8 pin connection+5V power supplys, the connection filter of+5V power supplys
Wave circuit.Attached drawing 5.1 is the circuit diagram being demodulated using SA639 demodulation chips to signal.Attached drawing 5.2 is SA639 solution aligning
The internal structure of piece.
(5) module 5:Microcontroller micro-process part：
Module 5 is used as singlechip microprocessor, control module 2 and module 4.17 pipes of the ADF4360-8 chips of module 2
Foot CLK, 18 pin DATA, 19 pin LE are connected to the I/O port 5.3,5.1,5.4 of this module MSP430F149 singlechip chips, mould
7 pins of the LM311 comparator chips of block 4 are connected to the I/O port P5.5 of this module MSP430f149 chips U11.In this module
In, P8 is emulator chip, and the minimum system of this MSP430F149 singlechip chip does not have to internal crystal oscillator but outside selection
8M crystal oscillators XTCLK3, P5 are spare row's pins, and P10 meets row's pin of 12864 liquid crystal, U10 and J2 composition serial communication systems, U11
It is MSP430F149 singlechip chips, LED liquid crystal D4 connection P1.0 pins, interrupt chip REST1 composition external interrupt circuits.
The supply voltage of MSP430F149 singlechip chips is+3.3V, and U8 is the voltage stabilizing piece chip of+3.3V, LED liquid crystal D2 connections+
3.3V power supply.+ 3.3V voltage stabilizing piece chip U13, the MSP430F149 singlechip chips of phaselocked loop ADF4360-8 chip analogue types
There are three pins with+3.3V voltage stabilizings the piece chip U8, voltage stabilizing piece U8 of numeric type, pin 1 is grounded, pin 3 is to enter termination+5V electricity
Source, pin 2 are output terminals, output+3.3V power supplys.Attached drawing 6 is 5 circuit diagram of module.
(6) module 6：The power supply control of whole circuit diagram and ground part：
Module 6 provides numeral, analog power and earth signal for all active chips in module 2,4,5.Attached drawing 7 is whole
The power supply control of a circuit diagram and ground circuit part, i.e. 6 circuit diagram of module, upper figure circuit by MSP430F149 singlechip chips most
Remaining all simulation ground GND of all digitally DGND and whole circuit that mini system is connected link together；Figure below be for
+ 5V the power circuits of whole circuit power supply, the capacitance C38 of capacitance C36,0.1uF of 10uF carry out the+5V power supplys of whole circuit
Blocking filters, the exterior+5V power supplys of LED liquid crystal D1 connections, and J1 and DC-IN-2 are whole circuit power supply+5V electric outlet structures.
6 modules of the above are exactly the content of the invention of patent of the present invention, also need to complete patent of the present invention before this certainly
Principle designs and experiment simulation, this part can be talked about in embodiment again.It is exactly finally to design patent 433M of the present invention
Modulating mode be the complete machine module map of 2FSK receivers as shown in Figure 8.
Including three parts, Part I is that principle design, emulation experiment and the hardware circuit for completing patent of the present invention connect
Connect.Part II be test patent 433M digital FM receivers of the present invention sensitivity and dynamic range index whether meet will
Ask.If meeting require that for two indices, continue Part III.Part III be combine 433M modulating modes be 2FSK
Transmitter, completes one section of detection of preamble and frame extraction, it is success to demonstrate patent 433M digital FM receivers of the present invention jointly
's.Part III not only plays the role of verification in fact, and it is exactly patent 433M numerals of the present invention that can more say second
FM receiver afterwards practical work when embodiment.Of course, Part III must also expire in Part II
Carried out on the premise of sufficient technical requirement, both are inseparable.
It is Part I embodiment first.
It is the principle design invention section of patent of the present invention first.Including complete machine principle diagram design, utilize ADS radio frequency simulations
Software emulation complete machine conceptual scheme obtains simulation result.Because patent of the present invention is substantially exactly to obtain a 433M modulating mode
It is the FM receiver of 2FSK, then according to several important indexs of FM receiver, it is specified that patent 433M tune of the present invention
Molding formula is the technical indicator that 2FSK receivers need to reach：Receiver frequency range：433MHz±75KHz；Receiver is sensitive
Degree：Less than -55dBm；Dynamic range：More than 40dB.Because the demodulation mode used in patent of the present invention is 2FSK demodulation, Ran Houfen
The theory and phase shift, multiplication frequency discriminator, the method for low-pass filter that not make use of Binary Frequency Shift Keying 2FSK come together to form
The theory of final demodulation 2FSK signals；Followed by it is 2FSK receiver systems to design patent 433M modulating modes of the present invention
Complete machine principle diagram design (as shown in Figure 1).Just explain the modules of the complete machine principle diagram design of Fig. 1 in detail below
Between contact and composition.Illustratively the design of this receiver need to be mixed twice first, because it is bad to be once mixed effect.First
Secondary mixing, frequency are changed into 40.7M from 433M, then the local frequency of first time is 392.3M.Second is mixed, frequency by
40.7M is changed into 10.7M, then local frequency is 30M.According to the technical requirement of the design and 433M receiver principles,
It has chosen following chip.It is that low-noise amplifier selects MAX2650 first；Wave filter selects 433M SAW filters SAW；It is mixed
Frequency device selects RF2418DS；Intermediate-frequency filter after mixing is self-designed low-pass filter, is set with RFSim99 wave filters
Software is counted, why designs low-pass filter, is because its filter effect is better than bandpass filter；It is larger defeated due to meet
Go out power, be equally to select MAX2650 so putting a low-noise amplifier again after intermediate frequency filtering；Demodulator is selected
SA639 chips, in demodulator SA639 chip internal structures, have a frequency mixer, are changed into complete frequency from 40.7M
10.7M；What comparator was selected is LM311 chips；That singlechip chip is selected is MSP430F149；Due to the sheet of first time mixing
Vibration frequency is 392.3M, without the crystal filter of so big frequency, so controlling phaselocked loop core by MSP430F149 microcontrollers
Piece ADF4360-8 produces the frequency of 392.3M；Equally, the square wave of the output of comparator also enters into MSP430F149 microcontrollers
On be processed and displayed.What this receiver received is 2FSK signals, and demodulation mode used is to be added to multiply with hardware phase shift network
Method frequency discriminator demodulates to complete 2FSK, i.e., completes digital demodulation with the hardware circuit of simulation.Next just imitated using ADS radio frequencies
True software emulation complete machine conceptual scheme obtains simulation result.Whether verification simulation result meets required technical indicator, reasonably
Words continue down to carry out.Analyzed by verification, the simulation result of patent of the present invention meets set technical requirement.Then
It is that 2FSK receivers have carried out the general introduction of integrated circuit to patent 433M modulating modes of the present invention, it is then determined that used in each module
The chip arrived, one is divided into 6 modules to form the circuitry figure of final 2FSK receivers, these in the content of the invention
Explained.
The hardware demodulation process for being 2FSK signals, just explaining 2FSK in detail below of the design demodulation.Orthogonal solution
The phase-shift network of device is adjusted to use the circuit form of resonant tank, the partial pressure formed using capacitance and single-tunded circuit transmits phase shift net
Network is as shown in figure 13.
If input voltage isOutput voltage isThen have
OrderQL=R/ (ω0), L ξ=2 (ω-ω0)QL/ω0It is available：
Amplitude versus frequency characte：
Phase-frequency characteristic：
When ω change it is smaller, i.e.,When, tan ξ ≈ ξ.
It is the component parameter that can obtain in resonant tank by above formula.This phase shifter is simple in structure because functional,
It is easily achieved, is often used as phase shift multiplication frequency discriminator together with multiplier.
Then realization of debugging design process and last survey are write for the software code of patent 433M receivers of the present invention
Test result process.Including welding and debugging hardware circuit, write code and measuring technology index three parts.According to set each
Bar technical indicator verifies whether to meet one by one, and two most wanted technical indicator is that sensitivity index and dynamic range refer to respectively
Mark.It is 2FSK transmitters finally exactly to combine 433M modulating modes, and it is that 2FSK is received to coordinate patent 433M modulating modes of the present invention
Machine, completes one section of detection of preamble and frame extraction jointly, and the header detected and message waveform are included on oscillograph,
The further reasonability of verification patent of the present invention.
Followed by Part II embodiment.
It is the sensitivity index for testing patent 433M digital FM receivers of the present invention first：Less than -55dBm.It is specific real
The mode of applying is：It is 433M to add intermediate frequency from signal source, and frequency deviation is 75K, and amplitude is the FM frequency-modulated waves of -55dBm, is observed with oscillograph
Waveform after demodulated, if it is preferable sine wave, should is 75K on its frequency theory, but due to input signal
Amplitude too small-signal can produce distortion, and the amplifier per level-one has noise and these noises can be also exaggerated, finally
The signal for causing to demodulate has a small amount of noise, this does not influence the demodulation result of signal.Selecting range is -65dBm during actual test
FM frequency-modulated waves, if oscillograph can show that preferable symbol waveform i.e. sine wave, illustrate this receiver sensitivity ratio
It is required that technical indicator it is more preferable because the sensitivity requirements of -65dBm than -55dBm is more stringent.Meet the requirements, say by test
Bright receiver sensitivity and receiver frequency range are all met the requirements.
Followed by the dynamic range index of test patent 433M digital FM receivers of the present invention：More than 40dB.It is specific real
The mode of applying is：It is 433M above to have crossed intermediate frequency during measurement sensitivity after tested, and frequency deviation is 75K, and amplitude is the FM frequency modulation of -65dBm
Ripple, it is 433M to change intermediate frequency into now, and frequency deviation is 75K, and amplitude is the FM frequency-modulated waves of -25dBm, if oscillograph remains to display preferably
Symbol waveform, that is, sine wave, just illustrate dynamic range index meet the requirements, met the requirements by test, illustrate this receiver
Dynamic range index is met the requirements.
It is finally Part III embodiment.
On the premise of having required technical indicator all to meet, for patent 433M receivers of the present invention, launched using 433M
Machine, carries out the work of a detection of preamble message extraction, further the function of verification patent 433M receivers of the present invention.It is specific real
The mode of applying is：Launch a frame symbol first with 433M transmitters, then receive this frame code with patent 433M receivers of the present invention
Member, must first detect header certainly, and then frame extracts again, finally show the information (arbitrary two ASCII characters) of transmitting
On oscillograph.Transmitter modulating mode is 2FSK, and the frequency corresponding to high level is 433.3M, the frequency corresponding to low level
For 422.7M.Chip rate is 50K, i.e., launches a symbol every 20us.Header structure is：0-20us is high level, 20us-
40us is that low level, 40us-60us are that high level, 60us-140us are that low level, 140us-160us are high level, 160us-
180us is that low level, 180us-200us are that high level, 200us-320us are low levels.Header structure is as shown in Figure 9.Report
The content of text is the ASCII character of A and B, they are both the binary number representations using 8, A is corresponding be 41 (16
System), 65 (decimal systems), 01000001 (binary system), B corresponding is 42 (hexadecimals), 66 (decimal systems), 01000010
(binary system).When test, the task of 433M transmitters is to launch the 2FSK signals that symbol waveform is A and B to pass through antenna
Send patent 433M receivers of the present invention to, after this 2FSK signal is demodulated, extracted by detection of preamble and frame, by its institute
The waveform of the A and B of carrying, that is, so-called symbol waveform are shown on oscillograph.Attached drawing 10 is the header waveform of oscilloscope display,
Attached drawing 11 is the message waveform that oscillograph detects, after detection of preamble is completed, oscillograph just have read message information, its structure
It is exactly the corresponding binary ASCII characters of A and B into being 01000001,01000010, illustrates the completely errorless reading of oscillograph
Message information is got.In conclusion patent of the present invention completes one section of simple detection of preamble and the function of message extraction, into
One step demonstrates the function of patent 433M receivers of the present invention.Other header and message can be launched in practice, they
All it is arbitrary.
Above three parts are exactly the embodiment of patent 433M digital FM receiver devices of the present invention.Total comes
Say that patent of the present invention completes the design, welding, software code of 433M receivers and writes debugging and the debugging of hardware finished product, make last
Hardware finished product have the function of to receive 433M carrier waves and demodulate entrained 2FSK information.It is with reference to 433M modulating modes
2FSK transmitters, a people enters two arbitrary ASCII characters in 433M frequency modulation transmitter circuits, by the transmission of antenna, this 433M
FM receiver can demodulate this ASCII character and include it on oscillograph, and final testing result also demonstrates this hair
Bright patent 433M digital FM receivers are successful.The FM receiver of high-power with others, big memory is compared, the present invention
The 433M digital FM receiver devices that patent provides are ingenious in design, rationally distributed, and low in energy consumption, high sensitivity, dynamic range are big,
Using the modulation /demodulation pattern of 2FSK, real-time Communication for Power can be carried out with 433M Digital Frequency Modulation Transmitters well.
Claims (1)
1. a kind of 433M digital FM receivers, including：Input terminal low-noise amplifier and 433M filter segments；392.3M this
Signal of vibrating circuit part；Frequency mixer and intermediate-frequency filter part；Demodulate secondary frequency down circuit part；Microcontroller microprocessor portion
Point；The power supply control of whole circuit diagram and ground part, it is characterised in that：Signal is filtered by input terminal low-noise amplifier and 433M
Device part enters；392.3M local vibration sources signal circuit section provides local oscillation signal to frequency mixer and intermediate-frequency filter part；Signal
The is completed in frequency mixer and intermediate-frequency filter part after being come out from input terminal low-noise amplifier and 433M filter segments
Frequency reducing, 40.7M is reduced to by 433M；Demodulation second of frequency reducing of secondary frequency down circuit part progress is entered back into from 40.7M to be changed into
10.7M, is then demodulated；Microcontroller micro-process part controls 392.3M local vibration sources signal circuit section and the secondary drop of demodulation
Frequency circuit part；The power supply of whole circuit diagram controls and ground part is module 392.3M local vibration source signal circuit sections；Demodulation two
Secondary frequency down circuit part；Microcontroller micro-process part provides numeral and analog power and earth signal；
Input terminal low-noise amplifier and 433M filter segments：
Use low noise amplifier MAX2650；Signal is entered by the tuner P1 of module 1, by 433M SAW filter chips U4
Port 5 go out into module 3 RF2418DS chips 1 pin；P1 is tuner, and tuner is connected to after antenna, comprising
The ripple of all frequency ranges including 433M carrier waves, enters chip U3 low-noise amplifiers MAX2650 by P1 and carries out power amplification, amplification
Next stage is exported by port 3 afterwards, what port 4 connected is+5V power supplies, and port 2 is grounded；Low-noise amplifier MAX2650
Supply voltage be+5V, the capacitance C11 and magnetic bead L4 of the capacitance C10 and polarized 10uf of 0.1uf are filtered power supply,
Blocking capacitance value at the input/output interface of MAX2650 is：
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Wherein, the unit of frequency F is MHz, and the carrier frequency of receiver is 433MHz, the capacitance of MAX2650 input/output terminals
For 122pF；Its both ends must add the capacitance C101 and capacitance C102 of 0.1uf, and direct current signal is filtered, and U4 is 433MHz sound
Surface wave filter, is entered by 2 pins, and the pin 1 of the RF2418DS chips of module 3 is output to from 5 pins；
392.3M local vibration source signal circuit sections：
4,5 pins of ADF4360-8 chips are connected to 8 pins of frequency mixer and the RF2418DS chips of intermediate-frequency filter part；
The minimum system that MSP430F149 singlechip chips are formed is controlled ADF4360-8 chips, produces the local oscillator frequency of 392.3M
Rate；Voltage controlled oscillator output frequency inside ADF4360-8 chips is：
fVCO=[(P × B)+A] × fREFIN/R；
Wherein fVCOFor voltage controlled oscillator output frequency, P is pre- frequency division coefficient, fREFINFor reference frequency；
Fcco=B × Frefin/R；
FccoBe phaselocked loop output frequency, Fcco=392.3M, B are the binary registers of 13, its value range is 3~
8191, Frefin be 16 pin REF of ADF4360-8 chipsinThe frequency for having source crystal oscillator of input, R are the binary system deposits of 14
Device, Frefin select 50M, R=500, B=3923；16 pin REF of ADF4360-8 chipsinWhat is connect is that 50M has source crystal oscillator
U12；The CPGND of 1 pin, the AGND of 3 pins, the AGND of 8 pins, the AGND of 11 pins, 12 pin Cc, 15 pins DGND,
The AGND of 22 pins all connect simulation i.e. GND；Take the supply voltages of+3.3V as phaselocked loop ADF4360-8 chips, 2 pins
Avdd, the Vvco of 6 pins, the Dvdd of 21 pins, the CE of 23 pins connect the power supply of+3.3V, each power supply need connection and
The same filter circuit in module 1；Voltage stabilizing the piece AMS1117-3.3, U13 that chip U13 is+3.3V are phaselocked loop ADF4360-8
The voltage of chip offer+3.3.V, the input of 3 pins, the output of 2 pins, input is+5V power supplys, and output is exactly+3.3V；9 pin L1、
10 pin L2Resistance R32, a R33 and inductance L29, a L30 are all met respectively, and wherein resistance R32, R33 is 470 Ω；Electricity
Inductance value：
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In formula, FoIt is 392.3M, Lext is required inductance value, Lext=16.8nH；17 pin CLK, 18 pin DATA,
19 pin LE be connected respectively to IO5.3 mouthfuls of MSP430F149 singlechip chips, IO5.1 mouthfuls, IO5.4 mouthfuls, resistance R22, R24, R2
All it is 0 Ω, 20 pin MUXOUT are connected with LED light D3, and 24 pin CP meet a low-pass filter, 16 pin REFinConnect 50M's
There is source crystal oscillator, filter circuit need to be connected by being connected with the power supply of source crystal oscillator, there is source crystal oscillator pin 3 and phaselocked loop ADF4360-8 chips
The 50 Ω resistors match circuits that pin 16 extracts are connected directly to be made of capacitance C73, C75 of 1nF and the resistance R26 of 51 Ω；0
Resistance R27, R28, the tuner P12 of Ω is external to frequency spectrograph, and the frequency for testing the generation of phaselocked loop ADF4360-8 chips is
No is 392.3MHz, and the local frequency that phaselocked loop ADF4360-8 chips produce is output to 8 pin of frequency mixer from 4 pin RfoutA
LO IN, the inductance L18 of the capacitance C44 and 10nH of the 4pF of 8 pin of the RF2418DS chips connection in module 3 complete phaselocked loop
The resistors match of 50 Ω between ADF4360-8 chips and mixing chip RF2418DS；
Frequency mixer and intermediate-frequency filter part：
U5 chips are RF2418 mixer chips；The pin 1 of RF2418DS chips connects input terminal low-noise amplifier and 433M filters
The port 5 of the U4 chips of ripple device part, the pin 8 of RF2418DS chips connect 392.3M local vibration source signal circuit sections
The RF In pins connection of the RfoutA of 4, the 5 pins connection of ADF4360-8 chips, U2 chips MAX2650 demodulate secondary frequency reducing electricity
1 pin of the U1 chips of road part；The inductance L12 of the resistance R8 and 10nH of the 5.11K that the pin 1 of RF2418 chips connects；3 pipes
Foot VDD1 connection+5V DC power supplies, 4 pin VDD2 do not have to connection, magnetic bead L13,10uF capacitance C34,47pF capacitance C32,0.1uF
Capacitance C35 forms filter circuit, and right+5V DC power supplies are filtered；By input terminal low-noise amplifier and 433M wave filters
Signal after partly coming out, enters frequency mixer RF2418 chips by pin 1LNA IN, enters 11 pipes by 14 pin LNA OUT
Foot RF IN, the signal after being mixed are input to the intermediate-frequency filter circuit part IN of this module by 6 pin IF2OUT,
The local oscillation signal for the 392.3MHz that 392.3M local vibration source signal circuit sections phaselocked loop produces is input to U5 frequency mixers by 8 pins
RF2418DS chips, the capacitance C44 and 10nH inductance L18 of 4pF complete 50 between ADF4360-8 chips and RF2418DS chips
The resistors match of Ω, circuit defaults connection at 7 pins, the 0.1uF capacitance C40 and 1.5K resistance R13 of 6 pins complete RF2418DS
The resistors match of 50 Ω between chip and the intermediate-frequency filter of this module；Intermediate-frequency filter part by 33pF capacitance C18,
The capacitance C20 compositions of inductance L7,33pF of capacitance C19,220nH of inductance L6,110pF of 220nH, signal enter from IN mouthfuls,
Go out from INI mouthfuls, IN mouthfuls that connect is the pin 6IF2OUT for being mixed chip RF2418DS, is come out at the IN of 6 pins, there is two-way
Signal, a frequency is 40.7M, the other is 825.3M, low-pass filter filters out the signal that 825.3M signals retain 40.7M；
Signal from INI mouthfuls out after enter next low-noise amplifier U2, the secondary frequency down circuit part of the connection demodulation of pin 3 of U2
The pin 1 of SA639 chips, the pin 4 of U2 connect+5V power supplys, power supply connection filter circuit, the input pin 1 of MAX2650 and defeated
Go out blocking filter capacitor C103 and C104 that pin 3 all connects 0.1uf；
Demodulate secondary frequency down circuit part：
Select U1 chips SA639 to complete secondary frequency reducing, 10.7M and demodulation are changed into from 40.7M；The intermediate-freuqncy signal of 40.7M is by module 3
The RF In pins of U2 chips enter 1 pin of the U1 chips for demodulating secondary frequency down circuit part；The inductance L3 of 760nH,
The capacitance C9 of the capacitance C6 and 16pF of 3pF complete frequency mixer and 50 Ω of MAX2650 low-noise amplifiers of intermediate-frequency filter part
Resistors match between 800 Ω input resistances of output resistance and SA639 demodulation chips；The C1 of the C8 and 1nF of 0.1 μ f are to 40.7M
Signal carries out blocking filtering；What 1,4,24 pins of SA639 demodulation chips were formed is a frequency mixer, and 2 pins are grounded, 3 pins
Do not connect, what 4 pins met 30M has a source crystal oscillator U6, and the 40.7M signals of 1 pin input are completed to be mixed together；Demodulated by SA639
10.7M signals after chip internal filtering are exported by 24 pin MIXER OUT, by the ceramic filter of first 10.7M
PLT1 is filtered, and filtering for the first time is followed by 22 pin IF AMP IN, and signal inside SA639 demodulation chips by coming again
20 pin IF AMP OUT, are then filtered by the ceramic filter PLT2 of a 10.7M again, and this time filtering is followed by
18 pin LIMITER；23rd, 21,16,17,19 pins ground connection GND；5 pin VCC connect+5V power supplys；6th, 7,8 pin default connection；
The signal of 10.7M after filtering twice is come out by 15 pins, 90 degree of networks of a phase shift is connected, before making to enter
90 degree of 10.7M signal phase shifts, 90 degree of networks of this phase shift are by the C27 groups of C28,11pF of R7,15pF of L11,1.3K of 4.7uH
Into entering SA639 demodulation chips by 14 pins by 90 degree of 10.7M signals of phase shift；By the entrance of 18 pins without phase shift
90 degree of 10.7M signals and the 10.7M signals by 90 degree of phase shift entered by 14 pins enter multiplier inside SA639 into
Row is multiplied, and by that will produce two components after multiplier, one high fdrequency component of a low frequency component, low frequency component is exactly symbol
Signal；The connection of 9 pin of chip internal, 10 pin is all an operational amplifier, and the operational amplifier of 9 pins completes emitter following
Function, the operational amplifiers of 10 pins just with exterior 5.6K resistance R4,5.6K resistance R5,22pF capacitance C24,33pF capacitances
C26 connects and composes the active low-pass filter of two ranks, only retains the low frequency component of chip rate；12 pipes of SA639 demodulation chips
Foot connects+2.5V power supplys, and the right+5V power supplys of resistance R9, R10 partial pressure that is averaged by being both 22K obtains, 13 pins connect 510
Ω resistance R6,10nF capacitances C25 also forms low-pass filter, and the low frequency component of chip rate is filtered again；By 13 pipes
Foot come out be positive low frequency component, and by 11 pins come out be negative low frequency component, two paths of differential signals is input to together
LM311 comparator chip U7, what it is from the output of 7 pin of LM311 comparators chip is exactly symbol square wave information；LM311 comparator cores
7 pins of piece are connected on the I/O port P5.5 of MSP430f149 chips U11, and detection of preamble, frame extraction and oscillography are carried out to information
Device shows symbol square wave information waveform；1, the 4 pins ground connection of comparator chip U7,5,6 pins do not connect, 7,8 pin connection+5V electricity
Source ,+5V power supplys connection filter circuit；
Microcontroller micro-process part：
17 pin CLK, 18 pin DATA, the 19 pin LE of ADF4360-8 chips are connected to microcontroller micro-process part
The I/O port 5.3,5.1,5.4 of MSP430F149 singlechip chips, 7 pins of the LM311 comparator chips of module 4 are connected to
The I/O port P5.5 of MSP430f149 chips U11；P8 is emulator chip, and the minimum system of MSP430F149 singlechip chips is selected
Exterior 8M crystal oscillators XTCLK3, P5 is spare row's pin, and P10 meets row's pin of 12864 liquid crystal, U10 and J2 composition serial communications system
System, U11 are MSP430F149 singlechip chips, and LED liquid crystal D4 connection P1.0 pins, interrupt chip REST1 composition external interrupts
Circuit；The supply voltage of MSP430F149 singlechip chips is+3.3V, and U8 is the voltage stabilizing piece chip of+3.3V, and LED liquid crystal D2 connects
Connect+3.3V power supplys；+ 3.3V voltage stabilizing piece chip U13, the MSP430F149 microcontrollers of phaselocked loop ADF4360-8 chip analogue types
+ 3.3V voltage stabilizings the piece chip U8, voltage stabilizing piece U8 of chip numeric type have three pins, pin 1 is grounded, pin 3 be enter termination+
5V power supplys, pin 2 are output terminals, output+3.3V power supplys；
The power supply control of whole circuit diagram and ground part：
All digitally DGND and whole circuit that MSP430F149 singlechip chip minimum systems are connected remaining own
Simulation ground GND links together；For+5V the power circuits of whole circuit power supply, the capacitance C38 of capacitance C36,0.1uF of 10uF
Blocking filtering is carried out to+5V the power supplys of whole circuit, the exterior+5V power supplys of LED liquid crystal D1 connections, J1 and DC-IN-2 are whole electricity
+ 5V the electric outlet structures of road power supply.
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| CN108205079B (en) * | 2016-12-16 | 2022-06-21 | 北京普源精电科技有限公司 | Method and device for detecting 2FSK signal by using frequency spectrograph |
| CN109714065B (en) * | 2017-10-25 | 2021-06-08 | 南京理工大学 | Satellite-borne AIS and ADS-B integrated receiver based on micro-nano satellite |
| CN110350932B (en) * | 2019-07-03 | 2021-06-18 | 南京大学 | High-frequency broadband receiver and signal processing method |
| CN114629559B (en) * | 2022-03-17 | 2024-02-06 | 西北工业大学 | Simultaneous image interference suppression and self-interference cancellation device based on Sagnac loop and adjustment method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0568939A2 (en) * | 1992-05-06 | 1993-11-10 | Nec Corporation | FSK receiver |
| CN1140935A (en) * | 1995-07-18 | 1997-01-22 | 三菱电机株式会社 | Digital receiver |
| CN102118208A (en) * | 2009-12-31 | 2011-07-06 | 上海博泰悦臻电子设备制造有限公司 | Frequency modulation broadcast receiving terminal and frequency modulation broadcast receiving method |
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2015
- 2015-10-30 CN CN201510726790.6A patent/CN105391497B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0568939A2 (en) * | 1992-05-06 | 1993-11-10 | Nec Corporation | FSK receiver |
| CN1140935A (en) * | 1995-07-18 | 1997-01-22 | 三菱电机株式会社 | Digital receiver |
| CN102118208A (en) * | 2009-12-31 | 2011-07-06 | 上海博泰悦臻电子设备制造有限公司 | Frequency modulation broadcast receiving terminal and frequency modulation broadcast receiving method |
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