CN114244384A - Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver - Google Patents
Continuous wave peak value capturing circuit and method for zero intermediate frequency receiver Download PDFInfo
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Abstract
The invention provides a continuous wave peak value capturing circuit and a method for a zero intermediate frequency receiver, wherein the continuous wave peak value capturing circuit for the zero intermediate frequency receiver comprises an FPGA input end and an FPGA output end which are arranged on an FPGA, and further comprises a control module, an FFT module and a peak value detection module which are arranged on the FPGA, the FPGA input end comprises an FPGA input signal, the FPGA input signal comprises two orthogonal digital baseband signals, the control module outputs a control signal to the FFT module and the peak value detection module, the FFT module outputs a signal to the peak value detection circuit, and the peak value detection circuit is connected with the FPGA output end. The invention can be realized in a digital domain, can be used for a continuous wave peak value capturing circuit of a zero intermediate frequency receiver, can simplify the design of a radio frequency front end, adopts a radio frequency transceiver chip with a single-chip integrated zero intermediate frequency architecture, can complete the whole application design by matching with a small amount of peripheral auxiliary circuits, can reduce the design difficulty, saves the development cost and accelerates the research and development speed.
Description
Technical Field
The invention belongs to the technical field of field programmable gate array development, and particularly relates to a continuous wave peak value capturing circuit for a zero intermediate frequency receiver.
Background
Radio spectrum is an extremely important strategic resource, and it is very necessary to recognize and control the radio spectrum. The continuous wave peak value capturing circuit has important practical significance in the fields of radio frequency spectrum management, radio frequency spectrum interference, anti-interference and the like.
The maximum signal value acquisition in the traditional analog domain usually needs complex hardware circuits, occupies a large volume and has low reliability, and simultaneously, the method also needs large investment of manpower and material resources and has low economic benefit.
At present, a single-chip integrated zero intermediate frequency transceiver is mature, the performance is gradually excellent, and the product is more reliable. Whereas the peak capture circuit for this type of transceiver must be implemented in the digital domain. Therefore, there is a great need in the industry for a continuous wave peak acquisition circuit that can be used in a zero intermediate frequency receiver implemented in the digital domain. And a continuous wave peak acquisition circuit implemented in the digital domain that can be used in a zero intermediate frequency receiver is not disclosed.
Disclosure of Invention
The present invention aims to solve the above problems, and an object of the present invention is to provide a continuous wave peak value capturing circuit and method for a zero intermediate frequency receiver, which can be implemented in a digital domain, can be used for a continuous wave peak value capturing circuit of a zero intermediate frequency receiver, and has the advantages of low design difficulty, low cost, good productivity, and short research and development period.
In order to achieve the purpose, the invention adopts the following technical scheme:
the utility model provides a continuous wave peak value capture circuit for zero intermediate frequency receiver, is including setting up FPGA input and FPGA output on FPGA, still including set up in control module, FFT module and peak detection module on FPGA, the FPGA input includes the FPGA input signal, the FPGA input signal includes two quadrature digital baseband signals, control module output control signal to FFT module and peak detection module, FFT module output signal to peak detection circuit, peak detection circuit connects the FPGA output. The input end of the FPGA comprises two orthogonal digital baseband signals which can be connected with a front-stage radio frequency channel of orthogonal demodulation, so that a single chip integrated transceiver chip of the existing zero intermediate frequency architecture can be matched with a continuous wave peak value capturing circuit for a zero intermediate frequency receiver, and the design of the front-stage radio frequency channel can be simplified; according to the invention, two orthogonal digital baseband signals are processed in the FPGA, so that signal detection can be realized, meanwhile, basic modules such as a control module, an FFT module, a peak detection module and the like are adopted, so that modular design can be realized, and researchers only need to design control logic in an important way, so that the design difficulty is reduced; in addition, the invention has lower cost under the condition of large-scale mass production in the FPGA.
Further, the input end of the FPGA further includes a global clock signal (clk) and a reset signal (rstn) which are input to the control module, the FFT module and the peak detection module, and further includes FPGA input control parameters which are input to the control module.
Furthermore, an FPGA input signal is input into the FFT module and comprises a first orthogonal digital baseband signal (I) and a second orthogonal digital baseband signal (Q), and the FPGA input control parameters comprise a detection period (detp), FFT times (ctpc) in a single period, a detection threshold level (detl) and FFT point numbers (nfft). The invention relates to a first quadrature digital baseband signal (I) and a second quadrature digital baseband signal (Q) suitable for use in a zero intermediate frequency receiver. The input parameters of the invention are used for setting the working state of each module, and the accuracy of peak capture can be improved to a certain extent by adjusting each parameter.
Further, the output end of the FPGA comprises a maximum peak value (mamp), a frequency serial number (midx) corresponding to the maximum peak value and an output end effective indication signal (vld). Each signal at the output end of the FPGA is provided for a user, and the signal strength, the signal frequency and whether the current output is effective or not can be represented respectively.
Furthermore, the control module comprises a control module input end, a detection period timing module for detecting period timing, a detection counting module in a single period for counting the FFT times in the single period, a parameter forwarding control module for parameter forwarding and a control module output end;
the detection cycle timing module is in communication connection with the detection counting module in a single cycle, the detection counting module in the single cycle is in communication connection with the parameter forwarding control module, and the detection cycle timing module is in communication connection with the parameter forwarding control module.
Further, the output terminal of the control module outputs a first control signal (ctrl1) and a second control signal (ctrl2), wherein the first control signal (ctrl1) is connected to and controls the FFT module, and the second control signal (ctrl2) is connected to and controls the peak detection module. The first control signal (ctrl1) and the second control signal (ctrl2) of the present invention can be used to control the start and stop of each module, and implement the period detection.
Further, the FFT module comprises an FFT core used for fast Fourier transform and a RAM module used for sorting the result output by the FFT core according to the frequency in a high-low manner, wherein the FFT core is in communication connection with the RAM module; the FFT module outputs a first signal (Amp) and a second signal (Idx) to a peak detection module.
Furthermore, the peak value detection module comprises a super-threshold interval detection module for detecting an interval exceeding a threshold level in a single FFT, a single interval peak value detection module for detecting a signal peak value in each interval, a full interval peak value detection module for detecting a maximum value of the signal peak value in each interval and a period peak value detection module for detecting the signal peak value in each detection period; the super-threshold interval detection module, the single interval internal peak detection module, the whole interval peak detection module and the periodic peak detection module are sequentially in communication connection.
The invention also provides a continuous wave peak value capturing method for the zero intermediate frequency receiver, which comprises the continuous wave peak value capturing circuit for the zero intermediate frequency receiver, and the method comprises the following specific steps:
s1, power-on reset, initialization configuration of all parameters of a continuous wave peak value capturing circuit of the zero intermediate frequency receiver, and starting of a control module, an FFT module and a peak value detection module;
s2, a single-period detection counting module in the control module starts counting in the detection period, and when the counting in the period reaches a target value, the control module outputs a control signal to control the FFT module and the peak value detection module to stop;
and S3, at the same time, the detection period timing module in the control module starts the detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the counting module in the period to restart, and starts a new round of detection.
Further, when the FFT module is started, FFT check in the FFT module carries out FFT point number fast Fourier transform on the first orthogonal digital baseband signal (I) and the second orthogonal digital baseband signal (Q) and outputs the FFT point number fast Fourier transform, and a RAM module in the FFT module sorts the output result of the FFT check from low to high according to frequency and outputs a first signal (Amp) and a second signal (Idx) to the peak value detection module;
the peak detection module receives the signal output by the FFT and completes the detection of the continuous wave peak value in each detection period, and finally outputs a maximum peak value (mamp), a frequency number (midx) corresponding to the maximum peak value and an output end valid indication signal (vld), specifically: the detection module of the super-threshold interval in the peak detection circuit detects the interval with the amplitude exceeding the detection threshold in single FFT and marks the interval with a signal, the peak detection module of the single interval screens out the maximum value of the amplitude and the corresponding frequency serial number in each interval marked by the detection module of the super-threshold interval by a successive comparison method and records the maximum value, the corresponding frequency serial number and the maximum value in all the marked intervals by the detection module of the whole interval by a successive comparison method and records the maximum value, and the corresponding frequency serial number and the maximum value of the signal in a single detection period by the detection module of the periodic peak are screened out by the detection module of the periodic peak by a successive comparison method and recorded and output.
Compared with the prior art, the invention has the advantages that:
1. the continuous wave peak value capturing circuit for the zero intermediate frequency receiver can be realized in a digital domain, can be used for the continuous wave peak value capturing circuit of the zero intermediate frequency receiver, can simplify the design of a radio frequency front end, adopts a radio frequency transceiver chip of a single-chip integrated zero intermediate frequency framework, can complete the whole application design by matching with a small amount of peripheral auxiliary circuits, can reduce the design difficulty, save the development cost and accelerate the research and development speed;
2. the method can solve the problem of continuous wave signal reconnaissance, can be used in frequency spectrum control equipment, and is convenient for management departments to find the frequency spectrum use problem in time and avoid risks; the method can also be used in interference equipment to realize aiming interference and reduce unnecessary energy loss.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention.
Drawings
Fig. 1 is a schematic structural diagram of a continuous wave peak value capturing circuit for a zero intermediate frequency receiver according to the present invention;
fig. 2 is a flowchart of a continuous wave peak capturing method for a zero intermediate frequency receiver according to the present invention.
In the figure, a global clock signal clk, a reset signal rstn, a quadrature digital baseband signal I, a quadrature digital baseband signal Q, a detection period detp, an FFT number ctpc in a single period, a detection threshold level detl and an FFT point number nfft; a maximum peak value mamp, a frequency serial number midx corresponding to the maximum peak value, and an effective indication signal vld at an output end; a first control signal ctrl1, a second control signal ctrl 2; a first signal Amp, a second signal Idx.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.
Example 1
As shown in fig. 1, the continuous wave peak value capturing circuit for a zero intermediate frequency receiver in this embodiment includes an FPGA input end and an FPGA output end that are disposed on an FPGA, and further includes a control module, an FFT module and a peak value detection module that are disposed on the FPGA, where the FPGA input end includes an FPGA input signal, the FPGA input signal includes two orthogonal digital baseband signals, the control module outputs two control signals to the FFT module and the peak value detection module, respectively, the FFT module outputs a signal to the peak value detection circuit, and the peak value detection circuit is connected to the FPGA output end. The input end of the FPGA of the embodiment comprises two orthogonal digital baseband signals which can be connected with a front-stage radio frequency channel of orthogonal demodulation, so that a single chip integrated transceiver chip of the existing zero intermediate frequency architecture can be matched with a continuous wave peak value capturing circuit for a zero intermediate frequency receiver of the embodiment, and the design of the front-stage radio frequency channel can be simplified; in the embodiment, two orthogonal digital baseband signals are processed in the FPGA, so that signal detection can be realized, meanwhile, basic modules such as a control module, an FFT module, a peak detection module and the like are adopted, so that modular design can be realized, and researchers only need to design control logic in an important way, so that the design difficulty is reduced; in addition, the embodiment is low in cost under the condition of large-scale mass production in the FPGA.
The input end of the FPGA of this embodiment further includes a global clock signal clk and a reset signal rstn which are input to the control module, the FFT module, and the peak detection module, and further includes an FPGA input control parameter which is input to the control module. The input signal of the FPGA of this embodiment is input to the FFT module, and includes a first orthogonal digital baseband signal I and a second orthogonal digital baseband signal Q, and the input control parameter of the FPGA includes a detection period detp, an FFT number ctpc in a single period, a detection threshold level detl, and an FFT point number nfft. The first and second quadrature digital baseband signals I, Q of this embodiment are suitable for use in a zero intermediate frequency receiver. The parameters above the embodiment can be used for setting the working state of each module, and the accuracy of peak capture can be improved to a certain extent by adjusting each parameter.
The output end of the FPGA of this embodiment includes a maximum peak value mamp, a frequency serial number midx corresponding to the maximum peak value, and an output end valid indication signal vld. Here a signal is provided to the user that characterizes the signal strength, the signal frequency and whether the current output is valid, respectively, where a vld high indicates that the output is valid. The control module of the embodiment comprises a control module input end, a detection period timing module for detecting period timing, a single period detection counting module for counting FFT times in a single period, a parameter forwarding control module for parameter forwarding and a control module output end; the detection cycle timing module is in communication connection with the detection counting module in a single cycle, the detection counting module in the single cycle is in communication connection with the parameter forwarding control module, and the detection cycle timing module is in communication connection with the parameter forwarding control module.
The output end of the control module of this embodiment outputs a first control signal ctrl1 and a second control signal ctrl2, where the first control signal ctrl1 is connected to and controls the FFT module, and the second control signal ctrl2 is connected to and controls the peak detection module. In this embodiment, the first control signal ctrl1 and the second control signal ctrl2 are used to control the start and stop of each module, so as to implement cycle detection.
The FFT module comprises an FFT core used for fast Fourier transform and a RAM module used for sequencing the output result of the FFT core according to the frequency, wherein the FFT core is in communication connection with the RAM module; the FFT module outputs a first signal Amp and a second signal Idx to a peak detection module. In this embodiment, the first signal Amp is amplitude, and the second signal Idx is a natural sequence from 0 to nfft-1. The RAM module of this embodiment may adopt a single-port form, and adopt a mode of writing first and then reading, that is, the result generated by the FFT core is stored into the RAM from low to high according to the address, and then the RAM address is mapped from low to high according to the frequency, and the data is read as a whole.
The peak detection module of the embodiment comprises a super-threshold interval detection module for detecting an interval exceeding a threshold level in single FFT, a single interval peak detection module for detecting a signal peak value in each interval, a full interval peak detection module for detecting a maximum value of the signal peak value in each interval and a period peak detection module for detecting the signal peak value in each detection period; the super-threshold interval detection module, the single interval internal peak detection module, the whole interval peak detection module and the periodic peak detection module are sequentially in communication connection.
The design input of the circuit of the embodiment includes a first quadrature digital baseband signal I and a second quadrature digital baseband signal Q, and therefore, the front-end rf channel is necessarily required to be quadrature-demodulated, so that the monolithic transceiver chip of the zero-if architecture is adapted to the circuit of the embodiment, which simplifies the design of the front-end rf channel. In the embodiment, a first orthogonal digital baseband signal I and a second orthogonal digital baseband signal Q are processed in an FPGA (field programmable gate array), so that signal detection is realized, IP cores such as FFT (fast Fourier transform), RAM (random access memory) and the like and basic modules such as a counter are adopted, the modular design is realized, researchers only need to design control logic in a key mode, and the design difficulty is reduced. Moreover, another advantage achieved in the FPGA of the present embodiment is that the productivity is good, and only a suitable FPGA device needs to be burned, so that the cost is low in the case of large-scale mass production. Therefore, the continuous wave peak value capturing circuit can be realized in a digital domain and can be used for a zero intermediate frequency receiver, the radio frequency front end design can be simplified, the monolithic integrated radio frequency transceiver chip with the zero intermediate frequency architecture is adopted, the whole application design can be completed by matching with a small amount of peripheral auxiliary circuits, the design difficulty can be reduced, the development cost can be saved, and the research and development speed can be accelerated.
The continuous wave peak value capturing circuit for the zero intermediate frequency receiver can be used in frequency spectrum control equipment, so that management departments can find frequency spectrum use problems in time and avoid risks; the method can also be used in interference equipment to realize aiming interference and reduce unnecessary energy loss.
Example 2
The present embodiment is different from embodiment 1 in that: the RAM module of the embodiment adopts a dual-port form, and simultaneously performs read-write operation, namely, the RAM address is mapped from low to high according to the frequency, and then each address space of the RAM is subjected to read-after-write operation, so that the running speed of the circuit can be improved.
Example 3
As shown in fig. 2, the present embodiment provides a continuous wave peak value capturing method for a zero intermediate frequency receiver, including a continuous wave peak value capturing circuit for a zero intermediate frequency receiver described in embodiment 1 or embodiment 2, and the specific steps are as follows:
s1, power-on reset, initialization configuration of all parameters of a continuous wave peak value capturing circuit of the zero intermediate frequency receiver, and starting of a control module, an FFT module and a peak value detection module;
s2, a single-period detection counting module in the control module starts counting in the detection period, and when the counting in the period reaches a target value, the control module outputs a control signal to control the FFT module and the peak value detection module to stop;
and S3, at the same time, the detection period timing module in the control module starts the detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the counting module in the period to restart, and starts a new round of detection.
When the FFT module is started, FFT core in the FFT module carries out FFT point fast Fourier transform on a first orthogonal digital baseband signal I and a second orthogonal digital baseband signal Q and outputs the FFT point fast Fourier transform, and an RAM module in the FFT module sorts output results of the FFT core from low to high according to frequency and outputs a first signal Amp and a second signal Idx to a peak value detection module;
the peak value detection module receives the signal output by the FFT and completes the detection of the continuous wave peak value in each detection period, and finally outputs a maximum peak value mamp, a frequency serial number midx corresponding to the maximum peak value and an output end effective indication signal vld, which specifically comprises the following steps: the peak value detection module in the peak value detection circuit detects the interval with the amplitude exceeding the detection threshold in single FFT and marks the interval with a signal, the peak value detection module in the single interval finds out and records the maximum value of the amplitude and the corresponding frequency serial number in each interval marked by the detection module in the super threshold interval by a successive comparison method, the peak value detection module in the whole interval finds out and records the maximum value and the corresponding frequency serial number in all the marked intervals by the successive comparison method, and the peak value detection module in the period finds out and records and outputs the maximum value of the signal and the corresponding frequency serial number in the single detection period by the successive comparison method, so that the peak value of the continuous wave in one detection period is obtained.
The specific embodiments described herein are merely illustrative of the spirit of the invention. Various modifications or additions may be made to the described embodiments or alternatives may be employed by those skilled in the art without departing from the spirit or ambit of the invention as defined in the appended claims.
Claims (10)
1. The continuous wave peak value capturing circuit for the zero intermediate frequency receiver comprises an FPGA input end and an FPGA output end which are arranged on an FPGA, and is characterized by further comprising a control module, an FFT module and a peak value detection module which are arranged on the FPGA, wherein the FPGA input end comprises an FPGA input signal, the FPGA input signal comprises two orthogonal digital baseband signals, the control module outputs a control signal to the FFT module and the peak value detection module, the FFT module outputs a signal to the peak value detection circuit, and the peak value detection circuit is connected with the FPGA output end.
2. The continuous wave peak value capturing circuit for the zero intermediate frequency receiver of claim 1, characterized in that the FPGA input terminal further comprises a global clock signal (clk) and a reset signal (rstn) input to the control module, the FFT module and the peak detection module, and further comprises FPGA input control parameters input to the control module.
3. A continuous wave peak capture circuit for a zero intermediate frequency receiver according to claim 2, characterized in that the FPGA input signal is input to an FFT module comprising a first quadrature digital baseband signal (I) and a second quadrature digital baseband signal (Q), and the FPGA input control parameters comprise a detection period (detp), a number of FFTs within a single period (ctpc), a detection threshold level (detl) and a number of FFT points (nfft).
4. The continuous wave peak capture circuit for a zero intermediate frequency receiver according to claim 1, wherein the output terminal of the FPGA comprises a maximum peak value (mamp), a frequency number (midx) corresponding to the maximum peak value, and an output terminal valid indication signal (vld).
5. The continuous wave peak value capturing circuit for the zero intermediate frequency receiver according to claim 1, wherein the control module comprises a control module input end, a detection period timing module for detecting period timing, a single period detection counting module for counting FFT times in a single period, a parameter forwarding control module for parameter forwarding, and a control module output end;
the detection cycle timing module is in communication connection with the detection counting module in a single cycle, the detection counting module in the single cycle is in communication connection with the parameter forwarding control module, and the detection cycle timing module is in communication connection with the parameter forwarding control module.
6. A continuous wave peak capture circuit for a zero intermediate frequency receiver according to claim 5, characterized in that the control module output outputs a first control signal (ctrl1) and a second control signal (ctrl2), the first control signal (ctrl1) being connected to and controlling the FFT module, the second control signal (ctrl2) being connected to and controlling the peak detection module.
7. The continuous wave peak capture circuit for a zero intermediate frequency receiver according to claim 1, wherein the FFT module comprises an FFT core for fast fourier transform and a RAM module for sorting the output result of the FFT core by frequency; the FFT module outputs a first signal (Amp) and a second signal (Idx) to a peak detection module.
8. The continuous wave peak value capturing circuit for a zero intermediate frequency receiver according to claim 1, wherein the peak value detecting module comprises a super-threshold interval detecting module for detecting intervals exceeding a threshold level within a single FFT, a single interval peak value detecting module for detecting signal peak values within each interval, a full interval peak value detecting module for detecting maximum values of signal peak values within each interval, and a period peak value detecting module for detecting signal peak values within each detection period; the super-threshold interval detection module, the single interval internal peak detection module, the whole interval peak detection module and the periodic peak detection module are sequentially in communication connection.
9. A continuous wave peak value capturing method for a zero intermediate frequency receiver, characterized by comprising a continuous wave peak value capturing circuit for a zero intermediate frequency receiver according to any one of claims 1 to 8, and specifically comprising the steps of:
s1, power-on reset, initialization configuration of all parameters of a continuous wave peak value capturing circuit of the zero intermediate frequency receiver, and starting of a control module, an FFT module and a peak value detection module;
s2, a single-period detection counting module in the control module starts counting in the detection period, and when the counting in the period reaches a target value, the control module outputs a control signal to control the FFT module and the peak value detection module to stop;
and S3, at the same time, the detection period timing module in the control module starts the detection period timing, and when the detection period timing reaches a target value, the control module outputs a control signal to control the FFT module, the peak detection module and the counting module in the period to restart, and starts a new round of detection.
10. The continuous wave peak value capturing method for the zero intermediate frequency receiver according to claim 9, wherein when the FFT module is activated, the FFT module performs FFT point number FFT on the first quadrature digital baseband signal (I) and the second quadrature digital baseband signal (Q) for output, sorts the output result of the FFT kernel from low to high in frequency by the RAM module in the FFT module, and outputs the first signal (Amp) and the second signal (Idx) to the peak detection module;
the peak detection module receives a signal output by the FFT and completes the detection of a continuous wave peak value in each detection period, and finally outputs a maximum peak value (mamp), a frequency serial number (midx) corresponding to the maximum peak value and an output end effective indication signal (vld), specifically: the detection module of the super-threshold interval in the peak detection circuit detects the interval with the amplitude exceeding the detection threshold in single FFT and marks the interval with a signal, the peak detection module of the single interval screens out the maximum value of the amplitude and the corresponding frequency serial number in each interval marked by the detection module of the super-threshold interval by a successive comparison method and records the maximum value, the corresponding frequency serial number and the maximum value in all the marked intervals by the detection module of the whole interval by a successive comparison method and records the maximum value, and the corresponding frequency serial number and the maximum value of the signal in a single detection period by the detection module of the periodic peak are screened out by the detection module of the periodic peak by a successive comparison method and recorded and output.
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