CN103019117B - Digitalizer based on PXI e interface - Google Patents

Digitalizer based on PXI e interface Download PDF

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Publication number
CN103019117B
CN103019117B CN201210519978.XA CN201210519978A CN103019117B CN 103019117 B CN103019117 B CN 103019117B CN 201210519978 A CN201210519978 A CN 201210519978A CN 103019117 B CN103019117 B CN 103019117B
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signal
module
unit
digital
frequency
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CN103019117A (en
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史浩
刘金川
辛丽霞
邵永丰
王凯
王石记
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Beijing Aerospace Measurement and Control Technology Co Ltd
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Beijing Aerospace Measurement and Control Technology Co Ltd
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Abstract

The invention discloses a digitalizer based on PXI e (PCI extensions for Instrumentation express) interface. The digitalizer comprises an analog signal processing and imitating/number A/D conversion circuit unit, a trigger management unit, a timer management unit, an on-board signal processing unit, a capturing engine unit, an on-board memory store management unit, a PXI e interface logic control unit and an analysis unit. By means of the technical scheme of the digitalizer, the digitalizer can provide digital analysis of high sampling rate and high resolution and high analog bandwidth and has a on-board signal processor function which can achieve the functions of DDC (direct digital control), resampling, FIR (finite impulse response) filter sampling and IQ data storing, meantime, the digitalizer supports clock synchronization function, trigger function and a plurality of demodulation modes.

Description

Based on the digitizer of PXI e interface
Technical field
The present invention relates to signal analysis field, particularly relate to a kind of digitizer based on PXI e interface.
Background technology
Along with the development of technology, military test equipment is just towards miniaturization, intelligent development, and require that the function of test is on the increase, volume is little as far as possible.In test equipment, analysis classes instrument occupies very important status, and in order to solve complicated signal analysis, often need to carry out domain Analysis, digitizer is that this demand provides technical guarantee.It is the item of digital signal processing technology be based upon on signal digital basis, for test macro provides various analytic function, comprise the several functions such as oscillograph, VSA, spectrum analyzer, meet the Conjoint Analysis demand of time domain, demodulation territory and frequency domain, from different angles, signal is analyzed, for the function debugging of Complicated Testing System, fault diagnosis provide effective support.But in the prior art, multi-functional, miniaturization is the Focal point and difficult point of this device development.
Summary of the invention
The invention provides a kind of digitizer based on PXI e interface, to solve the aforementioned problems in the prior.
The invention provides a kind of digitizer based on PXI e interface, comprise: analog signal processing and analog/digital A/D conversion circuit unit, for nursing one's health the simulating signal of input, and carry out A/D collection, the digital signal after being gathered by A/D is input to plate and carries signal processing unit; Triggering administrative unit, for carrying out trigger source distribution, and carrying out burst types management; Clock Managing Unit, for generation of the clock signal of each unit of digitizer, and distributes clock signal; Plate carries signal processing unit, processes, the I/Q data stream signal that output signal speed is adjustable for the digital signal after gathering A/D; Capture engine unit, the clock signal for sending according to the trigger pip and Clock Managing Unit that trigger administrative unit transmission is carried memory administrative unit to plate and is sent the steering order storing I/Q data stream signal; Plate carries memory administrative unit, and for the steering order according to capture engine unit, I/Q data stream signal plate being carried signal processing unit output stores; PXI e interface logic control element, for communicating with PXIe bus interface, the control signal that reception control unit is sent by PXIe bus interface, read and write according to the register of control signal to digitizer inside unit, realize the configuration to the unit in digitizer and control; Obtain plate carry the I/Q data stream signal stored in memory administrative unit, by PXIe bus interface by I/Q data stream signal to analytic unit; Analytic unit, for carrying out oscillography, Vector Signal Analysis and spectrum analysis according to I/Q data stream signal.
Preferably, analog signal processing and analog/digital A/D conversion circuit unit specifically comprise: impedance matching module, attenuator, filter and amplification module and A/D acquisition module; Impedance matching module, for carrying out terminal coupling to simulating signal; Attenuator, is made up of the attenuation network of 30dB dynamic range and 0.5dB stepping, decays for the simulating signal exported impedance matching module; Filter and amplification module, comprise: wave filter, switch and amplifier, wherein, wave filter is used for selecting two kinds of filtering modes, and filtering is carried out to the simulating signal that attenuator exports, wherein, two kinds of filtering modes comprise: low pass mode and the logical mode of band, and the simulating signal that low pass mode completes 100Hz ~ 400MHz receives; The simulating signal that the logical mode of band completes 296.4MHz ~ 346.4MHz receives; Switch and amplifier are used for the amplitude of simulating signal to adjust in the range of receiving of A/D acquisition module; A/D acquisition module, for carrying out A/D collection, is converted to digital signal by simulating signal.
Preferably, trigger source comprises: external, programmable functional interface PFI triggers, core bus triggers, signalling channel 0 triggers and plate carries signal processing unit triggering; Burst types comprises: triggering immediately, software trigger and digital triggering.
Preferably, Clock Managing Unit specifically comprises: clock generating module, for by AD9511 chip with reference to clock through phase-locked loop pll frequency multiplication to preset frequency, then through the frequency divider frequency division preset to required frequency; Clock distribution module, distributes to each unit for the clock signal produced by AD9511 chip.
Preferably, PXI e interface logic control element adopts FPGA to realize.
Preferably, plate carries signal processing unit and specifically comprises: equalization filter, digital gain module, digimigration module, direct data control DDC module, data processing mode select module and OSP trigger module; Equalization filter, carries out equalization filtering for the digital signal after A/D gathers; Digital gain module, for carrying out digital gain to the digital signal after equalization filtering; Digimigration module, carries out digimigration for the digital signal after digital gain; DDC module, for processing the digital signal after digimigration, exports I/Q data stream signal; Data processing mode selects module, and for selecting the data processing mode processed I/Q data stream signal, wherein, data processing mode comprises: real data tupe and complex data tupe; Plate carries signal processing unit trigger module, and for sending I/Q data stream signal to triggering administrative unit, wherein, I/Q data stream signal carries the basis for estimation of signal processing unit triggering as plate.
Preferably, DDC module specifically comprises: frequency translation module, for carrying out digital mixing and down coversion to the digital signal after digimigration; Fractional frequency division resampling module, for carrying out fractional frequency division resampling to the digital signal of carrying out after down coversion; Filtering extraction module, for carrying out filtering extraction to the digital signal of input, exports I/Q data stream signal.
Preferably, frequency translation module specifically for: according to the range of scanned frequencies pre-set and sweep frequency stepping, the digital signal after the A/D of input gathers is scanned, the digital oscillator signal that digital signal is orthogonal with two-way is respectively multiplied, and completes digital mixing and down coversion; Filtering extraction module specifically for: by cascaded integrator-comb cic filter, half band HB wave filter and have limit for length's unit impulse response FIR filter to input digital signal carry out high fdrequency component elimination, obtain in-phase component I and quadrature component Q, and obtain I/Q data stream signal according to in-phase component I and quadrature component Q, wherein, I/Q data stream signal comprises: I signal parameter, Q signal parameter, M signal parameter, P signal parameter and F signal parameter.
Preferably, control module specifically comprises: vector analysis module, synchronous with code for carrying out carrier synchronization to I/Q data stream signal, and Amplitude Compensation and phase compensation are carried out to I/Q data stream signal, after carrying out filtering by measurement wave filter, I/Q data stream signal is divided into two-way, symbol detection of leading up to forms reference signal, another road is measuring-signal, and Reference Signal and measuring-signal compare, and carries out error calculation; Spectrum analysis module, for being obtained the analysis bandwidth RBW of raw spectroscopy data by cic filter, HB wave filter and the FIR filter in filtering extraction module, and the display bandwidth VBW of raw spectroscopy data is obtained by amplitude discrimination and FIR filtering, detection is carried out to raw spectroscopy data, obtain frequency spectrum data, carry out spectrum analysis according to frequency spectrum data; And the range of scanned frequencies of controlled frequency modular converter and sweep frequency stepping, wherein, FIR filter coefficient is constant, is realized the conversion of different bandwidth by the extracting multiple controlling cic filter and HB wave filter.
Preferably, sweep frequency stepping is less than or equal to 1/3RBW.
Beneficial effect of the present invention is as follows:
The technical scheme of the embodiment of the present invention can provide high sampling rate, high-resolution numerical analysis, analog bandwidth is high, and there is plate and carry signal processor function, the functions such as DDC, resampling, FIR filtering extraction, I/Q data storage can be realized, support clock synchronous, Trigger Function simultaneously, support multiple demodulation mode, the field such as EW receiver, radar receiver, electronic reconnaissance in the various communication system such as radio communication, radio-frequency (RF) broadcast, satellite communication and military field can be widely used in.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of instructions, and can become apparent, below especially exemplified by the specific embodiment of the present invention to allow above and other objects of the present invention, feature and advantage.
Accompanying drawing explanation
By reading hereafter detailed description of the preferred embodiment, various other advantage and benefit will become cheer and bright for those of ordinary skill in the art.Accompanying drawing only for illustrating the object of preferred implementation, and does not think limitation of the present invention.And in whole accompanying drawing, represent identical parts by identical reference symbol.In the accompanying drawings:
Fig. 1 is the structural representation of the digitizer based on PXI e interface of the embodiment of the present invention;
Fig. 2 is the analog signal processing of the embodiment of the present invention and the structural representation of A/D conversion circuit unit;
Fig. 3 is the structural representation that the plate of the embodiment of the present invention carries signal processing unit;
Fig. 4 is the digitizer control module overall workflow figure of the embodiment of the present invention;
Fig. 5 is that the oscillograph of the embodiment of the present invention drives interface function schematic diagram;
Fig. 6 is the illustrative view of functional configuration of the driving of the embodiment of the present invention;
Fig. 7 is the schematic diagram of the digital quadrature extraction platform structure of the embodiment of the present invention;
Fig. 8 is the structural representation of the Vector Signal Analysis algorithm of the embodiment of the present invention;
Fig. 9 is the schematic diagram of the spectrum analysis process based on FIR of the embodiment of the present invention;
Figure 10 be the embodiment of the present invention take RBW as the schematic diagram that step-scan causes amplitude measurement error.
Embodiment
Below with reference to accompanying drawings exemplary embodiment of the present disclosure is described in more detail.Although show exemplary embodiment of the present disclosure in accompanying drawing, however should be appreciated that can realize the disclosure in a variety of manners and not should limit by the embodiment set forth here.On the contrary, provide these embodiments to be in order to more thoroughly the disclosure can be understood, and complete for the scope of the present disclosure can be conveyed to those skilled in the art.
In order to solve the problem, the invention provides a kind of digitizer based on PXI e interface, can complete the analytic function of three territories (time domain, frequency domain, modulation domain), the digitizer of the embodiment of the present invention comprises analog signal processing and A/D conversion circuit unit, triggers administrative unit, Clock Managing Unit, plate carry signal transacting OSP unit, plate carries memory administrative unit and capture engine unit and PXI e interface logic control element; And it is interconnected to adopt IVI standard interface to realize instrument, functional interface function is driven to follow IVI-4.1_Scope oscillograph specification, mutually compatible with NI digitizer product; The digitizer of the embodiment of the present invention can carry out spectrum analysis and vector analysis, followingly will provide the framed structure of spectrum analysis and vector analysis respectively.It should be noted that, the embodiment of the present invention can also have oscillograph function, and because oscillograph function is relatively simple, the embodiment of the present invention does not carry out too much elaboration.
Example of the present invention uses the original analog demodulation mode type of the universal demodulation framework substitution of general-purpose digital signal process, enormously simplify the physical dimension of signal analyzer, realize the wide band oscilloscope tube under PXIe compact volume, Vector Signal Analysis and spectrum analysis function, for the miniaturization of test equipment provides technical support, simultaneously for the Conjoint Analysis of the synthesization of Military Automatic Test System future development time domain, demodulation territory and frequency domain provides technical guarantee.
Below in conjunction with accompanying drawing and embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, do not limit the present invention.
According to embodiments of the invention, provide a kind of digitizer based on PXI e interface, Fig. 1 is the structural representation of the digitizer based on PXI e interface of the embodiment of the present invention, as shown in Figure 1, the digitizer based on PXI e interface according to the embodiment of the present invention comprises: analog signal processing and analog/digital A/D conversion circuit unit 10, trigger administrative unit 11, Clock Managing Unit 12, plate carries signal processing unit 13, capture engine unit 14, plate carries memory administrative unit 15, PXI e interface logic control element 16, and analytic unit 17, below the modules of the embodiment of the present invention is described in detail.
Analog signal processing and analog/digital A/D conversion circuit unit 10, for nursing one's health the simulating signal of input, and carry out A/D collection, and the digital signal after being gathered by A/D is input to plate and carries signal processing unit 13;
Analog signal processing and analog/digital A/D conversion circuit unit 10 specifically comprise: impedance matching module, attenuator, filter and amplification module and A/D acquisition module;
Impedance matching module, for carrying out terminal coupling to simulating signal;
Attenuator, is made up of the attenuation network of 30dB dynamic range and 0.5dB stepping, decays for the simulating signal exported impedance matching module;
Filter and amplification module, comprise: wave filter, switch and amplifier, wherein, wave filter is used for selecting two kinds of filtering modes, and filtering is carried out to the simulating signal that attenuator exports, wherein, two kinds of filtering modes comprise: low pass mode and the logical mode of band, and the simulating signal that low pass mode completes 100Hz ~ 400MHz receives; The simulating signal that the logical mode of band completes 296.4MHz ~ 346.4MHz receives; Switch and amplifier are used for the amplitude of simulating signal to adjust in the range of receiving of A/D acquisition module;
A/D acquisition module, for carrying out A/D collection, is converted to digital signal by simulating signal.
Triggering administrative unit 11, for carrying out trigger source distribution, and carrying out burst types management; Wherein, trigger source comprises: external, programmable functional interface PFI triggers, core bus triggers, signalling channel 0 triggers and plate carries signal processing unit 13 and triggers; Burst types comprises: triggering immediately, software trigger and digital triggering.
Clock Managing Unit 12, for generation of the clock signal of each unit of digitizer, and distributes clock signal;
Clock Managing Unit 12 specifically comprises:
Clock generating module, for by AD9511 chip with reference to clock through phase-locked loop pll frequency multiplication to preset frequency, then through the frequency divider frequency division preset to required frequency;
Clock distribution module, distributes to each unit for the clock signal produced by AD9511 chip.
Plate carries signal processing unit 13, processes, the I/Q data stream signal that output signal speed is adjustable for the digital signal after gathering A/D;
Plate carries signal processing unit 13 and specifically comprises: equalization filter, digital gain module, digimigration module, direct data control DDC module, data processing mode select module and OSP trigger module;
Equalization filter, carries out equalization filtering for the digital signal after A/D gathers;
Digital gain module, for carrying out digital gain to the digital signal after equalization filtering;
Digimigration module, carries out digimigration for the digital signal after digital gain;
DDC module, for processing the digital signal after digimigration, exports I/Q data stream signal; Wherein, DDC module specifically comprises: frequency translation module, for carrying out digital mixing and down coversion to the digital signal after digimigration; Particularly, frequency translation module scans the digital signal after the A/D collection of input according to the range of scanned frequencies pre-set and sweep frequency stepping, the digital oscillator signal that digital signal is orthogonal with two-way is respectively multiplied, and completes digital mixing and down coversion;
Fractional frequency division resampling module, for carrying out fractional frequency division resampling to the digital signal of carrying out after down coversion;
Filtering extraction module, for carrying out filtering extraction to the digital signal of input, exports I/Q data stream signal.Data processing mode selects module, and for selecting the data processing mode processed I/Q data stream signal, wherein, data processing mode comprises: real data tupe and complex data tupe;
Particularly, filtering extraction module specifically for: by cascaded integrator-comb cic filter, half band HB wave filter and have limit for length's unit impulse response FIR filter to input digital signal carry out high fdrequency component elimination, obtain in-phase component I and quadrature component Q, and obtain I/Q data stream signal according to in-phase component I and quadrature component Q, wherein, I/Q data stream signal comprises: I signal parameter, Q signal parameter, M signal parameter, P signal parameter and F signal parameter.
Plate carries signal processing unit 13 trigger module, and for sending I/Q data stream signal to triggering administrative unit 11, wherein, I/Q data stream signal carries the basis for estimation of signal processing unit 13 triggering as plate.
Capture engine unit 14, the clock signal for sending according to the trigger pip and Clock Managing Unit 12 that trigger administrative unit 11 transmission is carried memory administrative unit 15 to plate and is sent the steering order storing I/Q data stream signal;
Plate carries memory administrative unit 15, for the steering order according to capture engine unit 14, plate is carried the I/Q data stream signal that signal processing unit 13 exports and stores;
PXI e interface logic control element 16, for communicating with PXIe bus interface, the control signal that reception control unit is sent by PXIe bus interface, read and write according to the register of control signal to digitizer inside unit, realize the configuration to the unit in digitizer and control; Obtain plate carry in memory administrative unit 15 store I/Q data stream signal, by PXIe bus interface by I/Q data stream signal to analytic unit 17; Preferably, PXI e interface logic control element 16 adopts FPGA to realize.
Analytic unit 17, for carrying out oscillography, Vector Signal Analysis and spectrum analysis according to I/Q data stream signal.
Analytic unit 17 specifically comprises:
Vector analysis module, synchronous with code for carrying out carrier synchronization to I/Q data stream signal, and Amplitude Compensation and phase compensation are carried out to I/Q data stream signal, after carrying out filtering by measurement wave filter, I/Q data stream signal is divided into two-way, and symbol detection of leading up to forms reference signal, and another road is measuring-signal, Reference Signal and measuring-signal compare, and carry out error calculation;
Spectrum analysis module, for being obtained the analysis bandwidth RBW of raw spectroscopy data by cic filter, HB wave filter and the FIR filter in filtering extraction module, and the display bandwidth VBW of raw spectroscopy data is obtained by amplitude discrimination and FIR filtering, detection is carried out to raw spectroscopy data, obtain frequency spectrum data, carry out spectrum analysis according to frequency spectrum data; And the range of scanned frequencies of controlled frequency modular converter and sweep frequency stepping, wherein, FIR filter coefficient is constant, is realized the conversion of different bandwidth by the extracting multiple controlling cic filter and HB wave filter.Sweep frequency stepping is less than or equal to 1/3RBW.
Below in conjunction with accompanying drawing, the technique scheme of the embodiment of the present invention is described in detail.
The embodiment of the invention discloses a kind of Multifunction digitalization Instrument based on PXI e interface, adopt digital signal processing mode, 250MS/S high sampling rate, 16bit high-resolution signal analytic function can be provided, hardware forms primarily of analog signal processing and A/D change-over circuit and FPGA signal transacting IP, and it is interconnected to adopt IVI standard interface to realize instrument.
The structure of the digitizer of the embodiment of the present invention as shown in Figure 1, mainly comprises analog signal processing and A/D conversion circuit unit, triggers administrative unit, seven hardware cells such as Clock Managing Unit, plate carry signal transacting OSP unit, plate carries memory administrative unit, capture engine unit, PXI e interface logic control element and analytic unit form.Below respectively above-mentioned unit is described in detail.
1, analog signal processing and A/D conversion circuit unit
Analog signal processing and A/D conversion circuit unit complete and input analog signal conditioner and A/D acquisition function, Fig. 2 is the analog signal processing of the embodiment of the present invention and the structural representation of A/D conversion circuit unit, as shown in Figure 2, comprise five parts such as impedance matching, attenuator, filter and amplification network and A/D gather to form.
Wherein, the terminal coupling work of impedance matching network settling signal, avoids the reflection of signal, ringing, strengthens the stability of system.
Attenuator is made up of the attenuation network of 30dB dynamic range, 0.5dB stepping, the dynamic range of expanding system, makes module have the ability measuring large-signal.
Filter and amplification network is made up of wave filter, switch, amplifier etc., and filter and amplification network is divided into two kinds of filtering modes to select, the logical mode of low pass mode, band.Low pass mode completes the Signal reception of 100Hz ~ 400MHz, for the signal processing and analysis of device self; The logical mode of band completes the Signal reception of 296.4MHz ~ 346.4MHz, is mainly used in this device and connects with down-conversion device, and as the occasion of synthetic instrument, the logical mode of band can promote the signal to noise ratio (S/N ratio) of synthetic instrument, promotes the analysis ability of weak signal; Switch, amplifier adjust to the receivable more satisfactory scope of A/D the amplitude of signal, are convenient to A/D and receive.
It is very important link in device that A/D gathers, the effect that A/D gathers directly affects follow-up signal analysis result, A/D collection is the AD9467 chip of A/D chip selection height SFDR in device for this reason, sampling rate is up to 250MSPS, 16bit resolution, SFDR is 90dBFs when 300MHz, and interface is the LVDS of difference.The purity of frequency spectrum and the power supply of A/D collection are in close relations, especially the clutter interference of carrier wave near-end, therefore this device is powered should meet current requirements to A/D, reduces ripple as much as possible again simultaneously, and device adopts two panels LM1085 series voltage stabilizing sheet to provide+3.3V and+1.8V voltage respectively.
2, administrative unit is triggered
Trigger administrative unit and mainly comprise trigger source distribution, burst types management.Wherein, trigger source is triggered by outside PFI1, core bus, signalling channel 0 triggers and OSP triggers; Burst types comprises triggering immediately, software triggers, digital triggering.
3, Clock Managing Unit
Clock Managing Unit is responsible for generation and the distribution of system components clock, the generation of clock mainly by AD9511 chip 100MHz reference clock through PLL frequency multiplication to 1GHz, then through the frequency divider frequency division preset to required frequency; The distribution of clock mainly distributes to each element circuit, as trigger element, analogy signal processing unit etc. the clock signal that AD9511 produces.
4, plate carries signal processing unit (OSP)
Plate carry signal processing unit OSP be responsible for A/D gather after digital signal processing, Fig. 3 is the structural representation that the plate of the embodiment of the present invention carries signal processing unit, as shown in Figure 3, several aspects such as quadrature down-conversion architecture, NCO digital controlled oscillator, wave filter, drawing-out structure, signal gain and biased adjustment are comprised.It comprises real number and plural number two kinds of data processing modes, after A/D is gathered, the signal of upper frequency downconverts to lower frequency, support the extraction factor (support fractional mode) of 1-16384 simultaneously, the I/Q signal that output signal speed is adjustable, especially the synthetic instrument of down-conversion device combination is coordinated, intermediate frequency 321.4MHz can downconvert to very low frequency by OSP, so as with follow-up signal analysis, the multiple demand of user can be met.
5, plate carries memory administrative unit and capture engine unit
Plate carries memory administrative unit and coordinates capture engine unit, under the various triggering memory modules of user's setting, OSP is exported I/Q data stream signal store, support many records and continuous acquisition function, for oscillograph and spectrum analysis provide effective data stream, this device provides 2Gb Large Copacity DDR2 memory function simultaneously, makes user can carry out finer and smoother analysis to signal.
6, PXI e interface logic control element
PXIe bus interface is responsible for communicating with PXI e slot controller, each register of device inside is read and write, final realization is to the control of the hardware such as AD9467, usually Special Interface Chip can be adopted to complete, its advantage uses simply, protocol comparison is perfect, shortcoming be cost compared with high, volume is large.Consider that this device communication mode is fairly simple, for cost-saving, reduce volume, this device adopts FPGA to complete interface protocol conversion, interface routine mainly adopts ALTERA to carry the IP kernel of PCIe, the upper IP kernel coordinating Ext_Access etc. to be packaged into common CP U read-write mode in this basis.
7, control module (this control module can be arranged in host computer)
In embodiments of the present invention, control module comprises: application layer, IVI driver layer, device bsp driver layer, operating system and bus interface driver.Wherein, application layer, by calling driver, by VISA storehouse PXIe bus interface, realizes the configuration to instrument and control.
Fig. 4 is the digitizer control module overall workflow figure of the embodiment of the present invention, as shown in Figure 4, after the digitizer of the embodiment of the present invention powers on and starts shooting, start self-test operations, self-test operations completes the verification operation to digitizer, tests to parts important in system, if working properly, then start to enter next step operating process, otherwise send alerting signal, representative digit instrument is abnormal.During normal running flow process, the order of user waited for by digitizer, after receiving orders, completed the transformation of various sequential by FPGA, finally produces corresponding signal.
In embodiments of the present invention, the IVI interfaces such as host computer mainly provides hardware parameter to configure, the output of measured waveform result, are synthesized instrument and call.For driving compatibility with NI company digitizer, employing oscillograph drives, interface function follows IVI-4.1_Scope oscillograph specification, Fig. 5 is that the oscillograph of the embodiment of the present invention drives interface function schematic diagram, Fig. 6 is the illustrative view of functional configuration of the driving of the embodiment of the present invention, as shown in Figure 5,6, it is all calling bottom optimum configurations that all input parameters are arranged, and then calling device instrument driving.Bottom parameter setting apparatus requires there is corresponding handling function to each parameter, must carry out checksum protection to parameter area.What raw data obtained is the original waveform array of not amounting to.By Measurement Algorithm, obtain waveform parameter measurement result.
8, analytic unit (in embodiments of the present invention, analytic unit can be arranged in host computer)
(1) wideband vector signal analytical framework
Digital quadrature extracts platform
In embodiments of the present invention, algorithm realization makes full use of the thought of the Software Defined Instrument of software radio, after high-speed a/d collection, flow chart of data processing all adopts digital signal processing algorithm, Fig. 7 is the schematic diagram of the digital quadrature extraction platform structure of the embodiment of the present invention, as shown in Figure 7, AD converter figure place 16, sampling rate reaches as high as 250MHz, and the digital signal that after adopting, A/D exports reaches the object reducing signal frequency and sampling rate through digital mixing, low pass and extraction.First digital signal after AD conversion enters digital quadrature and extracts down coversion structure, input signal respectively with two-way orthogonal digital oscillator (NCO) signal multiplication, complete digital mixing, eliminate high fdrequency component by wave filters such as CIC, HB, FIR subsequently, the middle drawing-out structure that adopts reaches the object reducing signal sampling speed.The in-phase component I exported and quadrature component Q, enters feature extraction unit and isolates the signal parameters such as I, Q, M, P, F, for Vector Signal Analysis provides necessary data source.Wherein, the numerical control NCO shown in Fig. 7 corresponds to the frequency translation module in the DDC in Fig. 2, and cic filter, HB wave filter, FIR filter and feature extraction correspond to the filtering extraction module in Fig. 2 in DDC.
Digital demodulation Gneral analysis platform
Because Vector Modulation type is more, therefore adopt the core that commonality vector demodulation techniques are analyzed as wideband vector signal, to improve the demodulation function of digitizer to various Vector Modulation.Fig. 8 is the structural representation of the Vector Signal Analysis algorithm of the embodiment of the present invention, as shown in Figure 8, mainly comprises measuring-signal demodulating unit, reference signal forming unit and error analysis unit.It realizes universal signal demodulation function, only needs under the model to be configured universal demodulation device, can support a large amount of signal madulation patterns.
It is synchronous with code that first the I/Q data stream of quadrature decimation structure output carry out carrier synchronization, carrier synchronization adopts carrier wave frequency deviation to calculate algorithm, revise the deviation distortion in signal data stream, this algorithm can reach very high precision, is also the basis that hardware adopts asynchronous digital local oscillator.Subsequent data flows to into Amplitude Compensation and phase compensation, and the phase distortion (group delay distortion) that main compensation analog channel produces and amplitude distortion, promotion signal analyzes quality.Measuring wave filter actual is exactly ISI matched filter, according to the difference of signal, comprises square root raised cosine filter, wave filter etc. is measured in IS-95 up-downgoing.Signal stream after matched filter is divided into two-way, code stream of leading up to detects and obtains bit information flow, form new desired reference baseband signal, the reference matched filter of rear end changes with the modulation character of signal, and general has raised cosine filter, IS-95 up-downgoing reference filter, Gaussian filter etc.; Another road is used for comparing with reference signal, carries out error calculation, obtains EVM(Error Vector Magnitude), the information such as range error, phase error.
(2) spectrum analysis framework
Spectrum analysis process based on FIR:
Fig. 9 is the schematic diagram of the spectrum analysis process based on FIR of the embodiment of the present invention, and as shown in Figure 9, based in the spectrum analysis of FIR, intermediate-frequency filter generally only has 1 ~ 3 bandwidth to select, and corresponding filter bandwidht is called " real-time bandwidth " of frequency spectrograph.AD gathers and is converted into digital signal, I, Q two paths of signals is decomposed into through quadrature downconvert, I, Q signal extract through CIC, half band, filtering mixing with frequently (high frequency) signal, enter FIR filter, FIR filter corresponds to RBW wave filter, FIR filter coefficient is constant, under extracting in different CIC, half band, the data transfer rate entering FIR filter is different, thus the analog bandwidth causing FIR filter corresponding is different thus realize different RBW bandwidth.Amplitude discriminator corresponds to envelope detector, for measuring the signal amplitude (energy) after RBW filtering.VBW plays spectral smoothing effect, and realize with " CIC+ half band+FIR " in reality, to realize principle similar with RBW, and FIR coefficient is constant, realizes different VBW bandwidth by controls CIC, half band extraction.
In FIR mode, often change single pass frequency (NCO frequency), store the frequency spectrum data of a frequency, along with the change of scanning frequency, the frequency spectrum data (raw spectroscopy data) on whole frequency can be obtained, the number of scan points detection that raw spectroscopy data is specified according to user, can obtain final frequency spectrum.
Spectrum scan process based on FIR compares easy understand, do not repeat them here, elaborate the relations problems about the stepping of RBW bandwidth sum frequency sweep, directly with RBW bandwidth for signal amplitude measuring error when stepping scans is bigger than normal, and RBW filter shape (in RBW metering, requiring to scan out filter shape) cannot be scanned out.In fact, direct corresponding relation is not had between frequency sweep stepping and RBW bandwidth, at every turn frequency sweep stepping puts frequently, the frequency that local oscillation signal changes, and RBW bandwidth is the bandwidth of adopted intermediate-frequency filter, this point is easy to find out from the ramp generator of analog spectrum instrument, if take RBW bandwidth to be that stepping is carried out spectrum scan and will be produced serious amplitude measurement error, Figure 10 be the embodiment of the present invention take RBW as the schematic diagram that step-scan causes amplitude measurement error, as shown in Figure 10, suppose that input signal is positioned at fin position, before once put frequently filter centre frequency and be positioned at f1, again put filter centre frequency frequently and be positioned at f1+RBW, if there is f1<fin<f1+RBW, the measuring amplitude then putting signal frequently for twice is respectively the decay of two wave filters in fin position and the product of input signal size.Because RBW bandwidth is three dB bandwidth, if with RBW bandwidth for scanning stepping, under worst case, fin just=f1+RBW/2 time, the signal amplitude that twice measurement obtains is identical, but all little than actual signal amplitude 3dB.Cause very large amplitude measurement error thus.
Be not difficult to find out from explanation above, if carry out frequency sweep with the stepping being less than RBW, then just have more than one sampled point in a RBW bandwidth, amplitude measurement error will significantly reduce, if frequency sweep stepping is enough little, just can scan the shape of wave filter.General frequency sweep stepping is less than 1/3RBW, can meet engineering demand.
The broadband RBW splicing of frequency spectrograph
For obtaining good signal to noise ratio (S/N ratio), the wave filter that usual sampling is narrower, analyze favourable for little RBW like this, embodiment of the present invention intermediate-frequency filter is 1.5MHz bandwidth, therefore the realization of the RBW wave filter of 3MHz needs to splice, the result of the RBW of 1MHz is namely adopted to carry out 3 splicings.
Figure 10 is the schematic diagram of the RBW splicing of the 3MHz of the embodiment of the present invention, and as shown in Figure 10, if the frequency of input signal is F1, then first time analysis and left avertence move the curve of 1MHz, and it and frequency F1 intersection power are very little, can think to be 0; It is the curve of 0 that second time analyzes i.e. skew, and it is 1/2 of peak value that it and frequency F1 intersection power ratio high are worth little 3dB(power); Third time analysis and right avertence move the curve into 1MHz, it is 1/2 of peak value that it and frequency F1 intersection power ratio high are worth little 3dB(power), such three power synthesize 0+1/2+1/2=1 and peak power, the process calculated when input signal is in other position is similar.
Here the very important point is that the filter curve corresponding to RBW of 1MHz must be accurate, and namely three dB bandwidth is 1MHz, otherwise the rbw filter curve of the 3MHz of synthesis has comparatively big error.
Optional frequency operating process is as follows:
When the signal frequency that the RBW of 3MHz will analyze is fin, splice according to the following procedure:
Step 1, arranging RBW is 1MHz, and the power of the signal fin of acquisition is P_db1, and the power of signal fin-1MHz is P_db0, and the power of signal fin+1MHz is P_db2;
Step 2, the RBW equivalent power of 3MHz: Pow _ eq = 10 P _ db 0 10 + 10 P - db 1 10 + 10 P _ db 2 10 ;
Step 3, being converted into dB value is: Pow_eqdB=10*log10 (Pow_eq).
In sum, the digitizer of the embodiment of the present invention can provide the high sampling rate of 250MS/S16bit, Analytical high resolution, analog bandwidth is up to 400MHz, there is plate and carry signal processor function, DDC can be realized, resampling, FIR filtering extraction, the functions such as I/Q data storage, support clock synchronous simultaneously, Trigger Function, BPSK is provided, QAM, MSK, AM, the multiple demodulation mode such as FM, radio communication can be widely used in, radio-frequency (RF) broadcast, EW receiver in the various communication system such as satellite communication and military field, radar receiver, the fields such as electronic reconnaissance.
Intrinsic not relevant to any certain computer, virtual system or miscellaneous equipment with display at this algorithm provided.Various general-purpose system also can with use based on together with this teaching.According to description above, the structure constructed required by this type systematic is apparent.In addition, the present invention is not also for any certain programmed language.It should be understood that and various programming language can be utilized to realize content of the present invention described here, and the description done language-specific is above to disclose preferred forms of the present invention.
In instructions provided herein, describe a large amount of detail.But can understand, embodiments of the invention can be put into practice when not having these details.In some instances, be not shown specifically known method, structure and technology, so that not fuzzy understanding of this description.
Similarly, be to be understood that, in order to simplify the disclosure and to help to understand in each inventive aspect one or more, in the description above to exemplary embodiment of the present invention, each feature of the present invention is grouped together in single embodiment, figure or the description to it sometimes.But, the method for the disclosure should be construed to the following intention of reflection: namely the present invention for required protection requires feature more more than the feature clearly recorded in each claim.Or rather, as claims below reflect, all features of disclosed single embodiment before inventive aspect is to be less than.Therefore, the claims following embodiment are incorporated to this embodiment thus clearly, and wherein each claim itself is as independent embodiment of the present invention.
Those skilled in the art are appreciated that and adaptively can change the module in the equipment in embodiment and they are arranged in one or more equipment different from this embodiment.Module in embodiment or unit or assembly can be combined into a module or unit or assembly, and multiple submodule or subelement or sub-component can be put them in addition.Except at least some in such feature and/or process or unit be mutually repel except, any combination can be adopted to combine all processes of all features disclosed in this instructions (comprising adjoint claim, summary and accompanying drawing) and so disclosed any method or equipment or unit.Unless expressly stated otherwise, each feature disclosed in this instructions (comprising adjoint claim, summary and accompanying drawing) can by providing identical, alternative features that is equivalent or similar object replaces.
In addition, those skilled in the art can understand, although embodiments more described herein to comprise in other embodiment some included feature instead of further feature, the combination of the feature of different embodiment means and to be within scope of the present invention and to form different embodiments.Such as, in the following claims, the one of any of embodiment required for protection can use with arbitrary array mode.
All parts embodiment of the present invention with hardware implementing, or can realize with the software module run on one or more processor, or realizes with their combination.It will be understood by those of skill in the art that the some or all functions based on the some or all parts in the digitizer of PXI e interface that microprocessor or digital signal processor (DSP) can be used in practice to realize according to the embodiment of the present invention.The present invention can also be embodied as part or all equipment for performing method as described herein or device program (such as, computer program and computer program).Realizing program of the present invention and can store on a computer-readable medium like this, or the form of one or more signal can be had.Such signal can be downloaded from internet website and obtain, or provides on carrier signal, or provides with any other form.
The present invention will be described instead of limit the invention to it should be noted above-described embodiment, and those skilled in the art can design alternative embodiment when not departing from the scope of claims.

Claims (9)

1. based on a digitizer for PXI e interface, it is characterized in that, comprising:
Analog signal processing and analog/digital A/D conversion circuit unit, for nursing one's health the simulating signal of input, and carry out A/D collection, and the digital signal after being gathered by A/D is input to plate and carries signal processing unit; Described analog signal processing and analog/digital A/D conversion circuit unit specifically comprise: impedance matching module, attenuator, filter and amplification module and A/D acquisition module;
Impedance matching module, for carrying out terminal coupling to described simulating signal;
Attenuator, is made up of the attenuation network of 30dB dynamic range and 0.5dB stepping, decays for the simulating signal exported described impedance matching module;
Filter and amplification module, comprise: wave filter, switch and amplifier, wherein, described wave filter is used for selecting two kinds of filtering modes, and filtering is carried out to the simulating signal that described attenuator exports, wherein, two kinds of filtering modes comprise: low pass mode and the logical mode of band, and the simulating signal that low pass mode completes 100Hz ~ 400MHz receives; The simulating signal that the logical mode of band completes 296.4MHz ~ 346.4MHz receives; Described switch and described amplifier are used for the amplitude of described simulating signal to adjust in the range of receiving of A/D acquisition module;
A/D acquisition module, for carrying out A/D collection, is converted to digital signal by simulating signal;
Triggering administrative unit, for carrying out trigger source distribution, and carrying out burst types management;
Clock Managing Unit, for generation of the clock signal of each unit of described digitizer, and distributes described clock signal;
Plate carries signal processing unit, processes, the I/Q data stream signal that output signal speed is adjustable for the digital signal after gathering A/D;
Capture engine unit, the clock signal for sending according to trigger pip and the described Clock Managing Unit of described triggering administrative unit transmission is carried memory administrative unit to plate and is sent the steering order storing I/Q data stream signal;
Plate carries memory administrative unit, and for the steering order according to described capture engine unit, the described I/Q data stream signal described plate being carried signal processing unit output stores;
PXI e interface logic control element, for communicating with PXIe bus interface, the control signal that reception control unit is sent by PXIe bus interface, read and write according to the register of described control signal to the inner unit of described digitizer, realize the configuration to the unit in described digitizer and control; Obtain described plate and carry the I/Q data stream signal stored in memory administrative unit, by described PXIe bus interface by described I/Q data stream signal to analytic unit;
Described analytic unit, for carrying out oscillography, Vector Signal Analysis and spectrum analysis according to described I/Q data stream signal.
2. digitizer as claimed in claim 1, is characterized in that,
Described trigger source comprises: external, programmable functional interface PFI triggers, core bus triggers, signalling channel 0 triggers and plate carries signal processing unit triggering;
Described burst types comprises: triggering immediately, software trigger and digital triggering.
3. digitizer as claimed in claim 1, it is characterized in that, Clock Managing Unit specifically comprises:
Clock generating module, for by AD9511 chip with reference to clock through phase-locked loop pll frequency multiplication to preset frequency, then through the frequency divider frequency division preset to required frequency;
Clock distribution module, distributes to each unit for the clock signal produced by described AD9511 chip.
4. digitizer as claimed in claim 1, is characterized in that, described PXI e interface logic control element adopts FPGA to realize.
5. digitizer as claimed in claim 2, it is characterized in that, described plate carries signal processing unit and specifically comprises: equalization filter, digital gain module, digimigration module, direct data control DDC module, data processing mode select module and plate to carry signal processing unit OSP trigger module;
Described equalization filter, carries out equalization filtering for the digital signal after A/D gathers;
Described digital gain module, for carrying out digital gain to the digital signal after equalization filtering;
Described digimigration module, carries out digimigration for the digital signal after digital gain;
Described DDC module, for processing the digital signal after digimigration, exports I/Q data stream signal;
Described data processing mode selects module, and for selecting the data processing mode processed described I/Q data stream signal, wherein, described data processing mode comprises: real data tupe and complex data tupe;
OSP trigger module, for sending described I/Q data stream signal to described triggering administrative unit, wherein, described I/Q data stream signal carries the basis for estimation of signal processing unit triggering as plate.
6. digitizer as claimed in claim 5, it is characterized in that, described DDC module specifically comprises:
Frequency translation module, for carrying out digital mixing and down coversion to the digital signal after digimigration;
Fractional frequency division resampling module, for carrying out fractional frequency division resampling to the digital signal of carrying out after down coversion;
Filtering extraction module, for carrying out filtering extraction to the digital signal of input, exports I/Q data stream signal.
7. digitizer as claimed in claim 6, is characterized in that,
Described frequency translation module specifically for: according to the range of scanned frequencies pre-set and sweep frequency stepping, the digital signal after the A/D of input gathers is scanned, the digital oscillator signal that described digital signal is orthogonal with two-way is respectively multiplied, and completes digital mixing and down coversion;
Described filtering extraction module specifically for: by cascaded integrator-comb cic filter, half band HB wave filter and have limit for length's unit impulse response FIR filter to input digital signal carry out high fdrequency component elimination, obtain in-phase component I and quadrature component Q, and obtain described I/Q data stream signal according to in-phase component I and quadrature component Q, wherein, described I/Q data stream signal comprises: I signal parameter, Q signal parameter, M signal parameter, P signal parameter and F signal parameter.
8. digitizer as claimed in claim 7, it is characterized in that, described analytic unit specifically comprises:
Vector analysis module, synchronous with code for carrying out carrier synchronization to described I/Q data stream signal, and Amplitude Compensation and phase compensation are carried out to described I/Q data stream signal, after carrying out filtering by measurement wave filter, described I/Q data stream signal is divided into two-way, and symbol detection of leading up to forms reference signal, and another road is measuring-signal, described reference signal and described measuring-signal are compared, carries out error calculation;
Spectrum analysis module, for being obtained the analysis bandwidth RBW of raw spectroscopy data by the cic filter in described filtering extraction module, HB wave filter and FIR filter, and the display bandwidth VBW of raw spectroscopy data is obtained by amplitude discrimination and FIR filtering, detection is carried out to described raw spectroscopy data, obtain frequency spectrum data, carry out spectrum analysis according to described frequency spectrum data; And control range of scanned frequencies and the sweep frequency stepping of described frequency translation module, wherein, described FIR filter coefficient is constant, the conversion of different bandwidth is realized by the extracting multiple controlling described cic filter and described HB wave filter, wherein, described sweep frequency stepping is less than or equal to 1/3RBW.
9. digitizer as claimed in claim 8, is characterized in that, described spectrum analysis module specifically for:
When the signal frequency that the RBW of 3aMHz will analyze is fin, splice according to the following procedure:
Arranging RBW is 1aMHz, and the power of the signal fin of acquisition is P_db1, and the power of signal fin-1aMHz is P_db0, and the power of signal fin+1aMHz is P_db2, and wherein, a is positive integer;
The RBW equivalent power of 3aMHz: Pow _ eq = 10 P _ db 0 10 + 10 P _ db 1 10 + 10 P _ db 2 10 ;
Being converted into dB value is: Pow_eqdB=10*log10 (Pow_eq).
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