CN103645378B - The pulse power Statistical Measurement of Radial Void that a kind of high speed is seamless catches - Google Patents

The pulse power Statistical Measurement of Radial Void that a kind of high speed is seamless catches Download PDF

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CN103645378B
CN103645378B CN201310684706.XA CN201310684706A CN103645378B CN 103645378 B CN103645378 B CN 103645378B CN 201310684706 A CN201310684706 A CN 201310684706A CN 103645378 B CN103645378 B CN 103645378B
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adc
memory
data
dsp
statistical measurement
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CN103645378A (en
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李金山
徐达旺
冷朋
李强
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CLP Kesiyi Technology Co Ltd
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CETC 41 Institute
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Abstract

The invention provides the seamless pulse power Statistical Measurement of Radial Void of catching of a kind of high speed, in detection and front-end processing unit N1, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, envelope signal after detection, after logarithmic amplification, linear conditioning, is adjusted to detecting circuit the input range that meets A/D converter N2. N2 is 14, the A/D converter of 100Ms/s, detecting circuit converted to adc data, and send FPGA by adc data? N3 inside. Adopt such scheme, sampling rate is fast, can reach 10Ms/s, and guarantee is greater than the modulation signal of 100ns pulsewidth can not be missed, and substantially can meet the statistical measurement demand of radar, guidance, radio communication isopulse power.

Description

The pulse power Statistical Measurement of Radial Void that a kind of high speed is seamless catches
Technical field
The invention belongs to field of measuring technique, in particular the seamless pulse power Statistical Measurement of Radial Void of catching of a kind of high speed.
Background technology
In radar, guidance, radio communication, Ditital modulation method is incorporated into Modulation and Amplitude Modulation and phase-modulation more than one in level institutional framework, is used for representing the bit of a data flow, as communication modes such as CDMA (CDMA). Peak-equal the power ratio of pulse-modulated signal is the complex function of transmitted data, and is not only the function of pulse-modulated signal amplitude. Determined according to the impulse modulation degree of depth and impulse modulation index that the method for emitter or amplifier output power was no longer applicable in the past. And test to emitter or amplifier output power, method is that output pulse power is carried out to long statistical measurement the most accurately.
For the statistical measurement of pulse power, that can look at present has two kinds of methods:
1, the statistical measurement based on mass storage
The basis of this Statistical Measurement of Radial Void is jumbo memory. By in whole sampled data write memories, after memory is write completely, data reading is calculated and analyzed. Its shortcoming is: owing to being subject to the impact of memory span, the data volume of the method storage is limited, can not realize for a long time, not data sampling and the analysis of obliterated data.
2, the seamless Statistical Measurement of Radial Void of catching of low speed
The Statistical Measurement of Radial Void that low speed is seamless catches is compared with under low rate, realizes the seamless of data and catches, and the method speed is slower, is only 1Ms/s. Its shortcoming is: the method can realize long data sampling and analysis, but because its data pick-up speed is lower, be only 1Ms/s, the time interval between two sampled datas is 1us, may miss and width is less than the pulse-modulated signal of 1us, can not ensure exhaustively statistical measurement.
Therefore, there is defect in prior art, needs to improve.
Summary of the invention
Technical problem to be solved by this invention is for the deficiencies in the prior art, provides a kind of high speed seamless pulse power Statistical Measurement of Radial Void of catching.
Technical scheme of the present invention is as follows:
The pulse power Statistical Measurement of Radial Void that high speed is seamless catches, wherein, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, described envelope signal is after logarithmic amplification, linear conditioning, detecting circuit is adjusted to the input range that meets A/D converter, again detecting circuit is converted to adc data, and send FPGA inside by adc data;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, first DSP is written to frequency response data in frequency response data register, then carry out multiplying by multiplier and each ADC, adc data after compensation is under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: in the time that control signal CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in first memory, once-through operation fixedly writes 1000 adc datas, simultaneously, DSP, by enhancement mode direct memory access interface, reads the data that write in second memory in DSP internal RAM; In the time that control signal CTL is low level, the 1001st seamless being written in second memory of data, once-through operation fixedly writes 1000 adc datas, and DSP, by enhancement mode direct memory access interface, reads the data that write in first memory in DSP internal RAM;
Step 5: in DSP inside, adopt lookup table mode to carry out statistical measurement, ADC statistical table taking ADC value as index construct, the number of times that cumulative each ADC value of statistics occurs, the number of times that the cumulative all ADC of ADC quantity statistics register occur, number of times by the number of times that in ADC statistical table, each ADC occurs divided by the cumulative all ADC of ADC quantity statistics register, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, and ADC-power transfer form, by calibration, builds the power form taking ADC as index; Each ADC value, after ADC statistical table, is converted to milliwatt value, obtains one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside, and this form is left in the memory space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in corresponding with probability of occurrence performance number milliwatt form, according to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
Described measuring method, wherein, in described step 1, A/D converter is 14, the A/D converter of 100Ms/s.
Described measuring method, wherein, in described step 3, described first memory and second memory are the memory that 14, the degree of depth are 1024; Described control signal CTL produces by reading and writing control generation unit, and read-write is controlled generation unit and driven by the sampling clock of 10Ms/s, reverses once every 1000 clock cycle, produces control signal CTL; Control signal CTL is as the enable signal of first memory, and the data of controlling first memory write and read; Control signal CTL is after phase inverter negate, and as the enable signal of second memory, the data of controlling second memory write and read.
Described measuring method, wherein, in described step 4, DSP is enhancement mode direct memory access interface by the interface configuration that reads 2 first memories and second memory, and enhancement mode direct memory access interface reading rate is set is greater than speed 5-10 that ADC writes first memory and second memory doubly.
Described measuring method, wherein, described DSP inside is provided with ADC statistical table and ADC power transfer form; Described ADC statistical table, taking ADC as index, builds the form of an ADC probability of occurrence, in statistical measurement process, ADC is set and occurs once, and in the form that is just ADC by index, data add 1; Described ADC power transfer form, is taking ADC as index, sets up form corresponding between ADC and performance number.
Described measuring method, wherein, also performs step 5 after described step 4: after the statistical measurement having calculated in DSP, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show.
Adopt such scheme: 1, sampling rate is fast, can reach 10Ms/s, guarantee is greater than the modulation signal of 100ns pulsewidth can not be missed, and substantially can meet the statistical measurement demand of radar, guidance, radio communication isopulse power. 2, really realized seamless statistical measurement, be not subject to the restriction of memory span, in long-time, statistical measurement can not lost sampled data.
Brief description of the drawings
Fig. 1 is the seamless microwave power Statistical Measurement of Radial Void circuit diagram of catching of high speed of the present invention.
Fig. 2 is the seamless microwave power Statistical Measurement of Radial Void sequential chart of catching of high speed of the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Embodiment 1
Main circuit of the present invention will comprise detection and front-end processing unit N1, A/D (mould/number) converter N2, FPGA (PLD) N3, DSP (digital signal processor) N4, CPU (central processing unit) N5. In detection and front-end processing unit N1, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, the envelope signal after detection, after logarithmic amplification, linear conditioning, is adjusted to detecting circuit the input range that meets A/D converter N2. N2 is 14, the A/D converter of 100Ms/s, detecting circuit is converted to adc data, and send FPGAN3 inside by adc data.
Owing to being subject to the impact of DSP, CPU processing speed, under 100Ms/s speed, cannot complete the statistical measurement without loss of data, therefore the present invention carries out reduction of speed processing to seamless statistical measurement of catching. Reduction of speed is processed in the 1:10 data pick-up unit N6 by FPGA inside and is completed, and it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s.
In order to reduce the workload of DSP, the compensating for frequency response of power measurement is completed in FPGA. First DSP is written to frequency response data in frequency response data register N7, then, by multiplier N8, carries out multiplying with each ADC. Adc data after compensation is under the control of signal CTL, and timesharing writes first memory FIFO1N9, second memory FIFO2N10.
N9, N10 are that figure place is FIFO (FIFO) memory that 14, the degree of depth are 1024, control signal CTL produces by reading and writing control generation unit N11, read-write is controlled generation unit N11 and is driven by the sampling clock of 10Ms/s, reverse once every 1000 clock cycle, produce CTL control signal. CTL is as the enable signal of N9, and the data of controlling N9 write and read; CTL is through N12---and after phase inverter negate, as the enable signal of N10, the data of controlling N10 write and read.
Be illustrated in figure 2 two FIFO and realize seamless sequential chart of catching, concrete operations sequential is as follows:
1) in the time that CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in FIFO1, and once-through operation fixedly writes 1000 adc datas;
2), when CTL is high level, DSP, by EDMA (enhancement mode direct memory access) interface, reads the data that write in FIFO2 in DSP internal RAM;
3) when CTL becomes after low level, the 1001st seamless being written in FIFO2 of data, once-through operation is also fixedly to write 1000 adc datas;
4), when CTL becomes after low level, DSP, by EDMA interface, reads the data that write in FIFO1 in DSP internal RAM.
In order to ensure the speed of DSP reading out data from FIFO, DSP is EDMA interface by the interface configuration that reads 2 FIFO, and EDMA interface reading rate will write the speed of FIFO far away higher than ADC, can ensure upper once before adc data writes FIFO, FIFO is read to sky, do not lose any data.
Dsp processor has powerful data processing function, and therefore all software of the present invention calculates and all completes in DSP inside, and CPU just shows result of calculation in screen.
Three kinds of statistical measurement pattern: PDF (probability density function figure), CDF (cumulative distribution function figure) and CCDF (benefit-cumulative distribution function figure), its core is the probability that each power points of statistics occurs with respect to all sampled points.
In order to improve the arithmetic speed of DSP, probability statistics and ADC and power transfer have all adopted the mode of tabling look-up. As shown in Figure 1, there are 2 forms in DSP inside: ADC statistical table N13, ADC-power transfer form N15.
N13 is taking ADC as index, builds the form of an ADC probability of occurrence. In statistical measurement process, if a certain ADC occur once, in the form that is just ADC by index, data add 1. For example, from starting statistical measurement, the data that ADC value is 1000 have occurred 100 times, and the data of storing in the 1000th form in N13 are 100. The adc data that ADC quantity statistics register N14 storage is caught altogether. Value by N13 form intermediate value divided by N14 register is exactly the probability that each ADC occurs.
ADC is converted to power data and completes by ADC-power transfer form N15. N15 is by the calibration of power, taking ADC as index, sets up form corresponding between ADC and performance number. Adc data is tabled look-up and is converted to power data in N15. Adc data is tabled look-up and is converted to power data mW value in N15 kind, obtains one group of form that performance number mW is corresponding with probability of occurrence in DSP inside, and this form is left in the memory space that DSP is inner fixing;
After the statistical measurement having calculated in DSP, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show. After the statistical measurement having calculated in DSP, CPU passes through pci interface, by the data reading in corresponding with probability of occurrence performance number mW form, according to user's setting, can respectively statistical measurement be shown as to PDF (probability density function figure), CDF (cumulative distribution function figure) and CCDF (benefit-cumulative distribution function figure), and the unit of display can be selected mW or dBm.
Embodiment 2
On the basis of above-described embodiment, further, as Figure 1-Figure 2, the pulse power Statistical Measurement of Radial Void that a kind of high speed is seamless catches, wherein, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, described envelope signal is after logarithmic amplification, linear conditioning, detecting circuit is adjusted to the input range that meets A/D converter, again detecting circuit is converted to adc data, and send FPGA inside by adc data;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, first DSP is written to frequency response data in frequency response data register, then carry out multiplying by multiplier and each ADC, adc data after compensation is under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: in the time that control signal CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in first memory, once-through operation fixedly writes 1000 adc datas, simultaneously, DSP, by enhancement mode direct memory access interface, reads the data that write in second memory in DSP internal RAM; In the time that control signal CTL is low level, the 1001st seamless being written in second memory of data, once-through operation fixedly writes 1000 adc datas, and DSP, by enhancement mode direct memory access interface, reads the data that write in first memory in DSP internal RAM;
Step 5: in DSP inside, adopt lookup table mode to carry out statistical measurement, ADC statistical table taking ADC value as index construct, the number of times that cumulative each ADC value of statistics occurs, the number of times that the cumulative all ADC of ADC quantity statistics register occur, number of times by the number of times that in ADC statistical table, each ADC occurs divided by the cumulative all ADC of ADC quantity statistics register, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, and ADC-power transfer form, by calibration, builds the power form taking ADC as index; Each ADC value, after ADC statistical table, is converted to milliwatt value, obtains one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside, and this form is left in the memory space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in corresponding with probability of occurrence performance number milliwatt form, according to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
In described step 1, A/D converter is 14, the A/D converter of 100Ms/s.
In described step 3, described first memory and second memory are the memory that 14, the degree of depth are 1024; Described control signal CTL produces by reading and writing control generation unit, and read-write is controlled generation unit and driven by the sampling clock of 10Ms/s, reverses once every 1000 clock cycle, produces control signal CTL; Control signal CTL is as the enable signal of first memory, and the data of controlling first memory write and read; Control signal CTL is after phase inverter negate, and as the enable signal of second memory, the data of controlling second memory write and read.
In described step 4, DSP is enhancement mode direct memory access interface by the interface configuration that reads 2 first memories and second memory, and enhancement mode direct memory access interface reading rate is set is greater than speed 5-10 that ADC writes first memory and second memory doubly.
Described DSP inside is provided with ADC statistical table and ADC power transfer form; Described ADC statistical table, taking ADC as index, builds the form of an ADC probability of occurrence, in statistical measurement process, ADC is set and occurs once, and in the form that is just ADC by index, data add 1; Described ADC power transfer form, is taking ADC as index, sets up form corresponding between ADC and performance number.
After described step 4, also perform step 5: after the statistical measurement having calculated, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show in DSP.
Adopt such scheme: 1, sampling rate is fast, can reach 10Ms/s, guarantee is greater than the modulation signal of 100ns pulsewidth can not be missed, and substantially can meet the statistical measurement demand of radar, guidance, radio communication isopulse power. 2, really realized seamless statistical measurement, be not subject to the restriction of memory span, in long-time, statistical measurement can not lost sampled data.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.

Claims (6)

1. the seamless pulse power Statistical Measurement of Radial Void of catching of high speed, is characterized in that, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain microwave signalEnvelope signal, described envelope signal, after logarithmic amplification, linear conditioning, is adjusted to detecting circuit to meetThe input range of A/D converter, then detecting circuit is converted to adc data, and send FPGA by adc dataInner;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speedRate is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, and first DSP is written to frequency response dataIn frequency response data register, then carry out multiplying by multiplier and each ADC, the ADC after compensationData are under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: in the time that control signal CTL is high level, the ADC that the clock of 10Ms/s is crossed compensating for frequency responseData continue to write in first memory, and once-through operation fixedly writes 1000 adc datas, meanwhile, and DSPBy enhancement mode direct memory access interface, the data that write in second memory are read to DSP insideIn RAM; In the time that control signal CTL is low level, what the 1001st data were seamless is written to the second storageIn device, once-through operation fixedly writes 1000 adc datas, and DSP connects by enhancement mode direct memory accessMouthful, the data that write in first memory are read in DSP internal RAM;
Step 5: in DSP inside, adopt lookup table mode to carry out statistical measurement, taking ADC value as index constructADC statistical table, the number of times of each ADC value appearance of cumulative statistics, the ADC quantity statistics register institute that adds upThe number of times that has ADC to occur, posts the number of times that in ADC statistical table, each ADC occurs divided by ADC quantity statisticsThe number of times of all ADC that storage adds up, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, ADC-power transfer tableLattice, by calibration, build the power form taking ADC as index; Each ADC value is at process ADC statistical tableAfter, be converted to milliwatt value, obtain one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside,And this form is left in the memory space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in corresponding with probability of occurrence performance number milliwatt form,According to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
2. measuring method as claimed in claim 1, is characterized in that, in described step 1, and A/D converterBe 14, the A/D converter of 100Ms/s.
3. measuring method as claimed in claim 1, is characterized in that, in described step 3, described first depositsReservoir and second memory are the memory that 14, the degree of depth are 1024; Described control signal CTL is by reading and writing controlGeneration unit processed produces, and read-write is controlled generation unit and driven by the sampling clock of 10Ms/s, in the time of 1000Clock periodic reversal once, produces control signal CTL; Control signal CTL is as the enable signal of first memory,The data of controlling first memory write and read; Control signal CTL is after phase inverter negate, as secondThe enable signal of memory, the data of controlling second memory write and read.
4. measuring method as claimed in claim 1, is characterized in that, in described step 4, DSP will readThe interface configuration of 2 first memories and second memory is enhancement mode direct memory access interface, and arrangesEnhancement mode direct memory access interface reading rate is greater than ADC and writes first memory and second memorySpeed 5-10 doubly.
5. measuring method as claimed in claim 4, is characterized in that, described DSP inside is provided with ADCStatistical table and ADC power transfer form; Described ADC statistical table, taking ADC as index, builds an ADCThe form of probability of occurrence, in statistical measurement process, arranges ADC and occurs once, the table that is just ADC by indexIn lattice, data add 1; Described ADC power transfer form, is taking ADC as index, set up ADC and performance number itBetween corresponding form.
6. measuring method as claimed in claim 1, is characterized in that, after described step 4, also performs step5: after the statistical measurement having calculated in DSP, CPU is by pci interface, successively by the number of needs demonstrationAccording to reading from DSP, in screen, show.
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104393858B (en) * 2014-10-10 2017-07-11 中国电子科技集团公司第四十一研究所 A kind of compensating for frequency response data Real-time Generation based on static RAM
CN109030934B (en) * 2018-06-07 2020-07-03 中国电子科技集团公司第四十一研究所 Method for improving peak power measurement speed
CN112051442B (en) * 2020-08-05 2023-08-25 中电科思仪科技股份有限公司 Method for improving time parameter measurement speed in microwave peak power measurement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102495277A (en) * 2011-12-09 2012-06-13 中国人民解放军第二炮兵计量站 Repetition frequency vibrating pulse power measurement device
CN102565521A (en) * 2011-12-14 2012-07-11 中国电子科技集团公司第四十一研究所 High-precision wide-dynamic-range microwave signal level test device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6525545B2 (en) * 2001-02-28 2003-02-25 Tektronix, Inc. Frequency domain reflection measurement device
US6608475B2 (en) * 2001-08-23 2003-08-19 Tektronix, Inc. Network analyzer using time sequenced measurements
US9170986B2 (en) * 2009-11-06 2015-10-27 City University Of Hong Kong Power quality meter and method of waveform anaylsis and compression
CN204495996U (en) * 2011-10-26 2015-07-22 菲力尔系统公司 broadband sonar receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102495277A (en) * 2011-12-09 2012-06-13 中国人民解放军第二炮兵计量站 Repetition frequency vibrating pulse power measurement device
CN102565521A (en) * 2011-12-14 2012-07-11 中国电子科技集团公司第四十一研究所 High-precision wide-dynamic-range microwave signal level test device

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
功率统计测量的设计与应用;宁泽洪 等;《仪器仪表学报》;20100831;第31卷(第8期);第326-329页 *
基于CCDF的微波功率统计测量的算法设计;宁泽洪 等;《2011年全国微波毫米波会议论文集(下册)》;20111231;第1157-1160页 *
峰值功率分析仪中功率统计技术及其应用;冷朋 等;《国外电子测量技术》;20080831;第27卷(第8期);第12-14页 *

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