CN103645378A - High-speed seamless capture pulse power statistics measuring method - Google Patents
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Abstract
The invention provides a high-speed seamless capture pulse power statistics measuring method. The method comprises: in a demodulation and front-end processing unit N1, performing demodulation on microwave signals to obtain envelope signals of the microwave signals, after logarithmic amplification and linear conditioning are performed on the envelope signals after demodulation, adjusting demodulation voltages to the input scope of an A/D converter N2, the N2 being a 14-digit A/D converter with a rate of 100 Ms/s, converting the demodulation voltages into ADC data, and sending the ADC data into an FPGA N3. By using the scheme, the sampling rate can be as fast as 10 Ms/s so that modulation signals with pulse widths greater than 100 ns are not missed, and the statistics measuring demands of pulse power such as radar, guidance, wireless communication and the like can be basically satisfied.
Description
Technical field
The invention belongs to field of measuring technique, in particular the seamless pulse power Statistical Measurement of Radial Void of catching of a kind of high speed.
Background technology
In radar, guidance, radio communication, Ditital modulation method is incorporated into Modulation and Amplitude Modulation and phase-modulation more than one in level institutional framework, is used for representing the bit of a data stream, as CDMA(CDMA) etc. communication mode.The peak of pulse-modulated signal-all power ratio is the complex function of transmitted data, and is not only the function of pulse-modulated signal amplitude.According to the pulsed modulation degree of depth and pulsed modulation index, determined that the method for transmitter or amplifier output power was no longer applicable in the past.And test to transmitter or amplifier output power, method is that output pulse power is carried out to long statistical measurement the most accurately.
For the statistical measurement of pulse power, that can look at present has two kinds of methods:
1, the statistical measurement based on mass storage
The basis of this Statistical Measurement of Radial Void is jumbo storer.By in the whole write stories of sampled data, after storer is write completely, data reading is calculated and analyzed.Its shortcoming is: owing to being subject to the impact of memory span, the data volume of the method storage is limited, can not realize for a long time, not data sampling and the analysis of obliterated data.
2, the seamless Statistical Measurement of Radial Void of catching of low speed
The Statistical Measurement of Radial Void that low speed is seamless catches is compared with under low rate, realizes the seamless of data and catches, and the method speed is slower, is only 1Ms/s.Its shortcoming is: the method can realize long data sampling and analysis, but because its data pick-up speed is lower, be only 1Ms/s, the time interval between two sampled datas is 1us, and width is less than the pulse-modulated signal of 1us, may miss, can not guarantee exhaustively statistical measurement.
Therefore, there is defect in prior art, needs to improve.
Summary of the invention
Technical matters to be solved by this invention is for the deficiencies in the prior art, provides a kind of high speed seamless pulse power Statistical Measurement of Radial Void of catching.
Technical scheme of the present invention is as follows:
The pulse power Statistical Measurement of Radial Void that high speed is seamless catches, wherein, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, described envelope signal is after logarithmic amplification, linear conditioning, detecting circuit is adjusted to the input range that meets A/D converter, again detecting circuit is converted to adc data, and send FPGA inner adc data;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, first DSP is written to frequency response data in frequency response data register, then by multiplier and each ADC, carry out multiplying, adc data after compensation is under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: when control signal CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in first memory, single job fixedly writes 1000 adc datas, simultaneously, DSP, by enhancement mode direct memory access interface, reads the data that write in second memory in DSP internal RAM; When control signal CTL is low level, the 1001st seamless being written in second memory of data, single job fixedly writes 1000 adc datas, and DSP, by enhancement mode direct memory access interface, reads the data that write in first memory in DSP internal RAM;
Step 5: inner at DSP, adopt lookup table mode to carry out statistical measurement, the ADC statistical table that the ADC value of take is index construct, the number of times that cumulative each ADC value of statistics occurs, the number of times that the cumulative all ADC of ADC quantity statistics register occur, number of times by the number of times that in ADC statistical table, each ADC occurs divided by the cumulative all ADC of ADC quantity statistics register, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, and ADC-power transfer form is by calibration, builds to take the power form that ADC is index; Each ADC value, after ADC statistical table, is converted to milliwatt value, obtains one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside, and this form is left in the storage space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in performance number milliwatt form corresponding to probability of occurrence, according to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
Described measuring method, wherein, in described step 1, A/D converter is 14, the A/D converter of 100Ms/s.
Described measuring method, wherein, in described step 3, described first memory and second memory are the storer that 14, the degree of depth are 1024; Described control signal CTL produces by reading and writing control generation unit, and read-write control generation unit is driven by the sampling clock of 10Ms/s, every 1000 clock period reversions once, produces control signal CLT; Control signal CLT is as the enable signal of first memory, and the data of controlling first memory write and read; Control signal CTL is after phase inverter negate, and as the enable signal of second memory, the data of controlling second memory write and read.
Described measuring method, wherein, in described step 4, DSP is enhancement mode direct memory access interface by the interface configuration that reads 2 first memories and second memory, and enhancement mode direct memory access interface reading rate is set is greater than speed 5-10 that ADC writes first memory and second memory doubly.
Described measuring method, wherein, described DSP inside is provided with ADC statistical table and ADC power transfer form; Described ADC statistical table be take ADC as index, builds the form of an ADC probability of occurrence, in statistical measurement process, ADC is set and occurs once, and in the form that is just ADC by index, data add 1; Described ADC power transfer form, is to take ADC as index, sets up form corresponding between ADC and performance number.
Described measuring method, wherein, also performs step 5 after described step 4: after the statistical measurement having calculated in DSP, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show.
Adopt such scheme: 1, sampling rate is fast, can reach 10Ms/s, assurance is greater than the modulation signal of 100ns pulsewidth and can miss, and substantially can meet the statistical measurement demand of radar, guidance, radio communication isopulse power.2, really realized seamless statistical measurement, be not subject to the restriction of memory span, in long-time, statistical measurement can not lost sampled data.
Accompanying drawing explanation
Fig. 1 is the seamless microwave power Statistical Measurement of Radial Void circuit diagram of catching of high speed of the present invention.
Fig. 2 is the seamless microwave power Statistical Measurement of Radial Void sequential chart of catching of high speed of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
Main circuit of the present invention will comprise detection and front-end processing unit N1, A/D(mould/number) converter N2, FPGA(programmable logic device (PLD)) N3, DSP(digital signal processor) N4, CPU(central processing unit) N5.
In detection and front-end processing unit N1, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, the envelope signal after detection, after logarithmic amplification, linear conditioning, is adjusted to detecting circuit the input range that meets A/D converter N2.N2 is 14, the A/D converter of 100Ms/s, and detecting circuit is converted to adc data, and send FPGA N3 inner adc data.
Owing to being subject to the impact of DSP, CPU processing speed, under 100Ms/s speed, cannot complete the statistical measurement without loss of data, so the present invention carries out reduction of speed processing to seamless statistical measurement of catching.Reduction of speed is processed in the 1:10 data pick-up unit N6 by FPGA inside and is completed, and it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s.
In order to reduce the workload of DSP, the compensating for frequency response of power measurement is completed in FPGA.First DSP is written to frequency response data in frequency response data register N7, then, by multiplier N8, carries out multiplying with each ADC.Adc data after compensation is under the control of signal CTL, and timesharing writes first memory FIFO1N9, second memory FIFO2N10.
N9, N10 are that figure place is the FIFO(first-in first-out that 14, the degree of depth are 1024) storer, control signal CTL produces by reading and writing control generation unit N11, read-write control generation unit N11 is driven by the sampling clock of 10Ms/s, every 1000 clock period reversions once, produces CLT control signal.CLT is as the enable signal of N9, and the data of controlling N9 write and read; CTL is through N12---and after phase inverter negate, as the enable signal of N10, the data of controlling N10 write and read.
Be illustrated in figure 2 two FIFO and realize seamless sequential chart of catching, concrete operations sequential is as follows:
1) when CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in FIFO1, and single job fixedly writes 1000 adc datas;
2), when CTL is high level, DSP is by EDMA(enhancement mode direct memory access) interface, the data that write in FIFO2 are read in DSP internal RAM;
3) when CTL becomes after low level, the 1001st seamless being written in FIFO2 of data, single job is also fixedly to write 1000 adc datas;
4), when CTL becomes after low level, DSP, by EDMA interface, reads the data that write in FIFO1 in DSP internal RAM.
In order to guarantee the speed of DSP reading out data from FIFO, DSP is EDMA interface by the interface configuration that reads 2 FIFO, and EDMA interface reading rate will write the speed of FIFO far away higher than ADC, can guarantee upper once before adc data writes FIFO, FIFO is read to sky, do not lose any data.
Dsp processor has powerful data processing function, so all software of the present invention calculates and all in DSP inside, complete, and CPU just shows result of calculation in screen.
Three kinds of statistical measurement patterns: PDF(probability density function figure), CDF(cumulative distribution function figure) and CCDF(benefit-cumulative distribution function figure), its core is the probability that each power points of statistics occurs with respect to all sampled points.
In order to improve the arithmetic speed of DSP, probability statistics and ADC and power transfer have all adopted the mode of tabling look-up.As shown in Figure 1, in DSP inside, there are 2 forms: ADC statistical table N13, ADC-power transfer form N15.
N13 be take ADC as index, builds the form of an ADC probability of occurrence.In statistical measurement process, if a certain ADC appearance once, in the form that is just ADC by index, data add 1.For example, from starting statistical measurement, the data that ADC value is 1000 have occurred 100 times, and the data of storing in the 1000th form in N13 are 100.The adc data that ADC quantity statistics register N14 storage is caught altogether.Value by N13 form intermediate value divided by N14 register is exactly the probability that each ADC occurs.
ADC is converted to power data and completes by ADC-power transfer form N15.N15 is by the calibration of power, take ADC as index, sets up form corresponding between ADC and performance number.Adc data is tabled look-up and is converted to power data in N15.Adc data is tabled look-up and is converted to power data mW value in N15 kind, obtains one group of form that performance number mW is corresponding with probability of occurrence in DSP inside, and this form is left in the storage space that DSP is inner fixing;
After the statistical measurement having calculated in DSP, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show.After the statistical measurement having calculated in DSP, CPU passes through pci interface, by the data reading in performance number mW form corresponding to probability of occurrence, according to user's setting, can respectively statistical measurement be shown as to PDF(probability density function figure), CDF(cumulative distribution function figure) and CCDF(benefit-cumulative distribution function figure), and the unit of display can be selected mW or dBm.
On the basis of above-described embodiment, further, as Figure 1-Figure 2, the pulse power Statistical Measurement of Radial Void that a kind of high speed is seamless catches, wherein, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, described envelope signal is after logarithmic amplification, linear conditioning, detecting circuit is adjusted to the input range that meets A/D converter, again detecting circuit is converted to adc data, and send FPGA inner adc data;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, first DSP is written to frequency response data in frequency response data register, then by multiplier and each ADC, carry out multiplying, adc data after compensation is under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: when control signal CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in first memory, single job fixedly writes 1000 adc datas, simultaneously, DSP, by enhancement mode direct memory access interface, reads the data that write in second memory in DSP internal RAM; When control signal CTL is low level, the 1001st seamless being written in second memory of data, single job fixedly writes 1000 adc datas, and DSP, by enhancement mode direct memory access interface, reads the data that write in first memory in DSP internal RAM;
Step 5: inner at DSP, adopt lookup table mode to carry out statistical measurement, the ADC statistical table that the ADC value of take is index construct, the number of times that cumulative each ADC value of statistics occurs, the number of times that the cumulative all ADC of ADC quantity statistics register occur, number of times by the number of times that in ADC statistical table, each ADC occurs divided by the cumulative all ADC of ADC quantity statistics register, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, and ADC-power transfer form is by calibration, builds to take the power form that ADC is index; Each ADC value, after ADC statistical table, is converted to milliwatt value, obtains one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside, and this form is left in the storage space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in performance number milliwatt form corresponding to probability of occurrence, according to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
In described step 1, A/D converter is 14, the A/D converter of 100Ms/s.
In described step 3, described first memory and second memory are the storer that 14, the degree of depth are 1024; Described control signal CTL produces by reading and writing control generation unit, and read-write control generation unit is driven by the sampling clock of 10Ms/s, every 1000 clock period reversions once, produces control signal CLT; Control signal CLT is as the enable signal of first memory, and the data of controlling first memory write and read; Control signal CTL is after phase inverter negate, and as the enable signal of second memory, the data of controlling second memory write and read.
In described step 4, DSP is enhancement mode direct memory access interface by the interface configuration that reads 2 first memories and second memory, and enhancement mode direct memory access interface reading rate is set is greater than speed 5-10 that ADC writes first memory and second memory doubly.
Described DSP inside is provided with ADC statistical table and ADC power transfer form; Described ADC statistical table be take ADC as index, builds the form of an ADC probability of occurrence, in statistical measurement process, ADC is set and occurs once, and in the form that is just ADC by index, data add 1; Described ADC power transfer form, is to take ADC as index, sets up form corresponding between ADC and performance number.
After described step 4, also perform step 5: after the statistical measurement having calculated, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show in DSP.
Adopt such scheme: 1, sampling rate is fast, can reach 10Ms/s, assurance is greater than the modulation signal of 100ns pulsewidth and can miss, and substantially can meet the statistical measurement demand of radar, guidance, radio communication isopulse power.2, really realized seamless statistical measurement, be not subject to the restriction of memory span, in long-time, statistical measurement can not lost sampled data.
Should be understood that, for those of ordinary skills, can be improved according to the above description or convert, and all these improvement and conversion all should belong to the protection domain of claims of the present invention.
Claims (6)
1. the seamless pulse power Statistical Measurement of Radial Void of catching of high speed, is characterized in that, comprises the steps:
Step 1: in detection and front-end processing unit, microwave signal is carried out to detection, obtain the envelope signal of microwave signal, described envelope signal is after logarithmic amplification, linear conditioning, detecting circuit is adjusted to the input range that meets A/D converter, again detecting circuit is converted to adc data, and send FPGA inner adc data;
Step 2: carry out reduction of speed processing, completed by the 1:10 data pick-up unit of FPGA inside, it extracts speed is 10Ms/s, and the ADC speed after extraction is 10Ms/s;
Step 3: the compensating for frequency response of power measurement is completed in FPGA, first DSP is written to frequency response data in frequency response data register, then by multiplier and each ADC, carry out multiplying, adc data after compensation is under the control of control signal CTL, and timesharing writes first memory and second memory;
Step 4: when control signal CTL is high level, the adc data that the clock of 10Ms/s is crossed compensating for frequency response continues to write in first memory, single job fixedly writes 1000 adc datas, simultaneously, DSP, by enhancement mode direct memory access interface, reads the data that write in second memory in DSP internal RAM; When control signal CTL is low level, the 1001st seamless being written in second memory of data, single job fixedly writes 1000 adc datas, and DSP, by enhancement mode direct memory access interface, reads the data that write in first memory in DSP internal RAM;
Step 5: inner at DSP, adopt lookup table mode to carry out statistical measurement, the ADC statistical table that the ADC value of take is index construct, the number of times that cumulative each ADC value of statistics occurs, the number of times that the cumulative all ADC of ADC quantity statistics register occur, number of times by the number of times that in ADC statistical table, each ADC occurs divided by the cumulative all ADC of ADC quantity statistics register, obtains the probability that each ADC value occurs;
Step 6:ADC value adopts the power data that the lookup table mode unit of being converted to is milliwatt, and ADC-power transfer form is by calibration, builds to take the power form that ADC is index; Each ADC value, after ADC statistical table, is converted to milliwatt value, obtains one group of form that performance number milliwatt is corresponding with probability of occurrence in DSP inside, and this form is left in the storage space that DSP is inner fixing;
Step 7:CPU passes through pci interface, by the data reading in performance number milliwatt form corresponding to probability of occurrence, according to user's setting, respectively statistical measurement is shown as to probability density function figure, cumulative distribution function figure and benefit-cumulative distribution function figure, and the unit of display is milliwatt or dBm.
2. measuring method as claimed in claim 1, is characterized in that, in described step 1, A/D converter is 14, the A/D converter of 100Ms/s.
3. measuring method as claimed in claim 1, is characterized in that, in described step 3, described first memory and second memory are the storer that 14, the degree of depth are 1024; Described control signal CTL produces by reading and writing control generation unit, and read-write control generation unit is driven by the sampling clock of 10Ms/s, every 1000 clock period reversions once, produces control signal CLT; Control signal CLT is as the enable signal of first memory, and the data of controlling first memory write and read; Control signal CTL is after phase inverter negate, and as the enable signal of second memory, the data of controlling second memory write and read.
4. measuring method as claimed in claim 1, it is characterized in that, in described step 4, DSP is enhancement mode direct memory access interface by the interface configuration that reads 2 first memories and second memory, and enhancement mode direct memory access interface reading rate is set is greater than speed 5-10 that ADC writes first memory and second memory doubly.
5. measuring method as claimed in claim 4, is characterized in that, described DSP inside is provided with ADC statistical table and ADC power transfer form; Described ADC statistical table be take ADC as index, builds the form of an ADC probability of occurrence, in statistical measurement process, ADC is set and occurs once, and in the form that is just ADC by index, data add 1; Described ADC power transfer form, is to take ADC as index, sets up form corresponding between ADC and performance number.
6. measuring method as claimed in claim 1, is characterized in that, after described step 4, also performs step 5: after the statistical measurement having calculated in DSP, CPU is by pci interface, and the data that successively needs shown are read from DSP, in screen, show.
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