CN101860358A - Single-photon counting system and counting method - Google Patents
Single-photon counting system and counting method Download PDFInfo
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- CN101860358A CN101860358A CN 201010203524 CN201010203524A CN101860358A CN 101860358 A CN101860358 A CN 101860358A CN 201010203524 CN201010203524 CN 201010203524 CN 201010203524 A CN201010203524 A CN 201010203524A CN 101860358 A CN101860358 A CN 101860358A
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Abstract
The invention discloses a single-photon counting system and a counting method. The system comprises a flip-latch, a triggering circuit, a clock generating circuit, a counting unit and a memory, wherein the counting unit comprises two counters, the ping-pong operation is adopted for carrying out the single-photon counting, the dead time is short, and the counting efficiency is high. The system can be realized through an FPGA field programmable gate array, and the hardware realization of the system has better flexibility and performance. In addition, the system can be connected with an external system through an embedded type chip and a USB bus, high-speed data transmission can be realized, and the invention has better real-time performance.
Description
Technical field
The present invention relates generally to faint light detection counting field, specifically, relate to a kind of single photon counting system and method for counting that is used for faint light detection.
Background technology
In the faint light detection field, the single-photon detecting survey technology has a wide range of applications in fields such as laser radar, bioluminescence, quantum secret communication, high resolution spectral measuring, non-destructive species analysis, the detection of high speed phenomenon, rigorous analysis, radiation detection, high-energy physics, astronomical photometry, optical time domain reflections.General faint light detection number system mainly comprises single-photon detecting examining system, single photon counting system and computer system, single-photon detecting examining system output electric pulse signal, the single photon counting system realizes the counting to single photon by electric impulse signal is counted.
At present, for the single photon counting system, mainly realize by special chip, also there are some to realize,, have the low problem of counting efficiency for these systems by adopting DSP or single-chip microcomputer and flush bonding processor, and hardware capability is fixed, versatility is poor, interface also mostly is pci interface, serial ports or parallel port, and its transmission speed is low, causes real-time property poor, especially for the system of pci interface, its hardware power supply is from computer-internal, and the noise of power supply is bigger, the accuracy of influence counting.
Therefore, be necessary to propose the single photon counting system that a kind of versatility is good, counting efficiency is high.
Summary of the invention
In order to address the above problem, the invention provides a kind of single photon counting system, described system comprises: latch is used for receiving and the stored parameter setting; Circuits for triggering are used to trigger counting operation N time, and described circuits for triggering allow to receive from outer triggering signal, and transmit outer triggering signal to clock generation circuit, with flip-flop number; Clock generation circuit in response to the triggering signal of coming automatic triggering circuit, produces the clock signal in predetermined clock cycle; Counting unit, when the n time triggering signal was effective, the photon signal that each the is received clock cycle counting of rattling was up to passing through X clock cycle, wherein 0≤n≤N; Memory is used for the stored count unit in the described X count results of a clock cycle, as the n+1 time triggering signal when effective, and the basis of the table tennis of corresponding clock cycle counting, wherein said N, X are positive integer.Wherein said counting unit comprises first counter and second counter, described first counter and second counter replace counting according to the clock cycle, and count results is stored into the memory location that is used for storing the count results in a clock cycle on this in the memory in next clock cycle, described first counter and second counter obtain the count results of corresponding clock cycle in the memory next time before counting, and on the radix of this count results, carry out accumulated counts, preferably, can by address production electric circuit the operation appointment access address of counter.Wherein said counting unit comprises and the corresponding many cover counting units of the quantity of exterior light subsignal.
Preferably, described system also comprises digital to analog converter and comparator, described digital to analog converter is used for providing to comparator the threshold value of outer triggering signal and exterior light subsignal, described comparator is according to described threshold value, carry out signal identification, and outer triggering signal and exterior light subsignal after circuits for triggering and counting unit provide identification.
Alternatively, described system also comprises synchronous circuit, is used for the clock synchronization with exterior light subsignal and clock generation circuit.
Alternatively, described system also comprises phase-locked loop, is used to clock generation circuit and synchronous circuit that reference clock is provided.
Preferably, described system is realized by the FPGA field programmable gate array.
Preferably, described system is connected with external system with usb bus by embedded chip.
The present invention also provides a kind of single-photon counting method that is used for said system, and described method comprises:
S01 receives outer triggering signal the n time by circuits for triggering, with flip-flop number, and 0≤n≤N wherein;
S02, clock generation circuit produce the clock signal with period T according to described triggering signal;
S03, under x counting clock periodic signal, count value D1 (n-1 by first counter of first counter under x the clock cycle when counting for the n-1 time, x) on the basis outside photon signal is carried out accumulated counts, its value is D1 (n, x), by the count value D2 (n of second counter with second counter under x-1 the clock cycle in the n time when counting in the counter, x-1) presumptive address of write memory, and from the presumptive address of the memory count value D2 under x+1 the clock cycle during with the n-1 time counting (n-1 x+1) is written into second counter; Under x+1 clock cycle, by described second counter at D2 (n-1, x+1) on the basis outside photon signal is carried out accumulated counts, its value is D2 (n, x+1), (n x) deposits presumptive address to memory with count results D1 by first counter, and from the presumptive address of the memory count value D1 under x+2 the clock cycle during with the n-1 time counting (n-1 x+2) is written into first counter;
S04, repeating step S03 are up to x=X, and wherein X is a positive integer;
S05, repeating step S02-04 are up to n=N, and wherein N is a positive integer;
S06 stops to accept outer triggering signal.
Preferably, accepting between the circuits for triggering, also comprising by comparator, carrying out signal identification according to predetermined threshold, and outer triggering signal and exterior light subsignal after circuits for triggering and counting unit provide identification.
By adopting single photon counting of the present invention system, its counting unit adopts ping-pong operation to carry out the counting of single photon, dead time is little, the counting efficiency height, described system can realize by the FPGA field programmable gate array, its hardware realizes having better flexibility and performance, in addition, described system can be connected with external system with usb bus by embedded chip, realizes high-speed data transmission, has better real-time property, in addition, in a preferred embodiment, also comprise digital to analog converter and comparator, for system provides effective outer triggering signal and exterior light subsignal, exclude the interference signal, thereby effectively improved the accuracy of counting.
Description of drawings
Fig. 1 shows the structured flowchart that the single photon counting system according to the first embodiment of the present invention is connected with external system;
Fig. 2 shows the structured flowchart according to the counting logical circuit of the first embodiment of the present invention;
Fig. 3 shows the workflow diagram according to the single photon counting system of first embodiment of the invention;
Fig. 4 shows the embedded chip firmware program workflow diagram according to first embodiment of the invention;
Fig. 5 shows the structured flowchart that is connected with external system according to the single photon counting system of second embodiment of the invention;
Fig. 6 shows the structured flowchart that is connected with external system according to the single photon counting system of third embodiment of the invention.
Below, the specific embodiment of the present invention is described with reference to the accompanying drawings, reference marker identical in the accompanying drawing is represented similar implication.
Embodiment
First embodiment
First embodiment is the laser radar visibility meter that is applied to a passage single photon signal, return laser beam is counted, variation tendency by counting is calculated visibility, this appliance requires is counted 1 passage single photon signal, count frequency requires to be 10MHz, timing is spaced apart 100ns, and storage is counted and required to be 1K, and the triggering frequency is 3KHz.
With reference to figure 1, Fig. 1 shows the structured flowchart that the single photon counting system of first embodiment of the invention is connected with external system, in embodiments of the present invention, single photon counting system 100 is connected with embedded system 200 by plate level bus, and be connected with external system by USB, external system is a computer 300 in the embodiment of the invention, this connected mode, its transmission speed height has improved the real-time of counting.Described single photon counting system 100 mainly comprises the counting logical circuit, can pass through FPGA (FieldProgrammable Gate Array, field programmable gate array) realizes, preferably, also comprise comparator 120 and digital to analog converter (DAC) 130, described digital to analog converter 130 receives the threshold value of external signal, outside signal packet is drawn together single photon signal and gate-control signal in the present embodiment, gate-control signal is an outer triggering signal, the single photon signal is the signal of required counting, and provide the threshold value of outer triggering signal and outside single photon signal to comparator 120, described comparator carries out signal identification according to described threshold value, and the signal that surpasses threshold value is a useful signal, eliminate the interference of noise signal like this, improved the accuracy of number system counting.
To introduce each functional module of counting logical circuit below in detail, with reference to figure 2, Fig. 2 shows the structured flowchart of the counting logical circuit of being realized by FPGA, and it comprises: latch 102, circuits for triggering 104, clock generation circuit 106, counting unit 108 and memory 120.
Circuits for triggering 104, described circuits for triggering 104 allow to receive from outer triggering signal, and transmit outer triggering signal to clock generation circuit 106, with flip-flop number.
Specifically, the synchronous method of gate-control signal and inner count signal comprises: gate-control signal is input to circuits for triggering 104, and circuits for triggering 104 are exported to clock generation circuit 106 with gate-control signal after receiving the order that begins to trigger.Pass through the counting clock of the edge triggering for generating one-period of gate-control signal by the decision of counting clock cycle parameter in the clock generation circuit 106,108 pairs of photon signals of this clock control counting unit are counted, and each rising edge clock counting once.
In addition, alternatively, also comprise synchronous circuit, be used for clock synchronization with exterior light subsignal and clock generation circuit, to enter into the single photon signal of counting unit and the phase place of counting clock is fixed by synchronous circuit, and avoid the counter-rotating of counter unusual, thereby improve the accuracy of counting.
Alternatively, also comprise phase-locked loop, be used to clock generation circuit and synchronous circuit that reference clock is provided, make all circuit synchronous workings.
More than to the counting logical circuit functional module done detailed description, the workflow to whole number system is described in detail below, with reference to figure 3, Fig. 3 shows the workflow diagram of the single photon counting system of first embodiment.
At step S301, computer writes to number system with the parameter that is provided with, in embodiments of the present invention, the parameter that is provided with comprises: triggering times is N, counting step X, counting clock period T, wherein N, X are positive integer, and the external signal threshold value, and the parameter of setting transmits via bus, by address decoding circuitry the address is translated into control signal, and the parameter on the data/address bus is latched by the latch module.
At step S302, computer sends and begins the counting order, and order reaches number system by bus.
At step S303, circuits for triggering are open, allow outer triggering signal to enter into number system, and the triggering signal after comparing by comparator and threshold value enters number system.
At step S304, wait for that triggering signal arrives.
At step S305, if n outer triggering signal arrives, then enter step S306, do not arrive, then continue to wait for triggering signal.
At step S306, it is the counting clock of T that clock generation circuit produces one-period.Circuits for triggering are started working with the edge triggering clock generation circuit of gate-control signal after receiving the order that begins to trigger, and producing one-period is the counting clock of T.
At step S307, under the counting clock periodic signal, count.Concrete steps comprise: under x counting clock periodic signal, count value D1 (n-1 by first counter of first counter under x the clock cycle when counting for the n-1 time, x) on the basis outside photon signal is carried out accumulated counts, its value is D1 (n, x), by the count value D2 (n of second counter with second counter under x-1 the clock cycle in the n time when counting in the counter, x-1) presumptive address of write memory, and from the presumptive address of the memory count value D2 under x+1 the clock cycle during with the n-1 time counting (n-1 x+1) is written into second counter; Under x+1 clock cycle, by described second counter at D2 (n-1, x+1) on the basis outside photon signal is carried out accumulated counts, its value is D2 (n, x+1), (n x) deposits presumptive address to memory with count results D1 by first counter, and from the presumptive address of the memory count value D1 under x+2 the clock cycle during with the n-1 time counting (n-1 x+2) is written into first counter;
This step adopts two counters to carry out the method for counting of ping-pong operation, to reduce the dead time, improves counting efficiency.
At step S308, repeating step S07 up to x=X, count down to X time then, stops counting.
At step S309, repeating step S306-S308 is up to n=N.
At step S310, the computer reading of data.
Above-mentioned method of counting, at the counting under each outer triggering signal is to carry out on the basis of the count results under the last triggering signal, is accumulated value, finish add up for N time after, the mark position height that collection is finished, wait for computer inquery and send reading order.The embodiment of the invention realizes USB high-speed bus transfer of data by embedded chip, the workflow of firmware program as shown in Figure 4, it is specific as follows: after order sends to the input block, order is resolved, if reading order, from the number system reading of data and deposit output buffer in, wait for that host computer takes data away.If data are just taken out in write command from the input block, be written in the number system by bus.
In first embodiment of the invention, FPGA selects EP1C12Q240C8 for use, and maximum operating frequency 275MHz provides 234Kb RAM, 10260 logical blocks, and 2 PLL and 173 available I/O.Embedded chip is selected CY7C68013 for use, supports USB2.0 high-speed transfer agreement, integrated enhanced 8051 kernels and programmable peripheral interface.Digital to analog converter is selected LTC1454 for use, two 12Bits serial inputs, and output area is 0 to 2.5V.Comparator is selected ADCMP600 for use, and the propagation delay time is 3.5ns, and rise and fall time is 2.2ns.
Second embodiment
Second embodiment is the atmosphere environment supervision laser radar that is applied to two passage single photon signals, and laser radar is by dusty gas and aerosol in the Difference Absorption method measurement atmosphere.This laser radar requires 2 passages are carried out single photon counting, and it is 20MHz that count frequency requires, and it is adjustable that timing is spaced apart 100ns/200ns, and storage is counted and required to be 4K, and the triggering frequency is 5kHz.
With reference to figure 5, Fig. 5 shows the structured flowchart that the single photon counting system of second embodiment of the invention is connected with external system, the same with first embodiment, the single photon counting system 100 of second embodiment is connected with embedded system 200 by plate level bus, and is connected with external system by USB.Each functional module that second embodiment counts logical circuit can be realized by FPGA, have and the first embodiment identical functions module, just it comprises two cover counting units, to realize counting to two single photon signals, its method of counting, workflow, chip type selecting and functional module are all identical with first embodiment, do not repeat them here.
The 3rd embodiment
The 3rd embodiment is the Doppler anemometry laser radar that is applied to 16 passage single photon signals, and this laser radar is by wind speed and wind field in the Doppler effect measurement atmosphere.Concrete mode is as follows: laser echo signal produces stripe pattern by the Fizeau interferometer, and when wind speed changes, Doppler effect will cause stripe pattern generation translation, can be finally inversed by wind speed according to this translation.In the laser radar system, the array of forming by 16 photomultipliers carries out record to stripe pattern, so this laser radar requires 16 passages are carried out single photon counting, count frequency requires to be 50MHz, it is adjustable that timing is spaced apart 100ns/500ns/1000ns, storage is counted and is required to be 1K, and the triggering frequency is 5kHz.
With reference to figure 6, Fig. 6 shows the structured flowchart that the single photon counting system of third embodiment of the invention is connected with external system, the same with first embodiment, the single photon counting system 100 of the 3rd embodiment is connected with embedded system 200 by plate level bus, and is connected with external system by USB.
Each functional module that the 3rd embodiment counts logical circuit can be realized by FPGA, have and the first embodiment identical functions module, just it comprises 16 cover counting units, to realize counting to 16 single photon signals, its method of counting, workflow and functional module are all identical with first embodiment, do not repeat them here.
In the present embodiment, FPGA selects EP3C55Q484C7 for use, and maximum operating frequency 437.5MHz provides 2340Kb RAM, 55856 logical blocks, and 4 PLL and 377 available I/O.Other chip type selecting is identical with first embodiment.
More than to single photon counting system and the workflow thereof of different embodiment, method of counting is described in detail, single photon counting of the present invention system, its counting unit adopts ping-pong operation to carry out the counting of single photon, dead time is little, the counting efficiency height, described system can realize by the FPGA field programmable gate array, its hardware realizes having better flexibility and performance, in addition, described system can be connected with external system with usb bus by embedded chip, realize high-speed data transmission, has better real-time property, in addition, in a preferred embodiment, also comprise digital to analog converter and comparator, for system provides effective outer triggering signal and exterior light subsignal, effectively improved the accuracy of counting.
Claims (14)
1. single photon counting system comprises:
Latch is used for receiving and the stored parameter setting;
Circuits for triggering are used to trigger counting operation N time, and described circuits for triggering allow to receive the triggering signal from the outside, and transmit outer triggering signal to clock generation circuit, with flip-flop number;
Clock generation circuit in response to the triggering signal of coming automatic triggering circuit, produces the clock signal in predetermined clock cycle;
Counting unit, when the n time triggering signal was effective, the photon signal that each the is received clock cycle counting of rattling was up to passing through X clock cycle, wherein 0≤n≤N;
Memory is used for the stored count unit in the described X count results of a clock cycle, as the n+1 time triggering signal when effective, and the basis of the table tennis of corresponding clock cycle counting, wherein said N, X are positive integer.
2. system according to claim 1, wherein said counting unit comprises first counter and second counter, described first counter and second counter replace counting according to the clock cycle, and count results are stored into the memory location that is used for storing the count results in a clock cycle on this in the memory in next clock cycle.
3. system according to claim 1, described first counter and second counter are obtaining the count results of corresponding clock cycle in the memory before the counting next time, and carry out accumulated counts on the radix of this count results.
4. system according to claim 1, wherein said counting unit also comprises address production electric circuit, for the access address is specified in the operation of counter.
5. system according to claim 1, wherein said counting unit also comprises toggle flipflop, by counting clock signal control, realizes the ping-pong operation of counter.
6. system according to claim 1 also comprises synchronous circuit, is used for the clock synchronization with exterior light subsignal and clock generation circuit.
7. to go to 1 described system according to right, also comprise phase-locked loop, be used to clock generation circuit and synchronous circuit that reference clock is provided.
8. system according to claim 1, also comprise digital to analog converter and comparator, described digital to analog converter is used for providing to comparator the threshold value of outer triggering signal and exterior light subsignal, described comparator is according to described threshold value, carry out signal identification, and outer triggering signal and exterior light subsignal after circuits for triggering and counting unit provide identification.
9. according to each described system in the claim 1 to 7, realize by the FPGA field programmable gate array.
10. according to each described system in the claim 1 to 8, described system is connected with external system with usb bus by embedded chip.
11. according to each described system in the claim 1-8 item, wherein said counting unit comprises and the corresponding many cover counting units of the quantity of exterior light subsignal.
12. a single-photon counting method, the single photon counting system comprises first counter and second counter, and described method comprises:
S01 receives outer triggering signal the n time by circuits for triggering, with flip-flop number, and 0≤n≤N wherein;
S02, clock generation circuit produce the clock signal with period T according to described triggering signal;
S03, under x counting clock periodic signal, count value D1 (n-1 by first counter of first counter under x the clock cycle when counting for the n-1 time, x) on the basis outside photon signal is carried out accumulated counts, its value is D1 (n, x), by the count value D2 (n of second counter with second counter under x-1 the clock cycle in the n time when counting in the counter, x-1) presumptive address of write memory, and from the presumptive address of the memory count value D2 under x+1 the clock cycle during with the n-1 time counting (n-1 x+1) is written into second counter; Under x+1 clock cycle, by described second counter at D2 (n-1, x+1) on the basis outside photon signal is carried out accumulated counts, its value is D2 (n, x+1), (n x) deposits presumptive address to memory with count results D1 by first counter, and from the presumptive address of the memory count value D1 under x+2 the clock cycle during with the n-1 time counting (n-1 x+2) is written into first counter;
S04 is provided with x=x+2, and repeating step S03 is up to x=X, and wherein X is a positive integer;
S05 is provided with n=n+1, and repeating step S02-04 is up to n=N, and wherein N is a positive integer;
S06 stops to accept outer triggering signal.
13. method according to claim 12 before step S01, also comprises: according to predetermined threshold, carry out signal identification by comparator, and outer triggering signal and exterior light subsignal after circuits for triggering and counting unit provide identification.
14. method according to claim 12 after step S06, also comprises from presumptive address and reads the count results under first to X counting clock signal the N time counting.
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| CN102254218A (en) * | 2011-07-02 | 2011-11-23 | 广西工学院 | Counter device composed of Advanced RISC Machine (ARM) and Field Programmable Gate Array (FPGA), and implementation method thereof |
| CN102339412A (en) * | 2011-06-23 | 2012-02-01 | 安徽量子通信技术有限公司 | Coincidence counting system for entangled photon detection experiment |
| WO2012100457A1 (en) * | 2011-01-25 | 2012-08-02 | 西安交通大学 | Single photon counting system for detecting weak light of dielectric |
| CN105378693A (en) * | 2013-07-09 | 2016-03-02 | 菲尼克斯电气公司 | Metering unit and control system with metering unit |
| CN106019350A (en) * | 2016-06-24 | 2016-10-12 | 成都理工大学 | Nuclear pulse signal acquisition device and system |
| CN108168418A (en) * | 2016-12-07 | 2018-06-15 | 株式会社三丰 | For being stored with the flip-flop number of the measuring apparatus of count value in a flash memory |
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| CN111766598A (en) * | 2020-09-01 | 2020-10-13 | 中国人民解放军国防科技大学 | Recovery method of single photon detection time-intensity information |
| CN112629683A (en) * | 2021-03-09 | 2021-04-09 | 成都成电光信科技股份有限公司 | Single photon counting device and method thereof |
| CN113029367A (en) * | 2021-03-19 | 2021-06-25 | 南京大学 | Single photon coincidence logarithm measurement method and device |
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| WO2012100457A1 (en) * | 2011-01-25 | 2012-08-02 | 西安交通大学 | Single photon counting system for detecting weak light of dielectric |
| CN102339412A (en) * | 2011-06-23 | 2012-02-01 | 安徽量子通信技术有限公司 | Coincidence counting system for entangled photon detection experiment |
| CN102339412B (en) * | 2011-06-23 | 2014-01-15 | 安徽量子通信技术有限公司 | Coincidence counting system for entangled photon detection experiment |
| CN102254218B (en) * | 2011-07-02 | 2014-02-26 | 广西工学院 | Counter device composed of Advanced RISC Machine (ARM) and Field Programmable Gate Array (FPGA), and implementation method thereof |
| CN102254218A (en) * | 2011-07-02 | 2011-11-23 | 广西工学院 | Counter device composed of Advanced RISC Machine (ARM) and Field Programmable Gate Array (FPGA), and implementation method thereof |
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| CN105378693A (en) * | 2013-07-09 | 2016-03-02 | 菲尼克斯电气公司 | Metering unit and control system with metering unit |
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| CN106019350A (en) * | 2016-06-24 | 2016-10-12 | 成都理工大学 | Nuclear pulse signal acquisition device and system |
| CN108168418A (en) * | 2016-12-07 | 2018-06-15 | 株式会社三丰 | For being stored with the flip-flop number of the measuring apparatus of count value in a flash memory |
| CN108173601A (en) * | 2017-12-26 | 2018-06-15 | 东莞信大融合创新研究院 | A kind of training symbol detection technique based on SPAD dead time effects |
| CN111766598A (en) * | 2020-09-01 | 2020-10-13 | 中国人民解放军国防科技大学 | Recovery method of single photon detection time-intensity information |
| CN111766598B (en) * | 2020-09-01 | 2020-11-24 | 中国人民解放军国防科技大学 | Recovery method of single photon detection time-intensity information |
| CN112629683A (en) * | 2021-03-09 | 2021-04-09 | 成都成电光信科技股份有限公司 | Single photon counting device and method thereof |
| CN113029367A (en) * | 2021-03-19 | 2021-06-25 | 南京大学 | Single photon coincidence logarithm measurement method and device |
| CN113029367B (en) * | 2021-03-19 | 2022-05-17 | 南京大学 | Single photon coincidence logarithm measurement method and device |
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