CN105676198B - A kind of echo impulse delay generation device for pulse radar test - Google Patents
A kind of echo impulse delay generation device for pulse radar test Download PDFInfo
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- CN105676198B CN105676198B CN201610196573.5A CN201610196573A CN105676198B CN 105676198 B CN105676198 B CN 105676198B CN 201610196573 A CN201610196573 A CN 201610196573A CN 105676198 B CN105676198 B CN 105676198B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
- G01S7/406—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder
- G01S7/4065—Means for monitoring or calibrating by simulation of echoes using internally generated reference signals, e.g. via delay line, via RF or IF signal injection or via integrated reference reflector or transponder involving a delay line
Abstract
The invention discloses a kind of echo impulse for pulse radar test to postpone generation device, creative to carry out the equivalent interpolation sampling of high speed by multichannel phase shifting clock pulse signals, and storage free of discontinuities is carried out with multichannel FIFO memory cell pulse signals；Meanwhile the method counted using interpolation realizes the high accuracy delay control output to input pulse signal under relatively low clock frequency, meets the needs that back end test equipment postpones precision to echo pulse signal.If basic clock signal frequency is fIN, M frequencys multiplication and the phase shift of N roads are carried out using phaselocked loop, then equivalent sampling speed brings up to MNfIN, the pulse data temporal resolution of samples storage improves MN times, therefore the control accuracy for postponing output brings up to 1/MNfIN.Traditional pulse delay signal method is compared to, the present invention can enter the high-precision control output of line-pulse signal fixed delay and variable delay, so as to realize the flexible simulation highly or apart from echo-signal.
Description
Technical field
The invention belongs to signal processing technology field, more specifically, be related to it is a kind of be used for pulse radar height or
Echo impulse delay generation device in range simulation test process.
Background technology
Radar is that one kind enters row distance (height) and the equipment of target signature detection and measurement using electromagnetic wave.Radar emission
Modulated signal produce echo after target reflecting surface, by being carried out to the time-frequency characteristics for receiving echo-signal at analysis
Reason, so as to obtain target reflecting surface relative to information such as orientation, distance and the associated change speed of transmitting equipment.
Radar is divided by its function, available for occasions such as survey height, early warning, search, warning, guidances；Drawn from working system
Point, primary radar and secondary radar can be divided into；Emission signal frequency covers millimeter wave always from metric wave；Modulated from transmission signal
Type division, radar can be divided into the continuous major class of waves and pulsed two.
For the radar of pulse (modulation) formula, its operation principle is by measuring the transmission between transmitting pulse and echo impulse
Time difference, further according to electromagnetic wave space spread speed, calculate the information such as relative distance and the target signature of target.Pulsed
Radar not only with more preferable anti-interference, and also has relative to continuous waves radar in terms of orientation and distance measurement
There is larger advantage.
The calculation formula of relative distance is：
D=c Δs t/2 (1)；
Wherein, D is the relative distance of radar and target, and c is electromagnetic wave in the spread speed in space, and Δ t is transmission signal
Moment t0With reception signal moment t1Time difference, i.e. Δ t=t1-t0。
Pulse radar is tested, it is necessary to be tracked to the pulse signal launched, produced according to test request
The echo impulse of fixed delay or variable delay, the echo impulse after delay is connected to tested radar receiving terminal, compares and prolongs
Slow setting value and the resolving value of tested radar, so as to judge whether the function of tested radar and index are normal.
Due to transmission speed c=299792458m/s of the electromagnetic wave in space, therefore under shorter distance, pulse is received and dispatched
Delay very little.Traditional test mode is mostly using devices such as the fibre delay line of regular length, sound table delay lines to transmitting
Pulse signal (decay and detection, compare and shaping) carry out delay forwarding, fixed range can only be simulated and postponed, test step
Rapid cumbersome, testing efficiency is low, and can not carry out the delay simulation in variable range or orientation.Another test mode is then to use
Target is hung the winged mode of high or real machine extension and carried out, although this mode more presses close to pulse radar real working condition, exists
Test platform builds the weak points such as inconvenience, test period length, testing cost height.Therefore, how to realize more fast, neatly
Echo impulse delay simulation and control, in pulse radar in outfield various functions and index test, have highly important
Engineering application value.
The content of the invention
It is an object of the invention to overcome in existing pulse radar test process, echo impulse delay generation technology is not
Foot, there is provided a kind of echo impulse delay generation device for pulse radar test, further to improve prolonging for echo impulse
Slow precision.
For achieving the above object, the present invention is used for the echo impulse delay generation device of pulse radar test, base
Built in FPGA, including：
Count delay module, length of delay is set for receiving, and carry out delay counter, when count value is with setting length of delay phase
Deng after, the reading enable signal for producing FIFO memory is opened；
Characterized in that, also include：
Frequency multiplication and phase shift block, using two-stage, reference clock signal is entered line frequency frequency multiplication by totally three PLL (phaselocked loop) for it
It is with phase shift processing：The first order is a PLL, for carrying out frequency multiplication to reference clock signal and being fanned out to, the Clock Multiplier Factor of setting
For M, two-way is set to be fanned out to clock signal, clock signal frequency MfIN, phase difference is 180 degree, wherein, fINOn the basis of clock believe
Number frequency；The second level is two PLL, and the two-way clock signal that the PLL of the first order is fanned out to (output) is respectively fed to the second level
Two PLL, two PLL are set to export N/2 roads clock signal, every road clock signal phase shift successively of each PLL outputs respectively
360/N degree, i.e., adjacent two-way clock signal phase difference is 360/N, and two such PLL exports N/2 roads clock signal group respectively
Altogether, the clock signal that there is same phase difference to be 360/N on N roads has been obtained；
FIFO (First Input First Output, FIFO) memory cell of N number of 1Bit bit wides, each
The read-write clock of FIFO memory unit respectively with frequency multiplication and phase shift block caused by N roads clock signal be connected, FIFO memory
Depth capacity S be：
S=2D/cTFIFO=Δ t/TFIFO； (2)
Wherein, D is relative distance, and unit is rice, TFIFOIt is FIFO memory cell read-write clock cycle i.e. 1/MfIN, cTFIFO
Represent electromagnetic wave in TFIFOThe distance of transmission in time, Δ t is time delay corresponding to relative distance D；
Data collection module, there is N number of input, and the output end with N number of FIFO memory cell is connected respectively, for will be right
The data of N number of FIFO memory output are collected, and obtain echo impulse delay output；
The relative distance D simulated as needed by host computer, time delay corresponding to setting, and send time delay pair
The setting length of delay answered is to count delay module；After count delay module receives setting length of delay, pass through asynchronous resetting control first
End processed empties the data in N number of cell fifo, then waits pulse signal input；Wherein, the pulse signal is：Pulsed thunder
Highpowerpulse modulated signal up to transmitting terminal output passes through the exomonental detection frame that is obtained after fixed attenuator, wave detector
Frame signal, then detection frame signals are compared the signal obtained after shaping and level conversion by comparator；The pulse
Signal is connected respectively to the data input pin and count delay module of N number of FIFO memory cell；
When first pulse signal rising edge arrives, count delay module opens writing for N number of FIFO memory cell simultaneously
Enabled control, the pulse signal of input are written in corresponding FIFO memory cell in the rising edge of N roads clock signal；
While enabled operation is write in unlatching, the counter in count delay module is started working；When counting down to setting
Time delay be opened after count value is equal to setting length of delay N number of FIFO memory cell reading it is enabled and data collection module is defeated
Go out enabled, now, the read-write of N number of FIFO memory cell is enabled, tidal data recovering output is enabled is all turned on；In this state
Under, the pulse signal of input is while N number of FIFO memory cell is continually respectively written, also according to FIFO
Principle is continuously read out from N number of FIFO memory cell, is then output to data collection module and is carried out OR operation, is returned
Wave impulse delay output, delay output pass through radio-frequency signal source, produce final echo-signal and be sent to connecing for radar equipment again
Receiving end, so as to complete the delay of height or distance simulation.
The object of the present invention is achieved like this.
The present invention is used for the echo impulse delay generation device of pulse radar test, is the high collection that make use of FPGA device
Cheng Du, the features such as senior engineer's working frequency and strong parallel processing capability, the creative multichannel phase shifting clock pulse signals that pass through are carried out
The equivalent interpolation sampling of high speed, storage free of discontinuities is carried out with multichannel FIFO memory cell pulse signals；Count delay module is to depositing
The mode that data control is read is stored up, during solving pulse radar function and index test, fixed and variable delay is returned
This demand of wave pulse signal simulation.
Meanwhile using multichannel phase shifting clock and multichannel FIFO memory, using the method that interpolation counts in relatively low clock frequency
The high accuracy delay control output to input pulse signal is realized under rate, meets back end test equipment to echo pulse signal
Postpone the needs of precision.If basic clock signal frequency is fIN, M frequencys multiplication and the phase shift of N roads are carried out using phaselocked loop, then equivalent sampling
Speed brings up to MNfIN, MN times of the temporal resolution raising of samples storage pulse data.Using count delay module, according to test
Delay is needed to read the pulse data being stored in FIFO.Because counting and FIFO read-writes clock frequency are similarly equivalent to
MNfIN, therefore the control accuracy for postponing output brings up to 1/MNfIN.It is compared to traditional pulse delay signal method, this hair
The bright high-precision control output that can enter line-pulse signal fixed delay and variable delay, so as to realize height or believe apart from echo
Number flexible simulation.The present invention has precision height, small volume, cost is low, control is flexible, convenient to be taken jointly with other measuring instruments
The characteristics of building test platform and Auto-Test System.
The present invention is solved in existing pulse radar test process, and echo impulse postpones the deficiency of generation technology, is utilized
Abundant interconnection resource, phaselocked loop (PLL) and memory cell inside field programmable gate array (FPGA) logical device, to defeated
The radar pulse signal entered is acquired storage, delay forwarding, to realize under the conditions of interior field testing, to pulse radar height
Degree or the simulation apart from echo-signal, carry out the test measurement of correlation function and index, meet equipment development, produce, test and
The needs of regular maintenance guarantee.
Brief description of the drawings
Fig. 1 is the concrete application schematic diagram for the echo impulse delay generation device that the present invention is used for pulse radar test；
Fig. 2 is a kind of embodiment original of echo impulse delay generation device that the present invention is used for pulse radar test
Manage block diagram；
Fig. 3 is input pulse signal of the present invention, the sequential relationship of echo impulse postpones signal and multichannel phase shift clock signal
Schematic diagram.
Embodiment
The embodiment of the present invention is described below in conjunction with the accompanying drawings, so as to those skilled in the art preferably
Understand the present invention.Requiring particular attention is that in the following description, when known function and the detailed description of design perhaps
When can desalinate the main contents of the present invention, these descriptions will be ignored herein.
Fig. 1 is the concrete application schematic diagram for the echo impulse delay generation device that the present invention is used for pulse radar test.
In the present embodiment, as shown in figure 1, the highpowerpulse modulated signal of pulse radar transmitting terminal output passes through admittedly
Determine the exomonental detection frame signals obtained after attenuator decay, detector, then detection frame signals are passed through into ratio
The pulse signal P obtained after shaping and level conversion is compared compared with deviceIN, pulse signal PINIt is input to echo impulse delay production
Generating apparatus obtains echo impulse delay output, and delay output passes through radio-frequency signal source, produces final echo-signal and be sent to again
The receiving terminal of radar equipment, so as to complete the delay of height or distance simulation.
Fig. 2 is a kind of embodiment original of echo impulse delay generation device that the present invention is used for pulse radar test
Manage block diagram.
In the present embodiment, as shown in Fig. 2 being input to FPGA high-precision external timing signal i.e. reference clock fINFirst
The frequency multiplication and the first order PLL of phase shift block 1 entered in FPGA, the first order are a PLL, set the PLL and work in frequency multiplication
Pattern, it is M times to set Clock Multiplier Factor, is fanned out to the two-way homogenous frequency signal of half period phase shift.So, after by the PLL process of frequency multiplication
Clock signal frequency be MfIN, two-way clock skew is 180 degree.The two-way clock signal that first order PLL is exported is sent respectively
Enter two PLL of the second level, set two PLL to export N/2 roads clock signal, i.e. the 1st PLL outputs the 0th, 1 ... N/2 respectively
Road clock, the 2nd PLL export N/2+1, N/2+2 ... N roads clock.Adjacent two-way clock signal phase difference is 360/N degree,
This results in N roads clock signal, the delay of adjacent clock signal is td=1/MNfIN, the sequential relationship of N roads clock signal is such as
Shown in Fig. 3.
The FIFO memory cell 2 of N number of 1Bit bit wides is designed in FPGA, the N roads clock letter that will be obtained after frequency multiplication and phase shift
Number respectively as N number of FIFO memory cell 2 read-write clock fM1~fMN.In order to avoid FIFO memory cell write-in spilling causes
The pulse signal of storage is lost, in specific implementation process, FIFO storage depth S generally according to transmitting-receiving time difference Δ t most
Big value or radar and the relative distance D of target maximum, according to formula S=2D/cTFIFO=Δ t/TFIFOSet after calculating.
The pulse signal P obtained through overdamping and detection and after comparing shaping and level conversionINFPGA is sent into, is connected simultaneously
It is connected to the data input pin and count delay module of N number of FIFO memory cell 2.Count delay module 4 controls N number of FIFO storages single
The reading of member 2 enables, writes enabled and asynchronous resetting (in order that simplified form, is not drawn into).
When starting test, the relative distance D that is simulated as needed by host computer, time delay corresponding to setting, concurrently
Setting length of delay corresponding to time delay is sent to count delay module 4；After count delay module 4 receives setting length of delay, first
N number of FIFO memory cell 2 is all emptied by asynchronous resetting (not shown).When first pulse signal rising edge arrives
Afterwards, count delay module 4 opens the enabled control of writing of N number of FIFO memory cell 2 simultaneously, and the pulse signal of input is in N roads clock
The rising edge of signal is written in corresponding FIFO memory cell.From the figure 3, it may be seen that during every read-write of FIFO memory cell all the way
Clock frequency fMi=MfIN, (i=0,1,2 ... N), because the rising edge of the uniform phase shifting clock in N roads is in a MfINIn cycle at equal intervals
Distribution, therefore, multipath clock signal time sharing sampling in this FPGA pieces, the process of multiple memory cell storage are equivalent to fs=
MNfINFrequency carry out samples storage, under the conditions of realizing high accuracy by the method for " trading space for time " in FPGA device
The flexible simulation of echo impulse delay.Further, since pulse signal edge arrival time obeys uniformly within a sampling period
Distribution, therefore, the time error E of pulse signal rising edge samplingrWith the time error E of trailing edge samplingfIt is also reduced to 1/MN.
While input pulse signal rising edge triggers N number of FIFO memory cell 2 and writes enabled operation, count delay module
In counter start working, when count down to setting time delay i.e. count value be equal to setting length of delay after, open N number of FIFO
The reading of memory cell 2 is enabled and data collection module output is enabled.Now, the pulse being stored in N number of FIFO memory unit 2
Signal sequentially reading by FIFO in the presence of clock is read and write, it is output to data collection module 3 and carries out logical "or" behaviour
Make, the single channel that data collection module 3 realizes multipath input data merges output.N number of FIFO memory cell 2 is same after the completion of counting
When the process reading and writing and export, be continued until that host computer sends new setting length of delay again.
To sum up, by being stored to input pulse signal time sharing sampling, count delay is read the present invention, is collected merging and is exported this
Series of steps, realize the generation of echo impulse delay of the pulse radar highly or needed for range simulation test.
In the present embodiment, the high precision reference clock frequency f of selectionIN=10MHz, according to compiling from FPGA device
Journey resource characteristic, set first order PLL Clock Multiplier Factor M=25, setting two panels second level PLL phase shift way N=8.So,
It is identical 8 tunnel frequencies are obtained, the parallel clock signal that 45 degree of phase difference.In FPGA device, clock signal cabling is low latency
Copper wire, in the case where not considering PLL device self delay and signal transmission delay, equivalent clock signal fs=MNfIN=
2000MHz.Therefore, in whole pulse daley processing procedure, it is from signal input part to the temporal resolution for collecting output end
1/fsThe buffer path precision of=0.5ns, respective heights or distance is c/fs=0.15m.In the engineer applied of reality, consider
The other interference introduced into signal transmission and processing procedure and error, delay precision can be less than 0.3m.8 FIFO of setting are deposited
Storage unit, storage depth S=65536, it can at most store 32768ns pulse data.Retaining the feelings of a part of design capacity
Under condition, by formula S=2D/cTFIFO=Δ t/TFIFOThe maximum height or distance D >=9000m of delay simulation, the present invention can be drawn
It disclosure satisfy that the requirement of pulse radar measurement accuracy and measurement range.
The present invention takes full advantage of the abundant all kinds of resources of the present age advanced programmable gate array device inside and set
Meter, realize the signal delay processing during pulse radar and similar principles testing for electrical equipment.In test process,
Operating personnel can utilize FPGA device and this method to build test platform jointly with Other Instruments equipment, can be by host computer to prolonging
Slow parameter is configured.The present invention have the advantages that small volume, cost are low, simple to operate, easy to use, can reduce test into
This, improves testing efficiency.
Although the illustrative embodiment of the present invention is described above, in order to the technology of the art
Personnel understand the present invention, it should be apparent that the invention is not restricted to the scope of embodiment, to the common skill of the art
For art personnel, if various change in the spirit and scope of the present invention that appended claim limits and determines, these
Change is it will be apparent that all utilize the innovation and creation of present inventive concept in the row of protection.
Claims (2)
1. a kind of echo impulse delay generation device for pulse radar test, built based on FPGA, including：
Count delay module, length of delay is set for receiving, and carry out delay counter, when count value is equal with setting length of delay
Afterwards, the reading enable signal for producing FIFO memory is opened；
Characterized in that, also include：
Frequency multiplication and phase shift block, using two-stage, reference clock signal is entered line frequency frequency multiplication and shifting by totally three PLL (phaselocked loop) for it
Phase processor is：The first order is a PLL, and for carrying out frequency multiplication to reference clock signal and being fanned out to, the Clock Multiplier Factor of setting is M,
Two-way is set to be fanned out to clock signal, clock signal frequency MfIN, phase difference is 180 degree, wherein, fINOn the basis of clock signal
Frequency；The second level is two PLL, and the two-way clock signal that the PLL of the first order is fanned out to is respectively fed to two PLL of the second level, if
Put two PLL and export N/2 roads clock signal respectively, every road clock signals of each PLL outputs phase shift 360/N degree, i.e. phase successively
Adjacent two-way clock signal phase difference is 360/N, and two such PLL exports N/2 roads clock signal and combined, obtains respectively
N roads have the clock signal that same phase difference is 360/N；
FIFO (First Input First Output, FIFO) memory cell of N number of 1Bit bit wides, each FIFO are deposited
The read-write clock of storage unit respectively with frequency multiplication and phase shift block caused by N roads clock signal be connected, the maximum of FIFO memory
Depth S is：
S=2D/cTFIFO=Δ t/TFIFO；
Wherein, D is relative distance, and unit is rice, TFIFOIt is FIFO memory cell read-write clock cycle i.e. 1/MfIN, cTFIFORepresent
Electromagnetic wave is in TFIFOThe distance of transmission in time, Δ t is time delay corresponding to relative distance D；
Data collection module, there is N number of input, and the output end with N number of FIFO memory cell is connected respectively, for N number of
The data of FIFO memory output are collected, and obtain echo impulse delay output；
The relative distance D simulated as needed by host computer, time delay corresponding to setting, and send corresponding to time delay
Length of delay is set to count delay module；After count delay module receives setting length of delay, pass through asynchronous resetting control terminal first
The data in N number of cell fifo are emptied, then wait pulse signal input；Wherein, the pulse signal is：Pulse radar is sent out
The highpowerpulse modulated signal for penetrating end output is believed by the exomonental detection framework obtained after fixed attenuator, wave detector
Number, then detection frame signals are compared the signal obtained after shaping and level conversion by comparator；The pulse signal
It is connected respectively to the data input pin and count delay module of N number of FIFO memory cell；
When first pulse signal rising edge arrives, it is enabled that count delay module opens writing for N number of FIFO memory cell simultaneously
Control, the pulse signal of input are written in corresponding FIFO memory cell in the rising edge of N roads clock signal；
While enabled operation is write in unlatching, the counter in count delay module is started working；When the delay for counting down to setting
Time is that enabled exported with data collection module of reading that N number of FIFO memory cell is opened after count value is equal to setting length of delay makes
Can, now, the read-write of N number of FIFO memory cell is enabled, tidal data recovering output is enabled is all turned on；In this state, it is defeated
The pulse signal entered is while N number of FIFO memory cell is continually respectively written, also according to the principle of FIFO
Continuously read out from N number of FIFO memory cell, be then output to data collection module and carry out OR operation, obtain echo arteries and veins
Punching delay output, delay output pass through radio-frequency signal source, produce the receiving terminal that final echo-signal is sent to radar equipment again,
So as to complete the delay of height or distance simulation.
2. echo impulse according to claim 1 postpones generation device, it is characterised in that the frequency of the reference clock signal
Rate fIN=10MHz, according to the programmable resource feature from FPGA device, set first order PLL Clock Multiplier Factor M=25, setting
Two panels second level PLL phase shift way N=8, it is identical to obtain 8 tunnel frequencies, the clock signal that 45 degree of phase difference.
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| CN106027165B (en) * | 2016-07-06 | 2017-09-15 | 华南理工大学 | OOK pulsed signals device, method and communicator |
| CN108665922B (en) * | 2018-04-24 | 2021-09-24 | 电子科技大学 | Variable bidirectional digital delay method applied to radar simulation |
| CN108872956A (en) * | 2018-07-17 | 2018-11-23 | 中国人民解放军63895部队 | A kind of adjustable radar calibration source of delay distance |
| CN108647173B (en) * | 2018-08-01 | 2023-08-01 | 中国电子科技集团公司第三十四研究所 | Synchronous trigger pulse signal regeneration device and operation method thereof |
| CN109459733B (en) * | 2018-10-26 | 2021-01-22 | 中电科仪器仪表有限公司 | Anti-collision radar target speed simulation device, system and method based on phase modulation mode |
| CN109490866B (en) * | 2018-12-18 | 2021-04-30 | 北京无线电计量测试研究所 | Impulse radar system, signal transmitting, receiving and transmitting-receiving method |
| US20220120856A1 (en) * | 2018-12-28 | 2022-04-21 | Dspace Digital Signal Processing And Control Engineering Gmbh | Signal Delay Device and Simulator Device for Simulating Spatial Distances in Distance Measuring Devices Based on Electromagnetic Waves |
| CN109975772B (en) * | 2018-12-28 | 2021-11-05 | 北京航天测控技术有限公司 | Multi-system radar interference performance detection system |
| CN110515890B (en) * | 2019-08-02 | 2023-08-01 | 北京智行者科技股份有限公司 | Data analysis method and system of multiprocessor system-on-chip MPSOC |
| CN111697967B (en) * | 2020-06-29 | 2023-04-18 | 电子科技大学 | Self-adaptive digital clock taming system |
| CN111831606B (en) * | 2020-07-17 | 2023-03-31 | 电子科技大学 | FPGA-based data packet accurate delay method and system |
| CN115622541A (en) * | 2021-07-16 | 2023-01-17 | 长鑫存储技术有限公司 | Staggered signal generating circuit and integrated chip |
| JP7130218B1 (en) * | 2022-03-09 | 2022-09-05 | アズールテスト株式会社 | time to digital converter |
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| CN101799705B (en) * | 2010-03-23 | 2012-03-21 | 电子科技大学 | High-speed DDS signal generator |
| US8368574B1 (en) * | 2010-04-26 | 2013-02-05 | Omniphase Research Laboroatories, Inc. | Dynamic range ADC's |
| CN103354448B (en) * | 2013-06-18 | 2015-09-30 | 西安电子科技大学 | Based on the high resolution time interval generation system of FPGA |
| CN104020461B (en) * | 2014-05-06 | 2017-01-04 | 南京大学 | Light path antidote in a kind of laser based on TDC algorithm |
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