CN105446934B - A kind of moving-target and CFAR detection system based on multi-core DSP - Google Patents

Abstract

The present invention proposes a kind of moving-target based on multi-core DSP and CFAR detection system.The multi-core DSP includes a main core and more than two from core, more than two from core, individually open up one and is interrupted from core from core for response external as data receiver and receive radar signal data from FPGA by high-speed interface；Other processing for being used for radar signal data from core as data processing from core；Data receiver opens up two storage regions in external DDR from core and opens up two storage regions for storing the radar signal data received in oneself core from core for storing the radar signal data received, each data processing.The present invention solves the problems such as existing computation complexity height, operation time, data difficult communication when single-chip framework and multi-DSP Combined Treatment, has many advantages, such as that real-time is good, simple in structure, communication efficiency is high, processing capacity is strong.

Description

A moving target and constant false alarm detection system based on multi-core DSP

technical field

The invention belongs to the technical field of radar signal processing, in particular to a multi-core DSP-based moving target and constant false alarm detection system.

Background technique

With the rapid development of radar technology and digital signal processing chips represented by FPGA and DSP, radar signal processing technology has also been developed rapidly. This is not only reflected in the flexible and complex radar signal form and radar signal processing algorithm, but also in the use of high-performance digital signal processing devices and the emergence of various signal processing architectures.

Now a typical radar signal processor generally adopts a single DSP signal processing platform, based solely on FPGA or FPGA+DSP architecture. In the patent CN101561501A, a DSP-based radar target tracking recognizer is introduced, which has the advantage of not needing to use additional dedicated chips, which is conducive to reducing production costs. However, when the underlying signal preprocessing algorithm processes a large amount of data, but the operation structure is relatively simple, and the processing speed is high, the single DSP architecture obviously loses its advantage. Now the most commonly used structure is the DSP+FPGA structure, which has the advantages of two processors, taking into account speed and flexibility, and can be applied in different radar signal processing systems, and has strong versatility. In the article "Realization and Application of a Radar General Signal Processing System", a signal processing architecture based on one FPGA (EP2S60F1020) plus four DSPs (TS201) is introduced. This architecture has good versatility, strong processing capability, and data communication Advantages of high speed. However, this signal processing structure has disadvantages such as a large number of chips used, complex communication between chips, and difficulty in PCB layout and wiring.

Contents of the invention

The purpose of the present invention is to provide a multi-core DSP-based moving target and constant false alarm detection system, which solves the problems of high computational complexity, time-consuming calculation, and difficult data communication that exist in single-chip architecture and multi-chip DSP joint processing. It has the advantages of good real-time performance, simple structure, high communication efficiency, and strong processing ability.

In order to solve the above technical problems, the present invention provides a multi-core DSP-based moving target and constant false alarm detection system, wherein the multi-core DSP includes a master core and more than two slave cores, wherein:

The main core is responsible for the process control of the system processing radar signals, signal transmission, data transfer and information generation of tracking targets;

Among more than two slave cores, one slave core is separately opened as a data receiving slave core, and the data receiving slave core is used to respond to external interrupts and receive radar signal data from the FPGA through a high-speed interface; other slave cores are used as data processing slave cores, data Processing slave cores for the processing of radar signal data;

The data receiving slave core opens up two storage areas in the external DDR for storing the received radar signal data, and each data processing slave core opens up two storage areas in its own core for storing the received radar signal data.

Compared with the prior art, the present invention has significant advantages in that: (1) separately open up a core to respond to frequent GPIO interrupts and receive data from the outside, thereby improving the execution efficiency of the CPU; Bus access, reducing the additional overhead caused by DDR bus access conflicts; (3) Inter-core communication uses technologies such as flag bits, IPC interrupts, and DMA data transfer at the same time to ensure the reliability and speed of multi-core communication; (4) The slave core data storage adopts a ping-pong structure, which reduces the data waiting time.

Description of drawings

Fig. 1 is a working flow diagram of the main core in the present invention.

Fig. 2 is a working flow diagram of data receiving slave core in the present invention.

Fig. 3 is a working flowchart of the signal processing slave core in the present invention.

Detailed ways

The present invention is based on the moving target detection (MTD) of multi-core DSP and the constant false alarm detection (CFAR) system, comprises a master core and more than two slave cores in the described multi-core DSP, wherein:

The main core is responsible for the process control, signal transmission, data transfer and tracking target information generation of the system processing radar signals. The tracking target information includes distance, speed and other information;

Among more than two slave cores, one slave core is dedicated to respond to external interrupts and receive radar signal data from the FPGA through the high-speed interface (SRIO), that is, a separate slave core is opened as a data receiving slave core; other slave cores use For the processing of radar signal data, that is, to perform moving target detection and constant false alarm detection on tracking targets in radar signal data, that is, other slave cores are used as signal processing slave cores;

The data receiving slave core has opened up two storage areas in the external DDR (Double Rate Synchronous Dynamic Random Access Memory), and all the signal processing slave cores have opened up two storage areas in its own core, including the first storage area and the second storage area , to realize ping-pong structure storage.

Example

Select seven cores in the multi-core DSP to build the multi-core DSP-based moving target and constant false alarm detection system of the present invention, wherein it is determined that core 0 is the main core, and cores 1 to 5 are used as signal processing slave cores for processing radar signal data, which are developed separately Core 6 acts as a data receiving slave core in response to an external interrupt and receives radar signal data.

In conjunction with Fig. 1, the process of using the present invention to carry out moving target detection and constant false alarm detection to tracking targets in radar signal data is as follows:

The first step is to initialize the master core and slave core. The initialization of the main core core 0 includes configurations such as DSP system clock, DDR (Double Rate Synchronous Dynamic Random Access Memory), IPC (inter-core communication) interruption; the initialization of core 1 to core 5 includes initial value assignment of the inter-core communication flag bits; 6 initialization includes SRIO initialization configuration, GPIO (general purpose I/O port) interrupt configuration. After the initialization of each slave core of core 1 to core 6 is completed, the corresponding flag bit is pulled high, and the core 0 detects that the flag bit of each slave core initialization of core 1 to core 6 is pulled high and then enters the normal working mode.

In the second step, each time the FPGA completes a wave of radar signal data reception, it sends a GPIO rising edge interrupt signal to the data reception from core 6, and every time the core 6 receives an interrupt signal, it performs an SRIO read in the interrupt service function Operation, read radar signal data and store in external DDR.

The method for core 6 to read and store radar signal data is as follows: at the beginning, core 6 has been judging whether to receive an external interrupt signal from FPGA, and when core 6 receives the first interrupt signal, it responds to the external interrupt from FPGA, And read data from the outside through the SRIO interface. The core 6 judges whether to store the read data in the first storage area or the second storage area according to the parity of the times of receiving data currently. For example, the first wave of radar signal data read is stored in the first storage area of the external DDR. When it is judged that the wave of radar signal data is stored, its flag is pulled high, but at this time the core 6 does not stop receiving interrupt data. Continue to read the next wave of radar signal data and store it in the second storage area in the external DDR. Such a cycle realizes the storage of the ping-pong structure. The amount of radar signal data read by core 6 for each wave needs to be negotiated according to the reading rate and the storage resources on the FPGA side. The workflow of receiving data from the core 6 is shown in FIG. 2 .

The third step, in the process of step two, when the main core core 0 detects that the flag bit of core 6 is pulled high, it starts to perform DMA (direct data storage) data transfer, that is, core 0 stores core 6 in the external DDR The radar signal data is sequentially moved to the core storage space of each data processing slave core from core 1 to core 5. The specific process is: core 0 first gives DMA radar signal data to the first storage area in the core storage space of core 1 to core 5, and then processes each data from the second storage area DMA radar signal in the core storage space of the core The data realizes the ping-pong structure operation. After the main core core 0 starts to move the radar signal data, it has been waiting for the IPC interrupt generated by each core from core 1 to core 5 after the data processing is completed. When the main core core 0 receives the IPC interrupt, it determines which core the IPC interrupt comes from from core 1 to core 5, and DMAs the next wave of data to the core for radar data processing. When the master core 0 detects that all the data has been processed by the slave core, it determines the target distance, speed and other information according to the results returned by each signal processing slave core. The working flow chart of the main core core 0 is shown in Figure 1.

Considering that the core storage space resources of core 1 to core 5 are limited, and are divided into two storage areas for ping-pong structure storage, when a wave of data is large, it is impossible to DMA each wave of data to each data at one time Processing slave cores; at the same time, considering that core 1 to core 5 are doing target detection and constant false alarm detection, each distance unit is independent, therefore, when core 0 processes slave core DMA data for data, it uses distance Data is moved in units of units. In this embodiment, core 0 only DMAs the data of 3 distance units from the data processing slave core each time, and the data processing slave core performs moving target detection and constant false alarm detection processing on the data of the 3 distance units. The main core core 0 is interrupted by an IPC (inter-core communication), requiring core 0 to continue DMA data of another 3 distance units from the DDR. This loops until all the data is DMAed from the external DDR to core 1 to core 5.

In the fourth step, the workflow of the data processing slave core is shown in Figure 3. After each data processing of core 1 to core 5 receives the data from the main core core 0DMA from the core, it performs moving target detection and constant false alarm detection processing. The constant false alarm detection process adopts unit average constant false alarm, and one protection unit is taken on the left and right sides of the point to be detected, and then the left side of the taken protection unit on the left side and the right side of the taken right side protection unit are taken. Measure a number of points for accumulation (the number of points taken is related to the selected false alarm probability), generate a detection threshold and compare it with the signal, keep the value exceeding the threshold, set the points less than the threshold to 0, and process each signal from core 1 to core 5 The slave core returns the detected maximum value of the target amplitude and the corresponding position information to the agreed shared storage space. If you know the velocity information of the radar target last time, since the constant false alarm of the velocity dimension is used, the detection range of the velocity unit constant false alarm can be appropriately reduced according to the last velocity information.

In the fifth step, the main core core 0 divides the data in units of distance units, then the total number of distance units can be obtained, and then the number of distance units of the data that each slave core needs to process from core 1 to core 5 is allocated to core 1 From core 5 to each slave core, you can further know the number of DMA times that each slave core from core 1 to core 5 needs to complete during the issuance process. When the number of DMA data from the main core core 0 to the 5 signal processing slave cores reaches the corresponding DMA times of each core, the data transfer work of the main core core 0 has been completed at this time, and the flag is pulled high after the processing of the 5 slave cores is completed. .

After the data processing slave core has processed all the data, the respective processing results are stored in the designated shared storage space in the order of core 1 to core 5, and the respective radar signal processing completion flags are pulled high, the main core After core 0 detects that the flag bits of the five data processing slave cores are all pulled high, it reads the processing results of each core from the shared storage space, and generates tracking target information, including target distance, speed and other information.

In order to illustrate the present invention's advantage in computing speed, use the inventive method, DSP selects the high-performance 8 core DSP of TMS320C6678 that the model of TI Company is selected for use by DSP, the data is passed to DSP by the FPGA of XC7K325T model of XILINX Company through SRIO, and distance unit gets 59 Each interrupt receives 59*32*2*4=15014 data, 256 interrupts form a CPI data packet for processing, and the total data volume is 59*8192*8. If 59 distance units are allocated to core 1 to core 5, each core from core 1 to core 4 will get 12 distance unit data, and core 5 will get 11 distance unit data. If DMA is 3 distance units each time, the core 1 to core 5 all need DMA data 4 times. When using the method of the present invention to process, it can be seen from the CLOCK timing tool in TI's CCS software that only about 5.45ms is needed. The present invention also uses only one core for single-core processing under the above-mentioned experimental environment, and it can be seen from the CLOCK that the processing time is about 28.67ms. By comparison, the present invention improves the computing time by more than 5 times compared with that of single-core, and the saved time mainly comes from the reading of frequently interrupted data and the realization of multi-core algorithms.

Claims (6)

1. a kind of moving-target and CFAR detection system based on multi-core DSP, which is characterized in that the multi-core DSP includes one A main core and more than two from core, wherein：

Main core is responsible for the process control of system processing radar signal, signal transmits, the information life of data-moving and tracking target At；

More than two from core, individually open up one from core as data receiver from core, data receiver is from core for responding External interrupt simultaneously receives radar signal data by high-speed interface from FPGA；It is other from core as data processing at core, data Manage the processing that radar signal data are used for from core；

Data receiver opens up two storage regions for storing the radar signal data received, per number from core in external DDR Radar signal data of two storage regions for storing reception are opened up in oneself core from core according to processing；

It is to the process of the progress moving-target detection of tracking target and CFAR detection in radar signal data using the system：

Step 1 is initialized to main core and from core, and main core initialization includes dsp system clock, DDR, IPC interruption configuration； Data processing includes that intercore communication flag bit assigns initial value from core initialization；Data receiver includes that SRIO initialization is matched from core initialization It sets, GPIO interrupts configuration；All corresponding flag bit is drawn high after core initialization completion；When main core detect all from core at the beginning of The flag bit that beginningization is completed enters normal mode of operation after drawing high；

Step 2 after FPGA often completes a wave radar signal data receiver, is given data receiver to send a GPIO from core and is risen Along interrupt signal, data receiver just carries out a SRIO reading behaviour after often receiving an interrupt signal from core in interrupting service function Make, read radar signal data and is stored in external DDR；

Step 3, during carrying out step 2, after main core detects that data receiver is drawn high from the flag bit of core, main core In such a way that DMA data is moved by the radar signal data that data receiver is stored in from core in its external DDR move successively to Core memory space of each data processing from core；

Step 4, each data processing carry out after the data that core receives that main core is transmitted in a manner of direct memory access Moving-target detects and CFAR detection processing, and by handling result back to the shared memory space of agreement, then by respective thunder The flag bit completed up to signal processing is drawn high；

Step 5, main core detect each data processing after the flag bit of core is drawn high, from the shared memory space of agreement Handling result of each data processing from core is read, the information for line trace target of going forward side by side generates.

2. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 2 In, after data receiver receives first external interrupt signal from FPGA from core, the external interrupt is responded, and pass through SRIO interfaces read data from outside；The first wave radar signal data of reading are first stored in external DDR by data receiver from core In the first storage region, its flag bit drawn high after the wave radar signal data store, but do not stop receiving and interrupt Data continue to read next wave radar signal data and store to the second storage region in external DDR.

3. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 3 In, main core is first transmitted from the first storage region of the core memory space of core in a manner of direct memory access to each data processing Then radar signal data give each data processing to be visited from the second storage region of the core memory space of core directly to store again The mode of asking transmits radar signal data；Main core start just to wait for always after moving radar signal data each data processing from Core is completed the IPC generated later in data processing and is interrupted；Main core one receives one of data processing after the IPC of core interruptions, Just by next wave number, direct memory access mode is transferred to the data processing from core according to this.

4. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 3 In, main core carries out data when to data processing from core transmission data in a manner of direct memory access as unit of range cell It moves.

5. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 4 In, CFAR detection processing uses unit average constant false alarm, each side takes a protection location in measuring point to be checked, then in institute If the right side of the left survey of the protection location in the left side taken and the protection location on the right side taken measures to do and accumulate, inspection is generated It surveys after thresholding compared with radar signal, is more than the value reservation of thresholding, the points less than thresholding are set to 0.

6. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 5 In, main core according to it in a manner of direct memory access transmits data to each data processing from the number of core to judge data-moving Whether work is completed.