CN105446934B - A kind of moving-target and CFAR detection system based on multi-core DSP - Google Patents
A kind of moving-target and CFAR detection system based on multi-core DSP Download PDFInfo
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Abstract
The present invention proposes a kind of moving-target based on multi-core DSP and CFAR detection system.The multi-core DSP includes a main core and more than two from core, more than two from core, individually open up one and is interrupted from core from core for response external as data receiver and receive radar signal data from FPGA by high-speed interface；Other processing for being used for radar signal data from core as data processing from core；Data receiver opens up two storage regions in external DDR from core and opens up two storage regions for storing the radar signal data received in oneself core from core for storing the radar signal data received, each data processing.The present invention solves the problems such as existing computation complexity height, operation time, data difficult communication when single-chip framework and multi-DSP Combined Treatment, has many advantages, such as that real-time is good, simple in structure, communication efficiency is high, processing capacity is strong.
Description
Technical field
The invention belongs to Radar Signal Processing Technology fields, specifically relate to a kind of moving-target and constant false alarm based on multi-core DSP
Detecting system.
Background technology
Along with Radar Technology and using FPGA and DSP as the fast development of the digital signal processing chip of representative, radar
Signal processing technology is also developed rapidly.This is not only embodied at flexible, complicated radar signal form and radar signal
Adjustment method is also embodied in the appearance of the use and multi-signal processing framework of high-performance digital signal processor part.
Now typical radar signal processor generally using list DSP signal processing platforms, be based purely on FPGA or
FPGA+DSP frameworks.A kind of radar target tracking recognizer based on DSP, advantage are described in patent CN101561501A
It is and without in addition using special chip, advantageously reduces production cost.But it encounters at the Signal Pretreatment algorithm of bottom
When it is big to manage data volume, but the situation that operating structure is relatively easy, and requiring high situation to processing speed, the framework of single DSP is bright
It is aobvious not have advantage.Now most common is DSP+FPGA structures, tool the advantages of there are two types of processors, takes into account speed and flexibly
Property, and can apply in different Radar Signal Processing Systems, there is very strong versatility to exist《Electronics technology》's《A kind of thunder
Up to the realization and application of general signal processing system》In one text, describes one kind and added based on a piece of FPGA (EP2S60F1020)
The signal processing framework of four DSP (TS201), it is excellent which has that versatility is good, processing capacity is strong, data communication rates are high etc.
Point.But there is the signal processing structure chip to be communicated complicated, PCB placement-and-routings difficulty is big etc. between more, chip using number
Disadvantage.
Invention content
The purpose of the present invention is to provide a kind of moving-target based on multi-core DSP and CFAR detection systems, solve list
When chip architecture and multi-DSP Combined Treatment the problems such as existing computation complexity height, operation time, data difficult communication,
Have many advantages, such as that real-time is good, simple in structure, communication efficiency is high, processing capacity is strong.
In order to solve the above technical problem, the present invention provides a kind of moving-target based on multi-core DSP and CFAR detection systems
System, the multi-core DSP include a main core and more than two from core, wherein：
Main core is responsible for the process control of system processing radar signal, signal transmits, the letter of data-moving and tracking target
Breath generates；
More than two from core, individually open up one from core as data receiver from core, data receiver is used for from core
Response external interrupts and receives radar signal data from FPGA by high-speed interface；It is other from core as data processing from core, number
The processing of radar signal data is used for from core according to processing；
Data receiver opens up two storage regions for storing the radar signal data received, often from core in external DDR
A data processing opens up two storage regions for storing the radar signal data received from core in oneself core.
Compared with prior art, the present invention its remarkable advantage is：(1) core is individually opened up to respond in frequent GPIO
Break and receive data from outside, to improve the execution efficiency of CPU；(2) it avoids multiple cores for a long time to DDR bus access, subtracts
Overhead caused by few DDR bus access conflicts；(3) intercore communication is simultaneously using flag bit, IPC are interrupted, DMA data is removed
The technologies such as shifting ensure the reliability and rapidity that are communicated between multinuclear；(4) ping-pong structure is used from Nuclear Data storage, reduced
Data latency time.
Description of the drawings
Fig. 1 is the work flow diagram of main core in the present invention.
Fig. 2 be in the present invention data receiver from the work flow diagram of core.
Fig. 3 be in the present invention signal processing from the work flow diagram of core.
Specific implementation mode
The present invention is based on the moving-targets of multi-core DSP to detect (MTD) and CFAR detection (CFAR) system, the multinuclear
DSP includes a main core and more than two from core, wherein：
Main core is responsible for the process control of system processing radar signal, signal transmits, the letter of data-moving and tracking target
Breath generates, and the information for tracking target includes the information such as distance, speed；
More than two from core, individually open up one and interrupted from core dedicated for response external and pass through high-speed interface
(SRIO) radar signal data are received from FPGA, i.e., individually open up one from core as data receiver from core；It is other to be used for from core
The processing of radar signal data carries out moving-target detection and CFAR detection that is, in radar signal data to tracking target,
I.e. other from core as signal processing from core；
Data receiver opens two memory blocks from core in external DDR (Double Data Rate synchronous DRAM)
Domain, whole signal processings open up two storage regions from core in oneself core, that is, include the first storage region and the second memory block
Domain, to realize that ping-pong structure stores.
Embodiment
Seven cores are selected to build the present invention is based on the moving-target of multi-core DSP and CFAR detection system in multi-core DSP,
Middle determining core 0 is main core, and core 1 to core 5, from core, individually opens up core 6 as sound as the signal processing for handling radar signal data
It answers external interrupt and receives the data receivers of radar signal data from core.
In conjunction with Fig. 1, moving-target detection and constant false alarm are carried out to tracking target in radar signal data using the present invention
The process of detection is as follows：
The first step is initialized to main core and from core.The initialization of main core core 0 includes dsp system clock, DDR (double
Rate synchronization dynamic RAM), IPC (intercore communication) interrupt etc. configurations；The initialization of core 1 to core 5 includes intercore communication
Flag bit assigns initial value；The initialization of core 6 includes SRIO initial configurations, GPIO (general purpose I/O port) interruption configurations.Core 1 is to core 6
Corresponding flag bit is drawn high after each initialization completion from core, core 0 detects that core 1 initializes completion to core 6 is each from core
Flag bit enters normal mode of operation after drawing high.
Second step after FPGA often completes a wave radar signal data receiver, gives data receiver to send one from core core 6
GPIO rising edge interrupt signals, core 6 just carry out a SRIO reading behaviour after often receiving an interrupt signal in interrupting service function
Make, read radar signal data and is stored in external DDR.
Core 6 is read and the method for storing radar signal data is specially：Core 6, which is judging whether to receive always, when beginning comes
From the external interrupt signal of FPGA, after core 6 receives first interrupt signal, the external interrupt from FPGA is responded, and lead to
It crosses SRIO interfaces and reads data from outside.Core 6 judges that the data by reading are deposited by currently receiving the odd even of the number of data
Storage is in the first storage region or the second storage region.For example the first wave radar signal data of reading are stored in external DDR
In the first storage region, its flag bit drawn high after judging wave radar signal data storage, but core 6 does not stop at this time
It only receives and interrupts data, continue to read next wave radar signal data and store to the second storage region in external DDR.So
Cycle realizes ping-pong structure storage.The size for the radar signal data volume that core 6 is read per wave need according to reading rate and
The ends FPGA storage resources is reached an agreement on.The workflow of data receiver from core core 6 is as shown in Figure 2.
Third walk, during carrying out step 2, after main core core 0 detects that the flag bit of core 6 is drawn high, start into
Row DMA (immediate data storage) data-moving, i.e. core 0 move the radar signal data that core 6 is stored in external DDR successively
Core memory space of the core 1 to 5 each data processing of core from core.Detailed process is：Core 0 is first given and stores sky in core 1 to the core of core 5
Between the first storage region DMA radar signal data, then give each data processing second from the core memory space of core again
Storage region DMA radar signal data, realize ping-pong structure operation, main core core 0 after starting to move radar signal data just
It waits for core 1 to complete the IPC generated later in data processing to 5 each core of core always to interrupt.After main core core 0, which receives IPC, to interrupt,
Judge IPC interruptions come from which core in core 1 to core 5, and next wave number is subjected to radar data processing according to DMA to the core.
After main core core 0 detects that all data are completed by signal processing from core, the knot that is returned from core according to each signal processing
Fruit carries out the determination of the information such as target range, speed.The work flow diagram of main core core 0 is as shown in Figure 1.
In view of the core memory space resource of core 1 to core 5 is limited, and it is divided into two storage regions and does ping-pong structure
Storage, thus when a wave number according to it is very big when, it is impossible to will per wave number according to disposable whole DMA to each data processing from core；Together
When, it is contemplated that core 1 to core 5 do moving-target detection and when CFAR detection, between each range cell be it is independent, therefore,
Core 0 carries out data-moving when to data processing from core DMA data as unit of range cell.In the present embodiment, core 0 is every
Secondary DMA to data processing from the data of 3 range cells of core, data processing from core to the data of 3 range cells into
After target detection of taking action and CFAR detection processing, interrupted to 0 one IPC (intercore communication) of main core core, it is desirable that core 0 is from DDR
Continue the data of other 3 range cells of DMA.So cycle until all data from external DDR DMA to core 1 to core 5.
The workflow of 4th step, data processing from core is as shown in Figure 3.Core 1 to 5 each data processing of core receives master from core
After the data that core core 0DMA comes, moving-target detection and CFAR detection processing are carried out.CFAR detection processing uses unit
Average constant false alarm each side takes a protection location in measuring point to be checked, then the protection location in the left side taken left survey
And if the right side of the protection location on the right side taken measures to do and accumulates (taken point number is related with the false-alarm probability of selection),
It is more than the value reservation of thresholding after generation detection threshold compared with signal, the points less than thresholding are set to 0, and core 1 to core 5 is each believed
Number processing is from core by the target amplitude maximum value detected and corresponding location information back to the shared memory space of agreement.
If it is known that the velocity information of the radar target of last time can be according to last speed due to being the constant false alarm for doing speed dimension
Information suitably reduces speed unit CFAR detection detection range.
5th step, main core core 0 divide data as unit of range cell, then can obtain total range cell number
Mesh, then by core 1 to core 5 each from the range cell number assignment of core data to be treated to core 1 to core 5 each from core,
It then can further know that core 1 each needs DMA times completed number from core to core 5 during processing is provided.As main core core 0DMA
Data give 5 signal processings after the number of core all reaches the corresponding DMA number of each core, at this time the number of main core core 0
It has been completed according to work is moved, the mark after the completion of core processing of waiting 5 is drawn high.
It is after data processing has handled all data from core, respective handling result is suitable by the arrangement of core 1 to core 5
Sequence is stored in specified shared memory space, and the flag bit that respective Radar Signal Processing is completed is drawn high, and main core core 0 detects
To 5 data processings after the flag bit of core is all drawn high, the handling result of each core is read from shared memory space, is gone forward side by side
The information of line trace target generates, including the information such as the distance of target, speed.
In order to illustrate advantage of the present invention in calculating speed, using the method for the present invention, DSP selections TI company models are
The 8 core DSP of high-performance of TMS320C6678, data are transmitted to by the FPGA of the model XC7K325T of XILINX companies by SRIO
DSP, range cell take 59, interrupt receive 59*32*2*4=15014 data every time, 256 interruption one CPI numbers of composition
It is handled according to packet, total amount of data 59*8192*8.Core 1 is assigned to core 5 by 59 range cells, then core 1 is each to core 4
Core distributes to obtain 12 range cell data, and core 5 obtains 11 range cell data, by 3 range cells of each DMA, then core
1 is required to 4 data of DMA to core 5.It is handled using the method for the present invention, the CLOCK timeworkers from the CCS softwares of TI
It can be seen that only needing about 5.45ms in tool.The present invention only carries out monokaryon processing also under above-mentioned experimental situation with a core,
By CLOCK it can be seen that processing time is about 28.67ms.By comparing, the present invention is improved relative to monokaryon operation time
More than 5 times, the time of saving mostlys come from the realization of the reading and multinuclear algorithm of frequently interrupting data.
Claims (6)
1. a kind of moving-target and CFAR detection system based on multi-core DSP, which is characterized in that the multi-core DSP includes one
A main core and more than two from core, wherein：
Main core is responsible for the process control of system processing radar signal, signal transmits, the information life of data-moving and tracking target
At；
More than two from core, individually open up one from core as data receiver from core, data receiver is from core for responding
External interrupt simultaneously receives radar signal data by high-speed interface from FPGA；It is other from core as data processing at core, data
Manage the processing that radar signal data are used for from core；
Data receiver opens up two storage regions for storing the radar signal data received, per number from core in external DDR
Radar signal data of two storage regions for storing reception are opened up in oneself core from core according to processing；
It is to the process of the progress moving-target detection of tracking target and CFAR detection in radar signal data using the system：
Step 1 is initialized to main core and from core, and main core initialization includes dsp system clock, DDR, IPC interruption configuration；
Data processing includes that intercore communication flag bit assigns initial value from core initialization；Data receiver includes that SRIO initialization is matched from core initialization
It sets, GPIO interrupts configuration；All corresponding flag bit is drawn high after core initialization completion；When main core detect all from core at the beginning of
The flag bit that beginningization is completed enters normal mode of operation after drawing high；
Step 2 after FPGA often completes a wave radar signal data receiver, is given data receiver to send a GPIO from core and is risen
Along interrupt signal, data receiver just carries out a SRIO reading behaviour after often receiving an interrupt signal from core in interrupting service function
Make, read radar signal data and is stored in external DDR；
Step 3, during carrying out step 2, after main core detects that data receiver is drawn high from the flag bit of core, main core
In such a way that DMA data is moved by the radar signal data that data receiver is stored in from core in its external DDR move successively to
Core memory space of each data processing from core；
Step 4, each data processing carry out after the data that core receives that main core is transmitted in a manner of direct memory access
Moving-target detects and CFAR detection processing, and by handling result back to the shared memory space of agreement, then by respective thunder
The flag bit completed up to signal processing is drawn high；
Step 5, main core detect each data processing after the flag bit of core is drawn high, from the shared memory space of agreement
Handling result of each data processing from core is read, the information for line trace target of going forward side by side generates.
2. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 2
In, after data receiver receives first external interrupt signal from FPGA from core, the external interrupt is responded, and pass through
SRIO interfaces read data from outside；The first wave radar signal data of reading are first stored in external DDR by data receiver from core
In the first storage region, its flag bit drawn high after the wave radar signal data store, but do not stop receiving and interrupt
Data continue to read next wave radar signal data and store to the second storage region in external DDR.
3. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 3
In, main core is first transmitted from the first storage region of the core memory space of core in a manner of direct memory access to each data processing
Then radar signal data give each data processing to be visited from the second storage region of the core memory space of core directly to store again
The mode of asking transmits radar signal data；Main core start just to wait for always after moving radar signal data each data processing from
Core is completed the IPC generated later in data processing and is interrupted；Main core one receives one of data processing after the IPC of core interruptions,
Just by next wave number, direct memory access mode is transferred to the data processing from core according to this.
4. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 3
In, main core carries out data when to data processing from core transmission data in a manner of direct memory access as unit of range cell
It moves.
5. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 4
In, CFAR detection processing uses unit average constant false alarm, each side takes a protection location in measuring point to be checked, then in institute
If the right side of the left survey of the protection location in the left side taken and the protection location on the right side taken measures to do and accumulate, inspection is generated
It surveys after thresholding compared with radar signal, is more than the value reservation of thresholding, the points less than thresholding are set to 0.
6. the moving-target based on multi-core DSP and CFAR detection system as described in claim 1, which is characterized in that step 5
In, main core according to it in a manner of direct memory access transmits data to each data processing from the number of core to judge data-moving
Whether work is completed.
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| CN107885585A (en) * | 2016-09-30 | 2018-04-06 | 罗伯特·博世有限公司 | A kind of dynamic task scheduling device in multinuclear electronic control unit |
| CN107193230A (en) * | 2017-05-10 | 2017-09-22 | 合肥晟泰克汽车电子股份有限公司 | Car radar signal processing system and method |
| CN109587484B (en) * | 2017-09-28 | 2021-04-27 | 北京航空航天大学 | Multi-mode HEVC video encoder design method based on double-chip DSP |
| CN108717187A (en) * | 2018-05-23 | 2018-10-30 | 桂林电子科技大学 | Based on multinuclear digital signal processor through-wall radar motion target tracking imaging method |
| CN109324995A (en) * | 2018-08-24 | 2019-02-12 | 江西洪都航空工业集团有限责任公司 | A method of configuration DSP initialization |
| CN111830478B (en) * | 2020-07-08 | 2022-06-17 | 哈尔滨工程大学 | FPGA (field programmable Gate array) implementation method for MTD (maximum Transmission Difference) processing of LFMCW (Linear frequency modulation and continuous phase) radar |
| CN111858457B (en) * | 2020-07-15 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN113281709B (en) * | 2021-04-21 | 2022-08-02 | 中国海洋大学 | Radar performance evaluation method based on area coupling forecasting system |
| CN113325398B (en) * | 2021-05-13 | 2024-08-23 | 英博超算(南京)科技有限公司 | Application method of multi-core communication system of ultrasonic radar |
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