CN109324995A - A method of configuration DSP initialization - Google Patents
A method of configuration DSP initialization Download PDFInfo
- Publication number
- CN109324995A CN109324995A CN201810977634.0A CN201810977634A CN109324995A CN 109324995 A CN109324995 A CN 109324995A CN 201810977634 A CN201810977634 A CN 201810977634A CN 109324995 A CN109324995 A CN 109324995A
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- Prior art keywords
- dsp
- fpga
- initialization
- configuration
- reset
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The present invention relates to a kind of methods of configuration DSP initialization, and using Embedded FPGA+DSP framework, FPGA completes to include the steps that DSP power initialization, clock initialization, reset initialization and the configuration of DSP start-up mode to DSP initial configuration before DSP works.A kind of method of configuration DSP initialization of the invention can configure different DSP initial reguirements using the programmable characteristic of FPGA, can save external hardware resource, and realize fairly simple.
Description
Technical field
The invention belongs to electronic information application fields, and in particular to a method of configuration DSP initialization.
Background technique
With the rapid development of embedded technology, Embedded Application field is also increasingly extensive, also to embedded the relevant technologies
Propose increasingly higher demands.It is bigger to data demand in terms of Embedded Application field, especially data processing,
Processing result requires real-time high, mostly uses DSP solution on this basis.Dsp chip has powerful operational capability, place
Reason speed is fast, and can complete complicated calculating, can satisfy the demand in Embedded Application field.Common DSP is answered
It is developed with field, DSP initialization is usually problem to be solved in exploitation.For different application demands, need using not
With the DSP development platform of model, various demands also proposed to DSP initialization, so matching using agile and all-purpose type
Set the urgent need that initial method is also current Embedded Application field.
The method of hardware initialization or DSP power-up initializing is mostly used to write after the completion just currently for DSP initialization
Beginningization function solves.Hardware initialization needs the enough hardware supporteds of chip periphery, and software function initialization needs to call complicated
Function.
Summary of the invention
The purpose of the present invention:
The main object of the present invention is to configure inflexible problem, the present invention for dsp chip present in background technique
A kind of method for proposing flexible configuration DSP.
The technical scheme adopted by the invention is as follows:
A method of configuration DSP initialization, using Embedded FPGA+DSP framework, FPGA is completed before DSP works
To DSP initial configuration, specifically includes the following steps:
1) DSP power initialization
1.1) between FPGA and DSP, using chip UCD9222, the voltage of UCD9222 real-time monitoring DSP internal work,
The state of electric current, temperature feedback is forwarded to FPGA, FPGA calculates voltage, electric current, temperature according to the status information that DSP is fed back
Adjusted value automatically adjusts the supply voltage of DSP by UCD9222；
1.2) between FPGA and DSP, be also configured with the power supply chip of plurality of specifications, FPGA according to DSP timing diagram successively
Enable signal is issued to each power supply chip, each power supply chip is controlled and successively powers to DSP；
2) clock initializes
Clock chip CDCE62005 is set between FPGA and DSP, and FPGA passes through SPI interface configurable clock generator chip
The register of CDCE62005 generates the differential clocks output of two-way, completes the clock configuration that DSP initialization needs；
3) reset initialization
FPGA successively sends specific timing to DSP by IO, controls the reset of DSP；
4) DSP start-up mode configures
FPGA successively sends specific value to DSP by IO, controls the start-up mode of DSP.
It is characterized in that, the power supply chip of plurality of specifications, the kernel including DSP supplies voltage chips, and IO supplies voltage core
Piece, kernel storage supply voltage chips and part peripheral hardware supply voltage chips.
It is characterized in that, FPGA jumps sending enable signal by internal state machine during DSP power initialization, according to
Secondary starting kernel supplies voltage chips, and IO supplies voltage chips, kernel storage supply voltage chips, and part peripheral hardware supplies voltage core
Piece.
It is characterized in that, FPGA passes sequentially through IO to DSP and exports multiple reset signals, realization pair by writing state machine
The control of reset initialization sequence.
It is characterized in that, the multiple reset signal, is followed successively by electrification reset, warm reset resets completely, and reset state is defeated
Out.
It is characterized in that, FPGA successively sends specific value to the GPIO pin of DSP by IO, the starting mould of DSP is set
Formula, DSP obtain starting Configuration Values from corresponding external memory automatically, complete the starting of DSP.
Beneficial effects of the present invention:
A kind of method of configuration DSP initialization of the invention can configure different DSP using the programmable characteristic of FPGA
Initial reguirements can save external hardware resource, and realize fairly simple.
Detailed description of the invention
Fig. 1 DSP initializes schematic diagram
Fig. 2 DSP initializes detailed configuration schematic diagram
Fig. 3 DSP initialization process schematic diagram
Fig. 4 DSP initializes time diagram
Fig. 5 FPGA state of a control machine schematic diagram
Specific embodiment
Present invention is further described in detail with reference to the accompanying drawings of the specification.
The FPGA+DSP architecture design scheme used in the present invention, DSP starting correlative code are typically stored at external storage
In device, the initialization of DSP needs to obtain data from external memory and completes to start relevant configuration.FPGA of the present invention passes through control
GPIO pin relevant to DSP start-up mode, can be set the start-up mode of DSP, and DSP can be deposited from corresponding outside automatically
Starting Configuration Values are obtained in reservoir, complete the starting of DSP.
Characteristic of this method based on the erasable overprogram of FPGA, being capable of flexible configuration correlation DSP initial reguirements.This hair
The bright technical solution for solving Related Technical Issues and using are as follows: the method that flexible configuration DSP initialization is realized based on FPGA technology.It should
The content that initialization needs to complete includes completing to be powered on and initialized DSP, reset initialization, clock initialization, and start-up mode is matched
It sets.The present invention program uses the common FPGA+DSP framework in Embedded Application field, and FPGA is completed before DSP works to DSP
Initial configuration.
DSP must carry out initialization process before normal work, must assure that DSP power work is steady before working normally
Fixed, reset signal is working properly, and stable clock signal is reliable, and start-up mode configuration is correct.Since high-end DSP series is to power supply,
It resets, the signal accuracies timing requirements such as clock are higher, are all difficult to achieve the goal using external hardware and internal initialization function.This
Invention controls these signals using FPGA, can reach and be accurately controlled to these signals, the control sequential energy of generation
Enough work normally DSP.
The power supply type that the DSP family chip used in the present invention needs is relatively more, and power-on sequence is more complicated.
Power supply type mainly includes the kernel supply voltage of DSP, and IO supplies voltage, kernel storage supply voltage and the supply of part peripheral hardware
Voltage.This invention strictly designs power supply timing according to DSP service manual, and FPGA connects the enabled of each power module
Signal controls the boot sequence of each power module, successively starts line related.FPGA jumps completion pair by internal state machine
The control of related enable signal, successively starts core voltage, kernel storage supply voltage, and IO supplies voltage, other peripheral hardware voltages.
The clock accuracy that the DSP family chip used in the present invention needs is relatively high, and is differential clocks, therefore for clock
Initialization needs external special clock chip.Clock chip is configured using FPGA, meet demand can be configured
Differential clocks.FPGA by SPI interface to clock chip register configure different values reach different frequency requirements clock it is defeated
Out, flexible output clock can be configured by this method.
The DSP family chip used in the present invention needs to complete a series of reset initialization operations, including electrification reset, soft
It resets, resets completely, reset state output.FPGA successively enables each reset signal by writing state machine, realizes to reset
The control of initialization sequence.The FPGA+DSP architecture design scheme used in the present invention, DSP starting correlative code are typically stored at
In external memory, the initialization of DSP needs to obtain data from external memory and completes to start relevant configuration.FPGA of the present invention
By controlling GPIO pin relevant to DSP start-up mode, the start-up mode of DSP can be set, DSP can be automatically from corresponding
External memory in obtain starting Configuration Values, complete the starting of DSP.
The principle that DSP initialization is specifically configured in present example is as shown in Figure 1.FPGA is completed to DSP initialization four
The configuration of partial content mainly includes power sequence, clock sequence, homing sequence and Starting mode configuration etc..For TI company
Dsp chip TMS320C6655 series, which uses TI KeyStone multicore architecture, and dominant frequency can reach
1.25GHz has interface in peripheral configuration abundant.The power type needed inside the series DSP is relatively more, and inside powers on
Timing also have strict requirements.The power type that power sequence needs to configure includes DSP core voltage, is provided for storage array
Voltage, peripheral hardware reference voltage, DDR3 voltage, I/O voltage, PLL supply voltage etc..Homing sequence includes DSP electrification reset, soft multiple
Position, hard reset, CPU local reset etc..Clock sequence provides clock for DSP normal work, mainly includes Core Operational clock,
DDR3 work clock.Starting mode configuration DSP is started in which way, according to the difference of configuration peripheral hardware, present invention configuration
The Starting mode of DSP is the external EEPROM starting based on I2C.
As shown in Fig. 2, FPGA and DSP is interconnected by pin, realization configuration DSP is initialized specific implementation details of the present invention
Method.Some power supply chips are used when configuring power sequence, FPGA is completed by the enable signal of control power supply chip to power supply
The starting timing requirements of sequence.Particularly, the present invention reduces the power consumption of DSP, adopts to maximize the working efficiency for improving DSP
With the voltage adaptive adjustment technology inside DSP, using chip UCD9222 can according to the voltage of DSP internal work, electric current,
DSP core supply voltage is given in the feedback states such as temperature, automatic adjustment.For clock sequence, FPGA passes through SPI interface configurable clock generator core
The register of piece CDCE62005 generates the differential clocks output of two-way, completes the clock configuration that DSP initialization needs.For multiple
Bit sequence and Starting mode sequence, FPGA complete reset demand and Starting mode configuration by the timing of operation IO.
Configuration flow of the present invention is as shown in figure 3, power initialization is completed in configuration first, and secondly the initialization of completion clock, multiple
Bit sequence finally completes the configuration of Starting mode, completes the configuration that FPGA initializes DSP.The present invention configures specific timing and closes
System is as shown in figure 4, successively startup power supply sequence C VDD, CVDD1 first, and then clock configuration module is started to work, then successively
Start subsequent power sequence；Start to export clock, subsequent start-up homing sequence, including electrification reset after all power initiations
POR and completely reset RESETFULL signal；Finally starting configuration mode setting, is arranged the Starting mode of DSP.
Initialization timing requirements of the present invention using FPGA configuration DSP each unit module, the progress of FPGA adoption status machine
Control, may be implemented the accurate timing control to each initializing signal, and the control of particular state machine is as shown in Figure 5.It is wherein each
State is defined as follows:
SM_IDLE: the initial idle state of configuration DSP initialization.
SM_RST: the reset RST state of configuration DSP initialization.
SM_PMBS:PMBUS bus configuration UCD9222, generates corresponding power supply status.
SM_RST2: RST2 state is resetted.
SM_V1P5:1.5V starts configuration status.
SM_V075:0.75V starts configuration status.
SM_CLKG: differential clocks configuration status.
SM_PORWR: reset state, including electrification reset and complete reset state.
SM_PWORK: initialization completion status.
The configuration of each state provides corresponding configuration and completes flag bit after completing, state machine by detect the flag bit into
Row jumps to next state, passes through the timing of each state of delays time to control inside each state.Jump condition 1,3,5,7,9,
11,13,15 show that corresponding state complement mark is completed and given to Last status, that is, will jump to next state.It jumps
Turn condition 2,4,6,8,10,12,14,16,17 and show that internal delay units are not completed, does not provide corresponding complement mark,
State still rests on this state.It jumps condition 18 and shows that FPGA detects that DSP starts extremely, state machine jumps to configuration DSP
The initial idle state of initialization, FPGA re-start DSP initial configuration.
Claims (6)
1. a kind of method of configuration DSP initialization, using Embedded FPGA+DSP framework, FPGA completion pair before DSP works
DSP initial configuration, specifically includes the following steps:
1) DSP power initialization
1.1) between FPGA and DSP, using chip UCD9222, voltage, the electricity of UCD9222 real-time monitoring DSP internal work
The state of stream, temperature feedback is forwarded to FPGA, FPGA calculates voltage, electric current, temperature tune according to the status information that DSP is fed back
Whole value automatically adjusts the supply voltage of DSP by UCD9222；
1.2) between FPGA and DSP, it is also configured with the power supply chip of plurality of specifications, FPGA is according to DSP timing diagram successively to each
Power supply chip issues enable signal, controls each power supply chip and successively powers to DSP；
2) clock initializes
Clock chip CDCE62005 is set between FPGA and DSP, and FPGA passes through SPI interface configurable clock generator chip CDCE62005
Register, generate two-way differential clocks output, complete DSP initialization need clock configuration；
3) reset initialization
FPGA successively sends specific timing to DSP by IO, controls the reset of DSP；
4) DSP start-up mode configures
FPGA successively sends specific value to DSP by IO, controls the start-up mode of DSP.
2. a kind of method of configuration DSP initialization as described in claim 1, which is characterized in that the power supply chip of plurality of specifications,
Kernel including DSP supplies voltage chips, and IO supplies voltage chips, kernel storage supply voltage chips and the supply of part peripheral hardware
Voltage chips.
3. a kind of method of configuration DSP initialization as claimed in claim 2, which is characterized in that DSP power initialization process
In, FPGA jumps sending enable signal by internal state machine, successively starts kernel and supplies voltage chips, IO supplies voltage core
Piece, kernel storage supply voltage chips, part peripheral hardware supply voltage chips.
4. a kind of method of configuration DSP initialization as claimed in claim 3, which is characterized in that FPGA by writing state machine,
It passes sequentially through IO and exports multiple reset signals to DSP, realize the control to reset initialization sequence.
5. a kind of method of configuration DSP initialization as claimed in claim 4, which is characterized in that the multiple reset signal, according to
Secondary is electrification reset, and warm reset resets completely, reset state output.
6. a kind of method of configuration DSP initialization as claimed in claim 5, which is characterized in that FPGA is by IO successively to DSP
GPIO pin send specific value, the start-up mode of DSP is set, and DSP is obtained from corresponding external memory automatically and opened
Dynamic Configuration Values, complete the starting of DSP.
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| CN201810977634.0A CN109324995A (en) | 2018-08-24 | 2018-08-24 | A method of configuration DSP initialization |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112650090A (en) * | 2020-09-25 | 2021-04-13 | 合肥恒烁半导体有限公司 | MCU chip start mode selection circuit |
| CN114691227A (en) * | 2022-04-25 | 2022-07-01 | 紫光计算机科技有限公司 | Multi-mode starting method and device of BIOS (basic input output System), electronic equipment and storage medium |
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Cited By (3)
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| CN114691227A (en) * | 2022-04-25 | 2022-07-01 | 紫光计算机科技有限公司 | Multi-mode starting method and device of BIOS (basic input output System), electronic equipment and storage medium |
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Application publication date: 20190212 |
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