CN101515240A - Digital signal processor loading method, electronic device and electronic system - Google Patents
Digital signal processor loading method, electronic device and electronic system Download PDFInfo
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- CN101515240A CN101515240A CNA2009101326549A CN200910132654A CN101515240A CN 101515240 A CN101515240 A CN 101515240A CN A2009101326549 A CNA2009101326549 A CN A2009101326549A CN 200910132654 A CN200910132654 A CN 200910132654A CN 101515240 A CN101515240 A CN 101515240A
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Abstract
The embodiment of the invention discloses a digital signal processor loading method, which includes steps that DSP receives signal for noticing the DSP to execute initialization sent by field programmable gate array (FPGA); the DSP acquires reset configuration word (RCW) stored in the FPGA according to the received signal for noticing the DSP to execute initialization; and the DSP executes hardware resource configuration for the DSP according to the acquired RCW. In the technical solution of the present invention, the DSP acquires the RCW needed to be loaded through the RCW stored in the memory cell in the FPGA, because the FPGA can be controlled by the CPU, the RCW of the memory cell stored in the FPGA can be updated through control and remote control of the CPU, so that, memory cell is not needed to be added to supply RCW for the DSP, and production cost is reduced.
Description
Technical field
The present invention relates to field of computer technology, be specifically related to a kind of digital signal processor loading method, electronic installation and electronic system.
Background technology
Growing along with digital circuit, common field programmable gate array (the FPGA that constitutes by basic gate circuit and trigger, Field Programmable Gate Array), it is fast to have speed with it, characteristics such as applying flexible, increasing and central processing unit (CPU, Center Process Unit), digital signal processor (DSP, Digital Signal Processing) are formed the high-speed digital circuit system.DSP in this type systematic and FPGA great majority all have CPU to load configuration, just can use.Some DSP needs loading reset configuration words (RCW, Reset Configuration Word) before using after powering on, the purpose that loads RCW is hardware resources such as clock on the configuration DSP and interface.
The method that existing DSP loads RCW is to increase an independent memory device, as EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM, Electrically Erasable Programmable Read-Only Memory), the RCW that needs are loaded is stored among the EEPROM, behind startup DSP, DSP passes through IC bus (I from EEPROM
2C, Intel-Integrated Circuit bus) or Serial Peripheral Interface (SPI, Serial Peripheral Interface) etc. get access to RCW in the serial line interface, described referring to Fig. 1, behind starter gear in the prior art, the DSP in the device obtains the simplified schematic diagram of the RCW among the EEPROM.Device (perhaps digital circuitry) with the Flash of flash memory shown in figure module, EEPROM module, CPU module, FPGA module and DSP module is after powering on, the CPU module starts, when the reset signal POR that exports in the CPU module is high level, the DSP module is a high level signal according to receiving POR, obtain the RCW of storage from the EEPROM module, the interface of EEPROM module and DSP module communication can be I
2C or SPI etc.; According to the configuration of the RCW execution of obtaining to hardware resources such as clock among the DSP and interfaces.Flash module and FPGA module do not participate in DSP and load RCW among Fig. 1, and the FPGA module is accepted the control of CPU by local bus (Local Bus).
Adopt this DSP to load the method for RCW, because the data of storing among the EEPROM can not be controlled by CPU, therefore, the RCW that updates stored among the EEPROM is very inconvenient, and is unfavorable for remote upgrade RCW.And independent EEPROM module increases the cost of process units, is unfavorable for the miniaturization of equipment.
Summary of the invention
The embodiment of the invention provides a kind of digital signal processor DSP loading method and electronic installation, and making does not need independent EEPROM module that the RCW of needs loading is provided for DSP.
The embodiment of the invention provides a kind of digital signal processor DSP loading method, comprising:
The notice DSP that DSP receives the on-site programmable gate array FPGA transmission carries out initialized signal;
Described DSP carries out initialized signal according to the described notice DSP that receives, and obtains the reset configuration words RCW that stores among the described FPGA;
Described DSP carries out the configuration to the hardware resource of described DSP according to the described RCW that obtains.
The embodiment of the invention also provides a kind of electronic installation, comprising:
Receiving element is used to receive the notice that the phenomenon programmable gate array FPGA sends and carries out initialized signal;
Acquiring unit is used for carrying out initialized signal according to the described notice that receives, and obtains the reset configuration words RCW that stores among the described FPGA;
Dispensing unit is used for the RCW that obtains according to described, carries out hardware resource is disposed.
The embodiment of the invention also provides a kind of electronic system, comprising:
Digital signal processor is used to receive the notice that the phenomenon programmable gate array FPGA sends and carries out initialized signal; Carry out initialized signal according to the described notice that receives, obtain the reset configuration words RCW that stores among the described FPGA; According to the described RCW that obtains, carry out hardware resource is disposed.
The RCW that stores in the storage unit among the FPGA that DSP passes through in the embodiment of the invention obtains the RCW that needs loading.Because FPGA can control by CPU, therefore, be stored in that the RCW on the storage unit can be upgraded by CPU control among the FPGA, and realize Long-distance Control.Need not increase storage unit separately provides RCW for DSP, has reduced production cost.
Description of drawings
Fig. 1 be when DSP loads RCW in the prior art signal flow in the device to simplified schematic diagram;
Fig. 2 is the general flow chart of a kind of DSP loading method of providing of the embodiment of the invention one;
Fig. 3 be in the embodiment of the invention two device in signal flow to simplified schematic diagram;
Fig. 4 is the general flow chart of a kind of DSP loading method of providing of the embodiment of the invention two;
Fig. 5 is a kind of electronic installation logical diagram that the embodiment of the invention three provides;
Fig. 6 is a kind of electronic installation logical diagram that the embodiment of the invention four provides;
Fig. 7 is a kind of electronic system logical diagram that the embodiment of the invention five provides.
Embodiment
The embodiment of the invention provides a kind of digital signal processor DSP loading method.The embodiment of the invention also provides corresponding device thereof and system.Below be elaborated respectively.
Embodiment one
Present embodiment provides a kind of digital signal processor DSP loading method, and as shown in Figure 2, this method comprises:
The notice DSP that steps A 1:DSP receives the on-site programmable gate array FPGA transmission carries out initialized signal;
Steps A 2:DSP carries out initialized signal according to receiving notice DSP, obtains the reset configuration words RCW that stores among the FPGA;
Steps A 3:DSP carries out the configuration to the hardware resource of this DSP according to the RCW that obtains.
By of the explanation of above steps A 1 to steps A 3, this DSP has realized the loading to self, promptly to self the configuration of hardware resource, the embodiment of the invention has realized a kind of digital signal processor DSP loading method, by this method, do not need to increase independent memory device, as EEPROM etc., store RCW, but in FPGA, store RCW by obtaining.Because FPGA can control by CPU, therefore, update stored in that the RCW on the storage unit can be upgraded by CPU control among the FPGA, and Long-distance Control.Need not increase storage unit separately provides RCW for DSP, has reduced production cost.
Embodiment two
The embodiment of the invention provides a kind of digital signal processor DSP loading method.For the ease of understanding a kind of DSP loading method that the embodiment of the invention provides, at first to a kind of CPU module that comprises at least shown in Figure 3, the Flash module, the device of FPGA module and DSP module is done explanation.Want to make FPGA module and DSP module operate as normal, need respectively DSP module and FPGA module to be loaded, just can be so that this device can operate as normal.Communicate by local bus (Local Bus) between CPU module and the FPGA module in this device, in this FPGA, realize having I by programming in logic
2The EEPROM of C or SPI interface, the EEPROM among this FPGA passes through I
2C or SPI interface are communicated by letter with DSP, and after FPGA finished configuration to self, the RCW with storage was loaded among the DSP again, realize that DSP loads RCW.
The explanation of the above relevant embodiment of the invention of following basis is done explanation to a kind of method that the embodiment of the invention provides.Referring to shown in Figure 4, this method comprises:
Step 1: device powers on;
Step 2: the FPGA in the device downloads to logical code and the RCW that storage unit is preserved in the device by CPU;
Wherein, it will be appreciated that FPGA is after powering on, need by CPU from the storage unit of CPU control get access to programming code and relevant configuration information etc., after power down, it is blank that FPGA recovers, and the internal logic relation disappears, therefore, FPGA can use repeatedly, and can realize by programming in logic that in FPGA the EEPROM of multiple interfaces, this multiple interfaces can be SPI or I
2C etc., this is the advantage that FPGA has flexible use.Storage unit in this device can be flash memory Flash.
Wherein, the communication interface between CPU and the FPGA can be local bus Local Bus.
Step 3:FPGA is according to the logical code and the RCW that obtain, generate at least one logic module, wherein, have at least one to be the memory module that stores RCW in the logic module, this memory module can be EEPROM or the random access memory memory modules such as (RAM, Random AccessMemory) that realizes among the FPGA;
Step 4:FPGA sends notice DSP and carries out initialized signal;
Wherein, FPGA sends notice DSP to carry out initialized signal specifically can be to the POR pin on the DSP by FPGA output high level signal.Need to prove, DSP be not in reset mode before the configuration always, this is that the signal that the POR pin receives is a low level signal, when the signal that receives when the POR pin is high level signal, can think that this DSP is activated, this DSP carries out loading RCW and is configured according to the RCW that loads.Also need to understand the time, need upgrade DSP when CPU or other external controls and go up the RCW that loads, when perhaps again DSP being configured, the level of exporting to the last POR pin of DSP will place low level after a period of time, become high level, so just can control DSP and follow RCW again, carry out configuration.
The notice DSP that step 5:DSP receives the FPGA transmission carries out initialized signal, carries out initialized signal according to the above-mentioned notice DSP that receives, and obtains the RCW that stores among the FPGA;
Wherein, RCW can be stored in the memory modules such as EEPROM among the FPGA or RAM.The interface of transmission RCW can SPI or I between DSP and the FPGA
2Interfaces such as C.
Step 6:DSP carries out the configuration to the hardware resource of this DSP according to the RCW that obtains.
Wherein, DSP is according to the RCW that obtains in the step 6, and the configuration of carrying out hardware resource mainly comprises: the configuration of hardware resources such as clock and interface.
By of the explanation of above step 1 to step 6, the embodiment of the invention has realized a kind of digital signal processor DSP loading method, by this method, do not need to increase independent memory device in the device, as EEPROM etc., store RCW, but by in FPGA, setting up the storage unit of storage RCW, the RCW that stores in the storage unit among the FPGA that DSP in the device passes through obtains the RCW that needs loading.Because FPGA can control by CPU, therefore, update stored in that the RCW on the storage unit can be upgraded by CPU control among the FPGA, and Long-distance Control.Need not increase storage unit separately provides RCW for DSP, has reduced production cost.
Need to prove that also for the method that makes the embodiment of the invention provide is more stable, assurance device can operate as normal, this method can also comprise before the step 6 after step 5:
Step 7:DSP judges whether the RCW that loads is correct, if, enter step 6, if not, enter step 5.
Need to prove that RCW is usually according to the storage of certain form, therefore, DSP will satisfy when loading RCW that certain time sequence requires.If the temporal order mistake then loads normally wrong.Make this DSP when loading RCW by increasing step 7, can find the RCW mistake that loads as early as possible, and select to reload, to avoid follow-up mistake.
The method that the embodiment of the invention provides can also comprise after step 6:
Step 8:DSP exports configuration result, and this configuration result is transmitted to CPU by FPGA;
Step 9:CPU receives configuration result, judges according to configuration result whether configuration is successful, and if not, CPU notice FPGA enters step 4.
Need to prove that DSP carries out after the configuration to self according to the RCW that obtains, can export configuration result, this configuration result is generally clock signal, and CPU can judge whether this DSP can move and whether the frequency of operation of this DSP is correct according to the clock signal of output.If CPU judges that the result of configuration is a mistake, can notify FPGA to send notice DSP and carry out initialized signal to DSP, after FPGA receives this notice, execution in step 4.Also can task be that CPU controls DSP indirectly by FPGA and reloads RCW.
The method that present embodiment provides owing to increased step 8 and step 9, makes whether the DSP judgement is successful according to the configuration that the RCW that loads carries out, thereby makes DSP intelligent more, better provides service for the user.
Embodiment three
The embodiment of the invention provides a kind of electronic installation, participates in shown in Figure 5ly, comprising: receiving element 101, acquiring unit 102 and dispensing unit 103.This electronic installation can also comprise: the output unit 104 and/or first judging unit 105.
Wherein, receiving element 101 is used to receive the notice that FPGA sends and carries out initialized signal;
Wherein, receiving element 101 can be by IC bus I
2Interfaces such as C or Serial Peripheral Interface SPI, the notice that receives the FPGA transmission is carried out initialized signal.
Acquiring unit 102 is used for carrying out initialized signal according to the above-mentioned notice that receives, and obtains the RCW that stores among the above-mentioned FPGA;
Explanation by above a kind of electronic installation that the embodiment of the invention is provided, this electronic installation obtains RCW from FPGA, because CPU can be directly the RCW of the storage among the FPGA is upgraded, make this electronic installation to upgrade RCW by CPU control, having under the environment of FPGA, need not increase storage unit separately provides RCW for DSP, has reduced production cost.
In order to make this electronic installation possess better reliability, this electronic installation can also comprise:
First judging unit 105 is used to judge whether the described RCW that obtains correct, if, send be judged as be the result to dispensing unit 103, if not, send and be judged as result not to acquiring unit 102;
By increasing by first judging unit 105, make that this charged sub-device can be more intelligent, better provide service for the user.It will be appreciated that a kind of electronic installation that the above embodiment of the invention provides can be a digital signal processor DSP.
Embodiment four
The embodiment of the invention provides a kind of electronic installation, referring to shown in Figure 6, the electronic installation that provides among the embodiment three has been provided this electronic installation, being the electronic installation that provides of embodiment three, one ingredient of the electronic installation that provides in the present embodiment is provided, the electronic installation that the embodiment of the invention provides comprises: storage unit 10, central processor CPU unit 20, on-site programmable gate array FPGA unit 30 and digital signal processor DSP unit 40.
Wherein, storage unit 10 is used for logical code and the RCW of stored configuration FPGA, and storage unit 10 can be flash memory Flash;
Wherein, need to prove that FPGA unit 30 comprises register cell 301 at least, this register cell 301 is used to store RCW.
Wherein, need to prove also between CPU element 20 and the FPGA unit 30 to communicate that the interface of communicating by letter between FPGA unit 30 and the DSP unit 40 can be I by Local Bus
2C interface, or interface such as SPI.
Also need to prove, CPU element 20 also is used to receive the configuration result of DSP unit 40 transmissions of transmitting FPGA unit 30, configuration result according to the DSP unit 40 that receives, judge whether the configuration in the DSP unit 40 is successful, if finish the operating process that relevant DSP loads and disposes, if not, notice FPGA unit 30 sends notice DSP unit 40 and carries out initialized information, promptly passes through control DSP unit 40 indirectly, FPGA unit 30 by CPU element 20.
Explanation by above a kind of electronic installation that the embodiment of the invention is provided, in this device by in the FPGA unit, generating register cell, store RCW, the DSP unit obtains RCW from the FPGA unit, and does not need to increase the cell stores RCW that is independent of the FPGA unit.Because the FPGA unit can be controlled by CPU element, therefore, can upgrade by CPU element control according to being stored in the RCW that stores in the FPGA unit, and Long-distance Control, simultaneously, also reduced production cost.
Embodiment five
Present embodiment provides a kind of electronic system, comprises in this electronic system: digital signal processor DSP 402 can also comprise on-site programmable gate array FPGA 302, memory storage 102 and central processing unit CPU 202.
Wherein, DSP402 is used to receive the notice that the phenomenon programmable gate array FPGA sends and carries out initialized signal; Carry out initialized signal according to the described notice that receives, obtain the reset configuration words RCW that stores among the described FPGA; According to the described RCW that obtains, carry out hardware resource is disposed.
On-site programmable gate array FPGA 302 is used for logical code and reset configuration words RCW that the deriving means storage unit is preserved; According to logical code that obtains and RCW, generate at least one logic module, have at least one to be the memory module that stores RCW in the described logic module; Send described notice and carry out initialized signal.
Central processing unit CPU 202, the logical code and the RCW that are used for configuration FPGA that described storage unit is stored send to described FPGA.
Wherein, DSP unit 40 among the DSP402 in this electronic system, FGPA302, memory storage 102, CPU202 and the embodiment four, FPGA unit 30, storage unit 10, CPU20 are corresponding similar, the explanation of detailed description in can reference example four.
By the explanation of above a kind of electronic system that the embodiment of the invention is provided, by in FPGA, generating register cell, store RCW in this system, DSP obtains RCW from the FPGA unit, and does not need to increase the cell stores RCW that is independent of FPGA.Because FPGA can be controlled by CPU element, therefore, can upgrade by CPU element control according to being stored in the RCW that stores among the FPGA, and Long-distance Control, simultaneously, also reduced production cost.
One of ordinary skill in the art will appreciate that all or part of step in the whole bag of tricks of the foregoing description is to instruct relevant hardware to finish by program, this program can be stored in the computer-readable recording medium, and storage medium can comprise: ROM, RAM, disk or CD etc.
More than a kind of digital signal processor DSP loading method and electronic installation that the embodiment of the invention provided are described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (16)
1, a kind of digital signal processor DSP loading method is characterized in that, comprising:
The notice DSP that DSP receives the on-site programmable gate array FPGA transmission carries out initialized signal;
Described DSP carries out initialized signal according to the described notice DSP that receives, and obtains the reset configuration words RCW that stores among the described FPGA;
Described DSP carries out the configuration to the hardware resource of described DSP according to the described RCW that obtains.
2, method according to claim 1 is characterized in that, after the RCW that stores among the described FPGA of obtaining, described method also comprises:
Described DSP judges whether the described RCW that obtains is correct, if carry out described according to the configuration of described RCW execution of obtaining to the hardware resource of described DSP.
3, method according to claim 2 is characterized in that, described DSP judge the RCW that obtains whether the right judgement result carry out the RCW that stores among the described FPGA of obtaining once more when negating.
4, according to each described method of claim 1 to 3, it is characterized in that, the RCW that described basis is obtained, after the configuration of execution to the hardware resource of described DSP, described method also comprises:
Described DSP output configuration result is transmitted to described CPU by described FPGA.
5, method according to claim 1 is characterized in that, the RCW that stores among the described FPGA of obtaining specifically comprises:
By the IC bus I between DSP and the FPGA
2C or Serial Peripheral Interface SPI obtain the RCW that stores among the FPGA.
6, a kind of electronic installation is characterized in that, comprising:
Receiving element is used to receive the notice that the phenomenon programmable gate array FPGA sends and carries out initialized signal;
Acquiring unit is used for carrying out initialized signal according to the described notice that receives, and obtains the reset configuration words RCW that stores among the described FPGA;
Dispensing unit is used for the RCW that obtains according to described, carries out hardware resource is disposed.
7, electronic installation according to claim 6 is characterized in that, described electronic installation also comprises:
First judging unit is used to judge whether the described RCW that obtains correct, if, send be judged as be the result to described dispensing unit, if not, send and be judged as result not to described acquiring unit.
According to each described electronic installation of claim 6 to 7, it is characterized in that 8, described receiving element is by IC bus I
2C or Serial Peripheral Interface SPI, the notice that receives described FPGA transmission is carried out initialized signal.
9, electronic installation according to claim 8 is characterized in that, described device also comprises:
The on-site programmable gate array FPGA unit is used for logical code and reset configuration words RCW that the deriving means storage unit is preserved; According to logical code that obtains and RCW, generate at least one logic module, have at least one to be the memory module that stores RCW in the described logic module; Send described notice and carry out initialized signal.
10, electronic installation according to claim 9 is characterized in that, described device also comprises:
Storage unit is used for the logical code and the RCW of stored configuration FPGA unit;
The central processor CPU unit, the logical code and the RCW that are used for configuration FPGA unit that described storage unit is stored send to described FPGA unit.
11, electronic installation according to claim 10 is characterized in that, described electronic installation also comprises:
Output unit is used to export configuration result and gives described FPGA unit;
Described FPGA unit also is used to receive described configuration result, and described configuration result is sent to described CPU element;
Described CPU element also is used to receive described configuration result, according to described configuration result, judges whether configuration is successful, and if not, described CPU element notice FPGA carries out described FPGA unit transmission notice in the unit and carries out initialized signal to described receiving element.
12, a kind of electronic system is characterized in that, comprising:
Digital signal processor is used to receive the notice that the phenomenon programmable gate array FPGA sends and carries out initialized signal; Carry out initialized signal according to the described notice that receives, obtain the reset configuration words RCW that stores among the described FPGA; According to the described RCW that obtains, carry out hardware resource is disposed.
13, electronic system according to claim 12 is characterized in that, described electronic system also comprises:
Field programmable gate array is used for logical code and reset configuration words RCW that the deriving means storage unit is preserved; According to logical code that obtains and RCW, generate at least one logic module, have at least one to be the memory module that stores RCW in the described logic module; Send described notice and carry out initialized signal.
14, electronic system according to claim 13 is characterized in that, described digital signal processor is by IC bus I
2C or Serial Peripheral Interface SPI, the notice that receives described FPGA transmission is carried out initialized signal.
15, electronic system according to claim 13 is characterized in that, described electronic system also comprises:
Memory storage is used for logical code and the RCW of stored configuration FPGA;
Central processing unit CPU, the logical code and the RCW that are used for configuration FPGA that described storage unit is stored send to described FPGA.
16, electronic system according to claim 15 is characterized in that, described digital signal processor also is used to export configuration result and gives described FPGA;
Described FPGA also is used to receive described configuration result, and described configuration result is sent to described CPU;
Described CPU also is used to receive described configuration result, according to described configuration result, judges whether configuration is successful, and if not, described CPU notice FPGA carries out described FPGA unit transmission notice and carries out initialized signal to described digital signal processor.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890635A (en) * | 2011-07-20 | 2013-01-23 | 中兴通讯股份有限公司 | Method and device for loading digital signal processor |
| CN105630120A (en) * | 2014-11-03 | 2016-06-01 | 普天信息技术有限公司 | Processor hardware configuration word loading method and device |
| CN109324995A (en) * | 2018-08-24 | 2019-02-12 | 江西洪都航空工业集团有限责任公司 | A method of configuration DSP initialization |
| CN111158761A (en) * | 2019-11-28 | 2020-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
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2009
- 2009-03-30 CN CNA2009101326549A patent/CN101515240A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102890635A (en) * | 2011-07-20 | 2013-01-23 | 中兴通讯股份有限公司 | Method and device for loading digital signal processor |
| CN102890635B (en) * | 2011-07-20 | 2018-01-30 | 中兴通讯股份有限公司 | The loading method and device of a kind of digital signal processor |
| CN105630120A (en) * | 2014-11-03 | 2016-06-01 | 普天信息技术有限公司 | Processor hardware configuration word loading method and device |
| CN105630120B (en) * | 2014-11-03 | 2019-03-08 | 普天信息技术有限公司 | A kind of method and device of loading processing device hardware configuration word |
| CN109324995A (en) * | 2018-08-24 | 2019-02-12 | 江西洪都航空工业集团有限责任公司 | A method of configuration DSP initialization |
| CN111158761A (en) * | 2019-11-28 | 2020-05-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
| CN111158761B (en) * | 2019-11-28 | 2022-12-06 | 中国航空工业集团公司西安航空计算技术研究所 | Method for rapidly loading power-on configuration information of PowerPC processor through FPGA |
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